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Publication numberUS3760582 A
Publication typeGrant
Publication dateSep 25, 1973
Filing dateNov 23, 1970
Priority dateNov 23, 1970
Also published asCA946169A1, DE2156808A1, DE2156808B2
Publication numberUS 3760582 A, US 3760582A, US-A-3760582, US3760582 A, US3760582A
InventorsCarbtree W, Thiess G
Original AssigneeHmw Industries
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Electronic timepiece with power conserving features
US 3760582 A
Abstract
An electronic timepiece including an integral energy source. The circuitry of the timepiece is implemented using solid state devices arranged to maximize the useful life of the energy source by conserving energy.
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Description  (OCR text may contain errors)

White States atent r1 1 Thiess et al.

ELECTRONIC TIMEIIECE WITH POWER CONSERVING FEATURES Inventors: George H. Thiess, Willie A.

Crabtree, both of Dallas, Tex.

Assi gnee HMW Industries, Inc. (formerly Hamilton Watch Company), Lancaster. Pa.

Filed: Nov. 23, 1970 Appl. No.: 92,027

US. Cl 58/50 R, 58/23, 58/33, 58/855 Int. Cl. G04c 3/00, G04b 19/00 Field of Search 58/33, 23 R, 23 A, 58/34, 23 C, 5 DR, 85.5; 235/92 T, 92 EA References Cited UNITED STATES PATENTS 6/1972 Bergey et a1. 58/855 {451 Sept. 25, r973 3,576,099 4/1971 Walton 58/50 OTHER PUBLICATIONS Hamilton Watch Company, Timely Topics, May 6, 1970, pp. 1-4.

Primary Examiner-Richard B. Wilkinson Assistant Examiner-Edith C. S. Jackmon AttorneyRobert E. LeBlanc, Henry Shur, Leonard F. Stoll, Richard G. Besha and Donald C. Casey An electronic timepiece including an integral energy source. The circuitry of the timepiece is implemented using solid state devices arranged to maximize the useful life of the energy source by conserving energy.

ABSTRACT 17 Claims, 7 Drawing Figures A PATENIEDSEPZSIM F'IG.5A

J 8+ 7 OPERATE SHEET 1 III A LEVEL DETECTOR ll'l DUTY CYCLE CONTROLLER II T '2 FREQUENCY OSCILLATOR DIVIDER W DECODE M 8: DISPLAY DISPLAY SWITCH DUTY CYCLE CONT ROLLER LIGHT SENSORS CONTROL CIRCUW B OCOUNTE RS /9 0 SISET CONTROLLER 11v VENTORS WILLIE A. CRABTREE GEORGE H. THEISS PATENTEDSEPZBIW sum 3 m mm m hu PATENTEDSEP25|975 3,760,582

saw u or a r 436 2 l Wn W420] 4oo l L l? DISPLAY DECODER a CONTROL DISPLAY ELECTRONIC TIMEPIECE WITH POWER CONSERVING FEATURES BACKGROUND OF THE INVENTION Prior to the present invention, the so-called electronic wrist watches have been combination mechanical-electrical devices with mechanical arrangements for indicating time. It is recognized that a relatively simple timepiece can be achieved utilizing a suitable high frequency source, such as an oscillator or the like, coupled to a suitable counter which produces output signals at a prescribed rate, in sequence to effect a time keeping operation. The timepieces which have utilized digital techniques and electroluminescent displays either have not been powered by self-contained energy source or have been required to operate for only a limited period of time. Although wrist watches using digital techniques and electroluminescent displays have been suggested, power requirements in excess of those available for operation over substantial periods of time have precluded practical devices. Any truly utilizable electronic wrist watch must be sufficiently small as to be adapted to the operators handling and wearing ease but not require replacement of the energy source at frequency intervals.

SUMMARY OF THE INVENTION The subject invention provides an electronic timepiece which is constructed in micro-electronic form and has an illuminated digital output display. The output display provides hours, minutes and seconds readout. The circuitry includes operator control demand apparatus wherein the output display is selectively operable and illuminated. Since the display represents the greatest energy drain, a significant energy saving is accomplished. Moreover, when the watch is commanded to produce a readout display, a power control responsive to ambient light conditions selectively determines the energy supplied to the display. Consequently, unnecessary energy is not expended by supplying energy to the display in a dimly lit environment at the same level as in lightly lit conditions, conserving energy and providing a superior display.

Selectively operated switches are provided to permit the rapid setting of the correct time. Other logic control circuits are utilized to sequentially display the minutes and hours readout for a predetermined time and the seconds readout at an appropriate time. In addition, other circuitry as well as advantages thereof will be described in detail hereinafter whereby power conservation is continuously effected.

DESCRIPTION OF THE DRAWINGS Many objects and advantages of the invention will become apparent to those skilled in the art as a detailed description of a preferred embodiment of the invention unfolds with reference to the drawings wherein like reference numerals refer to like parts and in which:

FIG. 1 is a schematic representation of the external view of the watch housing and display face;

FIG. 2 is a block diagram of the electronic circuitry utilized in the invention;

FIGS. 3a and 3b are detailed logic diagrams of the circuitry utilized in the instant invention;

FIG. 4 is a group of curves illustrating control of the duty cycle of power supplied to an electroluminescent display;

FIG. 5 schematically illustrates an alternative control of the display intensity; and,

FIG. 5a illustrates a modification of the circuit of FIG. 5.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, there is shown a representation of the electronic watch in accordance with the preferred embodiment of the invention. The configuration shown in FIG. l is illustrative only and is not meant to be limitative. Typically, housing 1 for the timepiece may have a substantially oval configuration. Suitable means may be provided for attaching a wristband to the watch. The internal circuit portions of the watch may be mounted on a single circuit board which is mounted in-housing 1 along with a suitable integral power source such as a battery. The display or time readout is viewed through a protective covering 2.

The readout display comprises a plurality of digital representations, for example, in the form of pairs of 7-bar arrays 3a, 3b and 3c. The particular stylization or arrangement of the digital representations is not critical to the invention. The readout portion comprising 30 represents the hours read out. Likewise, the minutes readout is provided by array 3b. The seconds readout is provided by array 3a. Covering 2 is preferably formed to define a band pass filter which is transparent only to the wavelength of light emitted by the readout display, thereby enhancing legibility of the display. In accordance with the preferred embodiment, the readout was defined by light emitting diodes which emit red light. The cover 2 was of red plexiglas with a thin layer of transparent bluish-red paint on the undersurface. Preferably, the upper portion of the case underlying the cover is painted black to reduce reflected light and provide further enhancement.

A master control or operate switch 4, for example, a push button, is provided on the outer surface of the watch. In order to effect a readout of the time in hours and minutes, the operator momentarily depresses button 4, thereby energizing and activating the circuit so that the appropriate readout is displayed by the arrays 3b and 3c for a predetermined time interval. If switch 4 is maintained depressed, the array 3a indicating seconds will be energized and remain energized so long as the switch 4 is depressed.

Pushbutton switches 7 and 8 are utilized in the operation of setting the watch to a desired time. These pushbuttons may be located on the reverse side of the watch if desired. In addition, light sensors 5, of which three are shown for illustration, are mounted on the watch face. These light sensors control the power supplied to the display in accordance with ambient light conditions to minimize power drain and provide a superior display.

Referring now to FIG. 2 of the drawings, there is shown a block diagram of the circuitry of the preferred embodiment of the invention in which a basic time reference is provided by an oscillator l 1 which can be any suitable, stable oscillator such as a crystal controlled oscillator or the like. The relatively high frequency output signal of oscillator 11 is supplied to frequency divider 12 which can be suitably a conventional frequency divider of the type well known in the art. It will be noted, in this regard, that greatest accuracy can be obtained if the oscillator functions at a relatively high frequency such as 32,768 Hz.

Frequency divider 12 divides the frequency provided by the oscillator 11 the required number of times to provide a plurality of output frequencies. In accordance with the preferred embodiment disclosed herein, the frequency divider 12 produces 6 different output frequencies. As will be described in greater detail with reference to FIGS. 30 3b of the drawings, different ones of the output frequencies are supplied to the duty cycle controller 13 and to the operate and set controller 15.

The operate and set controller 15 applies pulses to the counters 9 which includes three individual counters each having outputs connected through a display and control 16 to the decoder and display 17. It is important to note that the supply voltage B+ is applied from the source only to the oscillator 11, the frequency divider 12, the counters 9 and a portion of the operate and set controller 15 except when one or more of the switches 4, 7 and 8 is operated. A substantial saving in power is thereby effectuated.

The light sensors can typically be light sensitive transistors which detect the ambient light and supply appropriate signals to the duty cycle controller 13. Duty cycle controller 13 supplies appropriate signals to the switch circuit 18 responsive to a signal from the operate and set controller 15 that one of the switches 4, 7 and 8 has been operated. The switch circuit 18 controls display control 16 to permit counter output information to be supplied to the decoder and display 17 and provides power to the decoder and display 17 in accordance with the environmental light level so that the display is energized for predetermined duty cycle and time periods. Such is important in that the display is a major source of power drain. In addition to minimizing power drain, an optimum-type display is provided which is neither so dim as to be not legible nor so bright as to cause fuzziness or blurring of the display.

Referring now to FIGS. 3a and 3b, there is shown a detailed schematic diagram of the circuit used in the preferred example of the invention. Oscillator 11, which is preferably a stable, crystal controlled oscillator, is connected to frequency divider 12. In the embodiment disclosed herein, frequency divider 12 produces six different output frequencies. For illustrative purposes only, the output frequencies are designated as F through F with the frequency F being the highest frequency, for example 256 Hz. The other frequencies, in descending order, are l28 Hz., 64 Hz., 8 l-Iz., 4 Hz. and 2 Hz. The frequencies F F and F are used to control the duty cycle at which pulses of energy are supplied to the display at a rate sufficiently high that the persistence of the eye does not perceive the flashes and which do not cause beats with 50 or 60 Hz. lighting. Frequency F is used as a time standard. Frequency F is used to provide a flashing display. Frequency F is used for setting the hours and minutes count.

The output signals from the divider 12 are connected to the specific inputsof the circuit portions shown in FIGS. 3a and 3b. For example, frequency F is connected to one input of NOR gate 20 which is located in operate and set controller 15.

Another input of gate 20 is supplied by NOR gate 58 which is in the duty cycle controller 13. Gate 20, and all other NOR gates in the instant circuit, is defined to produce a positive output signal only when all of the input signals are negative or binary zero signals. For purposes of definition and discussion of the operation of the gates in this network, the designations of binary zero," negative signal, and low level signal are intended to be synonymous. The definition is meant to designate the aforementioned signals as being negative relative to the opposite binary one, high level" or positive signal. The specific signal is not limited to absolute values, such as a negative voltage or positive voltage. Rather, by definition signals are intended to be considered relative one to the other.

The output of gate 20 is connected to one input of NOR gate 21. The other input of gate 21 is connected to the Q output of dual flip-flop 37. In addition, the output of gate 20 is connected to an input of NOR gate 46 in duty cycle controller 13 while the output of gate 21 is connected to another input of NOR gate 46 and to an input of AND gate 300. Frequency F is connected to the other input of AND gate 300. Frequencies F and F are connected to one input each of NAND gates 49 and 50, respectively. Gates 49 and 50 are located in duty cycle controller 13. NAND gates are defined as circuits which produce binary zero outputs only when all of the inputs are binary ones and the AND gates are defined as circuits which produce binary one outputs only when all inputs are binary ones.

Frequency F is connected to one input of each of NOR gates 38 and 40 in operate and set controller 15. Frequency F from frequency divider 12, is connected to one input of each NOR gates 27 and 28. Thus, it can be seen that the different frequency signals are supplied to different portions of the circuit to provide information thereto or control operation thereof.

During normal operation the second flip-flop of dual flip-flop Iiis in its set state and theO output is nega tive. The O output of dual flip-flop 37 is connected to the other input of NOR gate 40 as an enabling signal and through Line D to one input of each of the NOR gates 74a a nd a of counter 9a which counts seconds. When the Q output is negative, pulses of frequency F, applied to the other input of NOR gate 40 are applied through Line C to the clock input of counter 76a of counter 9a, which comprises a pair of counters 76a and 77a. The count stored in counter 760 indicates the units digit of the seconds count and the count stored in 77a indicates the tens digits of the seconds count. The frequency of pulses applied to the clock input of counter 76a is, in accordance with the preferred embodiment of the invention, 8 pulses per second rather than 1 pulse per second in order to minimize synchronization errors. Thus, it is possible to set the seconds count to one-eighth of a seconds accuracy. The counter 76a, in order to accommodate the pulse rate of 8 pulses per second while indicating the count in one pulse per second includes three additional stages which effectively divide the input signal by 8 and counts the quotient. Thus, as long as theO output is low, resulting from the second flip-flop of the dual flip-flop 37 being in a set condition, the count indicated at the outputs of the counters 76a and 77a will increase at the rate of one count per second.

Nand gate 72a is connected to certain ones of the outputs of counter 76a to detect a predetermined count. Typically, this count will be 10 counts. Gate 72a produces a negative output signal when the required count is reached. The negative signal is supplied to and inverted by inverter 73a. The positive signal from insupplied to counter 770. Thus, counter 77a (the tens counter for the seconds display) counts every eightieth pulse supplied to counter 76a. Gate 78a is connected to the outputs of counter 77a to detect a prescribed count, for example, 6. When this count is detected, NAND gate 78a supplied a negative signal to inverter 79a. In response to this signal, inverter 79a produces a positive signal and supplies same to an input of NOR gate 80a to force a negative output signal therefrom. The negative signal is supplied to one input of NOR gate 81a. The other input of gate 81a is clamped negative (i.e. to ground) so that gate 81a produces a positive signal which is supplied to the reset terminal of counter 77a whereby counter 77a is reset to zero.

It should be noted that gates 74a and 80a also receive signals from the@ terminal of flip-flop 37. An alternative reset of the seconds counter is initiated by operation of switch 8.

The output of inverter 79a is further supplied to an input of NOR gate 83. Another input of gate 83 is controlled by switch 8. Thus, in the absence of an altemative set signal, gate 83 receives a negative signal from gate 28. The output of gate 83 is connected to the input of minutes units counter 76b of counter 9b. Thus, every positive signal from inverter 79 causes gate 83 to produce a negative signal. The signals from gate 83 are counted by counter 76b. That is, every 60 seconds a minute count is produced in counter 76b. Again, the outputs of counter 76b are detected by gate 72b to provide a negative input to the inverter 73b. Counter 76b is reset on the tenth count thereof by the positive signal produced by inverter 73b in response to a negative signal from gate 72b.

In addition, the output of inverter 73b is connected to counter 77b whereby additional counts are made. A reset pulse is supplied to counter 77b via the network comprising NAND gate 78b and inverter 79b. The reset network is similar to those previously described.

In addition, the output of inverter 79b is connected to an input of NOR gate 93. The other input of gate 93 is connected to receive an alternate set signal as controlled by switch 7. Each positive signal to gate 93 causes a negative signal to be supplied to D type flipflop 97. When flipflop 97 is triggered by the signal from gate 93, an output signal is supplied to an input of one of gates 16c, the input of counter 98 and an input of NAND gate 104.

This circuit is similar to the preceding circuits in that the counter counts the input signals. However, as in usual timing devices, the hours readout will not display the character 0. Rather, after a readout of 12, there will be a readout of 1. Therefore, the output of flip-flop 97 is connected directly to the input of one of gates 160. Thus, when counter 98 is reset, an indication of l is provided and a transitional 0 is prevented. Counter 98 is reset by the network comprising NAND gate 720, inverter 73c and NOR gates 74c and 75c which detects a given condition at counter 98 and resets the counter at the appropriate time.

In addition, inverter 73c supplies a signal to flip-flop 103. The two outputs of flip-flop 103 are connected to one input of each of gates and 96, respectively of the display control 16c. Gate 95 operates to produce a l readout when enabled. Gate 96 operates to turn off the tens display on the hours readout unit when enabled.

The inputs of NAND gate 104 are connected to outputs of flip-flop 97, flip-flop 103 and counter 98 such that gate 104 is activated whenever a count of 13 is indicated. When activated, gate 104 supplies a negative signal to an input of NOR gate 105. The other input of gate 105 is already clamped at the negative level. Thus, at the count of 13, gate 105 produces a positive signal which is supplied to the base of NPN transistor T10. When transistor T10 is rendered conductive by this positive signal, a reset signal is supplied to ilip-flop 103 and to counter 98 via gates 74c and 750. Thus, only the 1 readout display from flip-flop 97 is activated. Therefore, the readout has changed from 12 to 1 as required.

The decoder and display 17 is divided into three sections 17a, 17b and each of which include a respective one of the displays 30, 3b and 3c. The decoder and display 17 incorporates conventional circuitry and is suitably similar to the solid state numeric indicator sold by Hewlett-Packard under its Part No. 5082-7000, but of reduced size. The four outputs of the counter 76a are applied to the associated portions 17a of the decoder and display through gates 200a, 202a, 204a and 206a of section 16a of the display control. The three outputs of counter 77a are connected to the decoder 17a through gates 208a, 210a and 212a. In similar fashion, the minutes counters 76b and 77b are connected through respective gates of display control 1612 to the decoder and display 17b incorporating the display 3b. The 3 outputs of counter 98 are connected through gates 200C, 202C and 2040 of display control 16c to a portion of the decoder and display 170 incorporating thedisplay 30. It will be appreciated, however, that a readout is not permitted until the source of B+ is applied to line H for the seconds readout, to Line I for the minutes readout or to line J for the hours readout and until enabling signals are provided on lines A, B andE as may be appropriate for enabling the gates of the display controls 16a, 16b and 16c. An important feature of the present invention is the use of NOR gates in the display control to prevent circulating currents between the counters and associated decoders and displays.

It is important to note that although signals have been supplied to inputs of several groups of gates, a readout display has not been permitted as these gates have not been enabled. The only power drain is that to the oscillator Ill, frequency divider 12, dual flip-flop 37 and the counter 9 and can be measured in micro-amperes.

The operate switch 4, as mentioned previously, controls operation of the watch. Momentary operation of switch 4 causes the hours and seconds display to be energized for a short time interval with the duty cycle controller 13 and switch circuit 18 controlling the intensity of the display in accordance with the ambient light levels sensed by light sensors 5 which respond to three different light levels L L and L If switch 4 is maintained depressed, the seconds display only will be energized under duty cycle control after the time interval until the switch 4 is opened. The duty cycle controller 13, as previously noted, receives input signals from frequency divider 12, and operates in set circuit 15 and light sensor 5.

The philosophy of duty cycle controller 13 is to control the length of time the display elements receive power from the power source. The duty cycle controller has the function of reducing the power supply drain to a minimum. This reduction can be effected in many ways as will be seen hereafter. The light sensors shown in FIG. 1 are, in the preferred example of the invention, light sensitive transistors T7, T8 and T9. Three sensors are used to cover the range of incident light without saturation or insufficient sensitivity. Such transistors are known in the art and effectively produce current flow therethrough as a function of the light incident thereupon. The collector electrode of transistors T8 and T9 are connected together and to one terminal of isolating resistor 57. The collector of transistor T7 is connected to the opposite terminal of resistor 57 and to one input of NOR gate 58. The other input of gate 58 is connected to ground. Resistor 57 is of sufficient resistance that the output of gate 58 is high when transistor T7 conducts. The emitter electrode of transistor T8 is connected to one input of NOR gate 59 across voltage dropping resistor 15] which is returned to ground. The other input of gate 59 is also connected to ground. The emitter electrode of transistor T9 is connected to one input of NOR gate 60 across voltage dropping resistor 150 which is returned to ground. The other input of gate 60 is also connected to ground. The emitter of transistor T7 is connected to ggundgates 58, 59 and 60 produce output signals L L and L respectively. These output signals represent conduction conditions of transistors T7, T8 and T9, respectively, with the presence of a signal indication that the threshold of the transistor has been attained. The conduction conditions are thereby indicative of the amount of light which is incident upon the face of the watch. This information is, of course, significant inasmuch as the readout display need not be illuminatedas brightly nor as long in a dimly lit environmental situation as is required in a bright environment.

The control of duty cycle can be explained most simply with reference to the curves of FIG. 4 wherein curves A, B and C show the output frequencies F F and F It will be noted that the phase relationship between the output signals of frequencies F F and F and F is such that the trailing edge of each lower frequency signal occurs at the time a trailing edge of each higher frequency signal occurs.

At light levels below L (dimmest light condition) power is supplied to the hours display each time all three signals are positive, as shown in Curve D, resulting in a 12.5 percent duty cycle. To decrease the maximum current drain, power is supplied to the minutes display when signals'of frequencies F and F are positive and F is low, as shown in Curve E. When light level L, is attained, a duty cycle of 25 percent is provided as shown in Curves F and G. When light level L is attained, a 50 percent duty cycle as shown in curves H and I is provided. At light level L both arrays receive power continuously, resulting in maximum intensity. However, further power savings can be achieved by causing the display to flash at frequency F reducing the duty cycle then prevailing by 50 percent. It is important to note that the pulse repetition rate is the same in each of the curves C I and is that of frequency F which is sufficiently high that due to normal persistence of the eye, pulsing of the diodes will not be detected.

Turning again to FIGS. 3a and 3b of the drawings, it can be seen that when switch 4 is opened, B+ (battery voltage) is disconnected from the line 44. Thus, a relatively negative signal is supplied to the C output of dual flip-flop 37 and to the input of inverter 45. This negative signal, which is produced by connecting resistor 301 to ground, is also supplied to one input of NOR gate 55. The other input of gate is connected to the output of inverter 47. Inverter 47 has the input thereof connected to the output of NOR gate 48. One input of gate 48 is connected to the output of gate 26. Another input of gate 48 is connected to the output of gate 22. Still another input of gate 48 is connected to the output of AND gate 300. Gate 300 has one input connected to receive frequency signal F from frequency divider network 12. The output of gate 21 (hereinafter referred to as LED CONTROL) is connected as another input of gate 300.

So long as switches 7 and 8 remain open (unoperated), gates 22 and 26, respectively, produce negative output signals which are supplied to gate 48. The LED CONTROL signal from gate 21 will be a low level nal, as well, inasmuch as gate 21 receives a positive Q signal from flip-flop 37. The output of gate 300 is low and gate 48 receives all negative input signals and produces a positive output signal. This signal is inverted by inverter 47 so that a negative signal is supplied to a second input of gate'55 and to one input of each of gates 52 and 53.

Since gate 55 receives negative signals at each input thereof, a positive signal is produced at its output. This signal is inverted by inverter 56 and supplied to the collector electrodes of transistors T8 and T9 directly and to the collector of transistor T7 via resistor 57. Thus, each of the light sensitive transistors is rendered nonconductive. Inasmuch as light sensitive transistors T8 and T9 are non-conductive, NOR gates 59 and 60 receive all negative inputs. Thus, gatesi9 and 60 produce positive output signals T5; and L respectively. These signals represent or are indicative of the fact that the ambient light sensed by the transistors has not reached a prescribed level. In this condition, the representation is merely indicative of the fact that switch 4 has not been closed.

In addition, gate 58 receives only negative signals at the inputs thereof. Consequently, gate 58 also produces a positive output signal. This signal is supplied to an input of NOR gate 20. A negative L signal (from gate 58) is required as an enable signal to permit the frequency signal F (ignoring phase reversal) to be passed therethrough. The negative signal is applied directly to one input of NOR gate 46 and to one input of NOR gate 21. Gate 21 is clamped by the aforementioned positive Q signal from flip-flop 37 and produces a negative output signal.

Gate 46 receives the negative output signal from NOR gate 21, the negative signal from gate 20 and a signal from inverter 45. Since switch 4 is defined as being open, inverter 45 inverts the negative signal supplied thereto and produces a positive signal which is applied to an input of gate 46. Consequently, gate 46 always produces a negative output signal until switch 4 is closed to supply a positive signal to inverter 45.

The negative signal produced by gate 46 is supplied as input of NAND gate 54. Gate 54 will produce a positive output signal in response to the negative input signals. This signal is supplied to the base of emitter follower transistor T6. Since transistor T6 is a PNP type, the positive input signal causes non-conduction in this transistor. When transistor T6 is non-conductive, transistor T3 is also non-conductive. Supply voltage B+ is, accordingly, not provided on line H for the seconds display and an enabling voltage forthe gate of the display control is not provided on line A. Thus, no drain has been placed upon the source.

Inverter 47 also supplies a negative signal to one input of each of gates 52 and 53. Thus, regardless of the condition of the other input signals, gates 52 and 53 must produce positive output signals. These signals are supplied to the bases of PNP transistors T and T4, respectively. With positive signals at the bases thereof, transistors T5 and T4 remain non-conductive. Consequently, transistor T2 and T1 are also non-conductive. Supply voltage 3+ is not provided on lines I and J nor is an enabling voltage provided on lines B or E.

If switch 4 is closed, a positive voltage from B+ is connected to the input of gate 46 via inverter 45. Consequently, a negative signal is supplied to gate 46. Simultaneously, a positive signal is supplied to the C input of flip-flop 37 and one input of NOR gate 34. The positive signal at D causes Q to become a negative signal which effectively enables NOR gate 40. Also, application of a positive signal to gate 34 causes a negative signal to be produced thereby. This negative signal is applied to NOR gate 35. The other input of gate 35 is already a negative signal (i.e. connected to ground). Thus, gate 35 produces a positive signal which is supplied to the C input of flip-flop 37. Application of the C signal causes output (T of flip-flop 37 to become a negative signal. This negative signal is supplied to gate 21 to enable,sam e as described hereinafter.

The negative Q signal is also connected to an input of NOR gate 38. The other input of gate 38 is connected to frequency signal P, (eg 8 Hz). Thus, when P, is at the negative level, gate 38 produces a positive pulse. Clearly, the pulses produced by gate 38 are identical, in frequency,to frequency signal F The signals from gate 38 are supplied to counter 41. Counter 41 is a conventional counter, many of which are known in the art. Gate 42 is connected to counter 41 in such a manner as to be responsive to a predetermined count. In the instant configuration, a count of pulses is detected. When the prescribed count is detected, gate 42 produces a negative signal which is supplied to and inverted by inverter 43. The positive signal from inverter 43 is supplied to the R terminal of flipflop 37 whereby 6 1s reset to the positive level and the output of gate 21 is effectively clamped to the negative level. In addition, the output of gate 38 is effectively clamped to the negative level. Thus, it is seen thatfor a prescribed period (e.g. 10 counts or 1.25 seconds) gate 21 i nabled.

When 0 is switched negative by the application of the C signal and gate 40 is enabled, the F signal (e.g. 8 Hz.) is supplied to the input of counter 76 associated with the seconds display. The F. signal is, thus, continuously applied to counter 76 until flip-flop 37 is reset by the R signal from gate 33. Consequently, the logic circuitry associated with the display units is continuously functioning to count pulses, until the R input of flipflop 37 receives a signal to reset the Q output signal to the positive level.

Moreover, when switch 4 is closed, a positive signal is supplied to one input of gate 55. In response to the positive input signal, gate 55 produces a negative signal which is inverted by inverter 56. Thus, a positive signal is supplied to the collectors of the light sensitive transistors whereby these transistors are now enabled. Depending upon the light incident thereupon, different combinations of transistors T7, T8 and T9 will conduct (unless no transistors conduct). Conduction by transistors T8 or T9 will apply a positive signal to an input of the associated NOR gates 59 and 60, respectively. A positive input signal will cause either of gates 59 60 to produce negative output signals. Conversely, nonconduction by transistors T8 or T9 will cause the associated gate 59 or 60 to produce a positive output signal. Thus, in this circuit configuration a positive signal at L or L represents a light level below a presented threshold. Obviously, a negative signal at Eor L represents a light level above a defined threshold. Similarly, conduction by transistor T7 supplies a negative signal to an input of gate 58 whereby gate 58 produces a positive output signal. This signal represents the attainment of a prescribed light level. If gate 58 produces a negative signal, the appropriate light level has not been reached and transistor T7 is non-conductive. Typically, L represents the highest light level, e.g. bright sunlight, and the other signals represent lower light levels.

Signal L is supplied as one input to gate 20. If L is a negative signal, representative of very dim environment, gate 20 is enabled and frequency F is transmitted therethrough. Signal F is supplied to one input of gate 2ll and to one input of gate 46. Since switch 4 is closed, gate 21 is enabled by a negative 6, signal. Thus, a LED (Light Emitting Diode) CONTROL signal is supplied to another input of gate 46 and to the input of AND gate 300. It will be seen that the LED CONTROL signal from gate 21 is out of phase with the signal from gate 20. Consequently, it is impossible to obtain a condition of all negative inputs at gate 46 whileO is negative. Therefore, gate 46 will generate a negative output signal. This signal is supplied to NAND gate 54 and forces a positive signal at the output thereof. This positive signal prevents transistor T6 from conducting. Thus, transistor T3 does not conduct and seconds display 3a is not energized.

In addition, the frequency signals F (e.g. 4 Hz.) is supplied as another input to gate 300. Gate 300 produces a positive signal only when all inputs thereto are positive. Clearly, frequency signal F5 is positive only for a portion of the time and negative for the rest of the time. Therefore, gate 300 produces a pulsed output of frequency F modulated at frequency F This signal has the effect of producing a pulsating signal such that display control gates are intermittently enabled by lines B and E and power is intermittently supplied on lines I and J. Thus, a further conservation of energy is effected since the display unit is illuminated only for the time permitted by signal F The output of AND gate 300 is applied as one input of NOR gate 48 whose other inputs are the outputs of NOR gates 22 and 26. As switches 7 and 8 are open, the outputs of gates 22 and 26 are low and each time the output of gate 300 is low a positive pulse (frequency F modulated at frequency F is provided at the output of gate 48. This signal is inverted by inverter 47 and applied to one input of each of NOR gate 55 and NAND gates 52 and 53. NAND gate 53 also receives inputs from NAND gates 49 and 51. The inputs to NAND gate 49 is frequency F and the signal L The inputs to gate 51 are the output of NAND gate 50 and the signal i The inputs togate 50 are the t signal and frequency F At the dimmest light levelT and will be positive and toward the end of each pulse of frequency F transistors T and T conduct if a pulse of frequency F is supplied to gate 52, energizing the hours display 30 as shown in curve D. Immediately prior to the beginning of each pulse frequency F;, the output of gate 53 will go low if a pulse of frequency F 1 is provided at its input, rendering transistors T and T conductive to energize the minutes display 3b as shown in curve E. When the light level L is reached, transistor T7 will conduct. The voltage drop across resistor 57 is sufficient to cause the input to gate 58 to be low, resulting in a high output.

The high output of gate 58 is applied to an input of gate to cause its output to go low, and causing the output of gate 21 to be high. The output of gate 46 will remain low and the output of gate 300 will be positive pulses of frequency F producing positive pulses of frequency F at the output of inverter 47. These positive pulses are supplied to gate 55 for causing the transistors T7, T8 and T9 to be enabled.

When the output of inverter 47 is positive, pulses of frequency F the output signals 1 3 and i will be positive and positive pulses of frequencies F and F will cause the outputs of gates 49 and 50 to be low since the t and I signals are positive. The output of gate 51 will be high when the signal of frequency F is positive and low when the signal of frequency F is negative. Accordingly, when the signal of frequency F is positive, the output of gate 52 will be low, causing transistors T and T to conduct and supply B+ power to the hours decoder and display 170 on line I as shown in curve F. The positive pulses of curve F are inverted by inverter 310 and applied on line E to enable the gates of display control 160, causing the hour display to be energized in accordance with the count stored in counts 98 and the state of flip-flops 97 and 103. When the signal of frequency F is negative, the output of gate 52 will be high and the output of gate 53 will be low causing line I to receive B+ as shown in curve G and an enabling signal to be supplied from inverter 312 on line B. Minutes display 3b will accordingly be energized.

In similar fashion, when light level L is reached, transistor T8 will conduct and the output of signal E of gate 59 will be low, causing the output of gate 49 to be high. When the signal of frequency F is high, the hours display will be energized as shown in curve II; when it is low the minutes display will be energized as shown in curve I.

Transistor T9 will conduct when light level L is present, causing the output of gate 60, t to be low, and the outputs of gates 50 and 51 will be high. The only pulsating signal is of frequency F supplied by gate 48. The output of gates 52 and 53 will be low at all times the signal of frequency F is high, causing the displays 3b and 3c to flash at maximum intensity of frequency F Thus, it can be seen that the duty cycle is a direct function of incident light. The greater the intensity of ambient light, the greater the duty cycle.

It can be seen that it would be practical to connect the output of gate 21 directly to gate 48 in which event the flashing effect would not be provided and the power consumption would almost double.

In order to illuminate the seconds display 3a, operate switch 4 must be maintained in the closed position for a time period greater than the time-out period or counting period for counter 41. That is, switch 4 must remain closed to supply a negative signal to gate 46 until flip-flop 37 has been reset by counter 41 and output signal 6 is returned to the positive level. This positive signal is supplied to gate 21 and forces a negative output signal therefrom. The negative LED CON- TROL signal is supplied to inputs of gates 300 and 46. The negative input to gate 300 has the effect of blocking the gate. However, the negative signal supplied to gate 46 results in a positive output signal of frequency F therefrom since all of the other input signals supplied to gate 46 are negative, at least periodically. Moreover, the signals supplied to gate 54 are all positive for at least a portion of the time as controlled by the light threshold achieved. When all of the input signals to gate 54 are positive, a negative signal is produced at its output, biasing transistors T and T on and 8+ is connected through line H to supply power to display 3a. The duty cycle at which power is supplied will vary in accordance with the light level present, as described above, but without flashing, and inverter 314 will apply 8+ on line H and enabling signal on line A.

An alternative form of control for the diode displays in order that the intensity of the light produced by the diode arrays will be related to the ambient light as shown in FIG. 5 of the drawings. In accordance with the embodiment of the invention shown in FIG. 5 of the drawings, ambient light 400 passes through the filter 2 and impinges upon a transistor 402. The collector of the transistor 402 is connected through switch 404 to 8+ with its emitter being connected through 406 to ground. The emitter of transistor 402 is also connected through resistor 408 to one input of the differential amplifier 410 and through capacitor 412 to ground. The second photosensitive transistor 420 is similarly connected with its collector being connected to 8+, its emitter being connected through resistor 422 to ground, its emitter being connected through resistor 424 to the other input of differential amplifier 410 and its emitter being connected through capacitor 426 to ground. The output of the differential amplifier 410 is connected through diode 430 to the base of transistor 432 whose emitter-collector circuit is connected between the source of power 8+ to the decoder and display 17 through display control 16 and through resistor 434 and light emitting diode 436 to ground. The light emitting diode 436 and the phototransistor 420 are positioned within the case 1 such to be shielded from ambient light with the radiation emitted by the diode 436 impinging upon the photosensitive 42 It will be noted that the diode 436 and the diodes of display 17 each receive power in accordance with the output of the differential amplifier 410. Further, the conductivity state of the transistor 420 is a function of the emission from the diode 436 and the conductivity state of transistor 402 is a function of the intensity of the ambient light. Accordingly, the output of th amplifier 410 and the amount of voltage supplied to the diode displays is a function of the intensity of the ambient light.

The circuit shown in FIG. 5 has the advantage of greater simplicity and also permits the diode displays to be energized to a desired extent even through the battery may be discharged to a substantial level. The principal disadvantage of the circuits of FIG. is that it does not provide for alternative energization of the hours and minutes displays or for a flashing display. However, these features could be embodied into the circuit of FIG. 5 as desired. For example, as shown in FIG. 5a, the output of the amplifier 410 can be supplied to a level detector having a plurality of outputs connected to the duty cycle controller 13. It would, of course, be feasible for the outputs to control transistors corresponding to transistors T7, T8 and T9.

Thus, there has been described the operation of the duty cycle control circuit and part of the operate circuit for standard operation as initiated by operate switch 4. However, it will normally be required to set the watch to the correct time, at least initially. Setting of the watch is performed by actuation of switches 7 and 8 which control the setting of the hours and minutes, respectively.

In setting the watch, switch 4 will be open. However, switch 7 will be closed by the operator to set the hours display. When switch 7 is closed, both inputs of NOR gate 22 are clamped negative whereby gate 22 produces a positive signal which is supplied to gate 48. Gate 48 produces a negative signal which is supplied to and inverted by inverter 47. Thus, a continuous positive signal is supplied to an input of each of gates 52 and 53. The ohter signals supplied to gates 52 and 53 are positive, at least peridically, as'described above. Consequently, the hours and minutes display is illuminated for reference by the operator.

When switch 7'is closed, a negative signal is also supplied to an input of NOR gate 27. The other input of gate 27 is connected to receive frequency F from frequency divider 12. When signal F (suitable 2 Hz.) is at the low level, gate 27 produces a high level output signal which is supplied to NOR gate 93 on line G. This positive signal causes gate 93 to produce a negative signal which triggers flip-flop 97 and causes operationof counter 98. When counter 98 produces the proper output signal combination as indicated at the display, switch 7 is released. The input to gate 27 returns to the positive level thereby producing a negative output signal which is supplied to gate 93 whereby gate 93 is enabled and can transfer signals from the minutes counter to the hours counter when appropriate.

Similarly, when switch 8 is closed, a negative signal is supplied to an input of each of NOR gates 26 and 28. The other input of gate 28 is connected to receive frequency signal F so that a pulsating signal is supplied at the output of gate 28. The pulsating output of gate 28 is supplied on line F to an input of'NOR gate 83 and produces a pulsating'output of gate 83. The pulsating output of gate 83 is supplied to counter 912. When the appropriate minutes readout is provided, switch 8 is released. A positive signal is then applied to an input of gate 28, thereby effectively blocking this gate and preventing additional pulses of frequency F from being transmitted to counter 9!). However, gate 28 now provides a negative signal to gate 83 whereby signals can be transferred from the seconds counter to the minutes counter when appropriate. In addition, while switch 8 is closed, the pulsating signal from gate 28 is supplied to an input of NOR gate 32 and produces a pulsating signal at the output thereof. This signal is, in turn, supplied to an input of NOR gate 33 which also produces a pulsating output signal of about 2 Hz. The output of gate 33 is supplied to the reset 2 input of flip-flop 37 to switch output signal 6 to the positive condition. Thus, NOR gate 40 is effectively blocked and produces a continuous negative output signal. In addition, the application of a positive 6 signal on line D to NOR gates 74 and 80a forces a negative output signal therefrom. This latter low level signal is supplied to NOR gates 75a and 81a along with another low level input. Thus, gates 75a and 81a produce high output signals which resets counters 76a and 77a to the zero condition until a subsequent operate signal is supplied.

The output of gate 33 is also supplied to one input of NOR gate 34. Thus, gate 34 supplies a pulsating signal to one input of NOR gate 34 as a function of the pulsating signal supplied by gate 32. Gate 35 provides a pulsating input to the C input of flip-flop 37. A positive input signal at C, input causes O to be positive and, therefore, 6, is negative. A negative O signal enables gate 21 as described above to ensure that the LED CONTROL signal is supplied. Thus, the display is illuminated and the operator can observe the minutes setting.

In addition, the negative O, signal initiates operation of the reset network which includes counter 41. Thus, flip-flop 37 will be reset and 6 will become positive in normal operation. However, if the minutes setting operation takes a longer time than the timeout period, switch 8 will be held closed by the operator and the C signals from gate 35 will override the RESET 1 signal and maintain O, at the negative level until the proper minutes setting is displayed.

The watch is now assumed to be set to the proper time. The minutes and hours are appropriately registered and the seconds display is set at 00. For precise time, the operator can detect the time tone supplied by many official agencies. At the tone, switch 4 is closed. A high level signal is supplied to the C input of flip-flop 37 and pulses are supplied to the counters to increase the count from that set.

Although the invention has been described with reference to particular preferred embodiments thereof, many changes and modifications will become apparent to those skilled in the art in view of the foregoing description which is intended to be illustrative and not limiting of the invention defined in the appended claims.

We claim:

1. An electronic timepiece comprising:

a. a self-contained power source;

b. visual display means for providing a visual output representative of time;

c. signal generating means for supplying stable frequency signals;

d. means responsive to said signals for providing a plurality of binary outputs representative of time;

c. a manually operable switch; and,

f. display control means effective only upon opera- 7 tion of said manually operable switch for energizing said visual display means in accordance with said plurality of binary outputs, said visual display means being controlled by said display control means to provide an indication of minutes and hours responsive to operation of said manually operable switch, said display control means controlling the power supplied to the visual display means in accordance with ambient light conditions.

2. An electronic timepiece comprising:

a. a self-contained power source;

b. visual display means for providing a visual output representative of time;

0. signal generating means for supplying stable frequency signals;

means responsive to said signals for providing a plurality of binary outputs representative of time;

e. a manually operable switch; and,

f. display control means effective only upon operation of said manually operable switch for energizing said visual display means in accordance with said plurality of binary outputs, said visual display means being controlled by said display control means to provide an indication of minutes and hours responsive to operation of said manually operable switch, said display control means controlling the power supplied to the visual display means in accordance with ambient light conditions, the duty cycle at which power is supplied being varied to control the power supplied to the visual display means.

3. An electronic timepiece comprising:

a. a self-contained power source;

b. visual display means for providing a visual output representative of time;

c. signal generating means for supplying stable frequency signals;

d. means responsive to said signals for providing a plurality of binary outputs representative of time;

e. a manually operable switch; and,

f. display control means effective only upon operation of said manually operable switch for energizing said visual display means in accordance with said plurality of binary outputs, said visual display means being controlled by said display control means to provide an indication of minutes and hours responsive to operation of said manually operable switch, said display control means controlling the power supplied to the visual display means in accordance with ambient light conditions, said display control means including a plurality of light sensitive devices each responsive to different levels of ambient'light.

4. An electronic timepiece comprising:

a. a self-contained power source;

b. visual display means for providing a visual output representative of time;

0. signal generating means for supplying stable frequency signals;

d. means responsive to said signals for providing a plurality of binary outputs representative of time;

e. a manually operable switch; and,

f. display control means effective only upon operation of said manually operable switch for energizing said visual display means in accordance with said plurality of binary outputs, said visual display means being controlled by said display control means to provide an indication of minutes and hours responsive to operation of said manually operable switch, said display control means controlling the power supplied to the visual display means in accordance with ambient light conditions, said display control means including a first light sensitive means responsive to the level of ambient light, detector means responsive to the power level supplied to the display means, and means responsive to signals produced by said light sensitive means and said detector means for varying the power supplied to the display means.

5. A timepiece as defined in claim 2 wherein the pulse repetition rate at which power is supplied is sufficiently high that it is not detectable by the human eye and of a frequency which does not beat with 50 or 60 Hz. light.

6. A timepiece as defined in claim 2 wherein said display control means includes means responsive to ambient light levels being below a level at which the duty cycle is percent for causing alternate indications of minutes and hours at a frequency rate sufficiently high as to be not detectable by the human eye.

7. A timepiece as defined in claim 2 wherein said display control means includes means for modulating power supplied to said visual display means to produce a flashing indication of minutes and hours discernable by the human eye.

8. A timepiece as defined in claim 5 wherein said visual display means comprises light emitting diodes.

9. A timepiece as defined in claim 8 including a cover over said light emitting diodes substantially transparent to light of the frequency emitted but not to light of higher frequency.

10. A timepiece as defined in claim 4 wherein said display means is a plurality of light emitting diodes and wherein detector means includes a second light sensitive means and a light emitting diode energized at the same level as said plurality of light emitting diodes.

11. A timepiece as defined in claim 10 wherein said first and second light sensitive means are photo transistors.

12. An electronic wrist watch comprising an integral power source means, display means for producing a visual output representation of time, first switch means connected between said source means and said display means whereby said source means is selectively connected to said display means, logic control means connected to said display means to supply logic signals thereto to produce selective operation of said display means when said display means is connected to said source means, signal generating means for supplying alternating signals, duty cycle controller means for selectively connecting said signal generating means to said logic control means to control the number of said alternating signals which are selectively supplied to said logic control means, sensor means for sensing the environmental light condition, said sensor means connected to said duty cycle controller and to said logic control means to affect the operation thereof as a function of the environmental light condition and further switch means for selectively connecting said source means to said logic control means.

13. The electronic wrist watch recited in claim 12 wherein said first switch means includes a plurality of semiconductor devices connected between said source means and said display means, said plurality of semiconductors selectively controlled by said duty cycle controller means whereby said source means supplies energy to said display means only when said semiconductor means is conductive.

14. The electronic wristwatch recited in claim 12 wherein said further switch means comprises a plurality of pushbutton switches, each of said pushbutton switches controlling an operation of said wrist watch, at least one of said pushbutton switches controlling the setting of said wrist watch.

15. The electronic wrist watch recited in claim 13 wherein said signal generating means includes oscillator means and frequency divider means, said logic control means includes a plurality of counters connected to gating networks, said gating networks connected to said display means and operative to supply signals to said display means as a function of the status of said counters when said semiconductor means is conductive.

16. The electronic wrist watch recited in claim 12 wherein said display means includes illuminable elements, said elements being illuminated upon the application of electrical energy thereto, said logic control means including first gate means for supplying electrical energy to said elements upon receipt of appropriate signals thereto, said first gate means adapted to receive energy from said source means via said first switch means where said'switch means is rendered conductive in response to signals from said duty cycle controller counter means connected to said signal generating means to count signals supplied thereto and produce l output signals representative of the signal count and supply the output signals to said first gate means to enable same to transmit electrical energy therethrough to said elements, reset network means associated with each counter means whereby the counter means can be reset to a preselected count.

17. The electronic wrist watch recited in claim 12 wherein said sensor means comprise at least one light sensitive transistor in which the conduction thereby is a function of the light incident thereupon, each of said light sensitive transistors connected to the input of a separate gate unit to produce a control signal therefrom representative of the light incident upon said wrist watch, said duty cycle controller means including a plurality of gate means connected to receive and operate upon signals from said signal generating means and from said gate units to produce signals which selectively activate said switch means to supply electrical energy from said source to said display means.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
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Non-Patent Citations
Reference
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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3962858 *Aug 29, 1973Jun 15, 1976Uranus Electronics Inc.Electronic watch
US4008429 *Mar 31, 1975Feb 15, 1977Intel CorporationVoltage translator for solid state watch
US4011557 *May 13, 1975Mar 8, 1977Ebauches S.A.Device in a time piece for feeding an electro-luminescent display
US4026101 *May 27, 1975May 31, 1977Hughes Aircraft CompanyPush button response of combination LCD/LED wristwatch
US4036008 *Jul 6, 1976Jul 19, 1977Tokyo Shibaura Electric Co., Ltd.Electronic timepiece
US4090350 *May 3, 1976May 23, 1978Citizen Watch Co., LimitedElectronic timepiece
US4092822 *Nov 25, 1975Jun 6, 1978Ebauches SaControl device for an electronic wrist-watch
US4153358 *Jul 26, 1977May 8, 1979Minolta Camera Kabushiki KaishaInformation setting apparatus for cameras
US4184318 *Nov 16, 1978Jan 22, 1980Copal Company LimitedTime indicating device for electronic digital type car clocks
US4264966 *Jun 29, 1979Apr 28, 1981Terzian Berj ABalanced digital time displays
US4270196 *Mar 6, 1979May 26, 1981Terzian Berj ABalanced complementary digital time displays
US4271497 *Mar 13, 1978Jun 2, 1981Terzian Berj AQuadri-balanced digital time displays
US4483628 *Mar 17, 1981Nov 20, 1984Terzian Beri ABalanced chronograph digital time display
US8934320 *Feb 7, 2012Jan 13, 2015Casio Computer Co., Ltd.Electronic timepiece
US20120213040 *Feb 7, 2012Aug 23, 2012Casio Computer Co., Ltd.Electronic timepiece
Classifications
U.S. Classification368/239, 968/914, 968/928
International ClassificationG04G5/00, G04G9/00, G04G5/04
Cooperative ClassificationG04G9/0017, G04G5/04
European ClassificationG04G5/04, G04G9/00C