|Publication number||US3771152 A|
|Publication date||Nov 6, 1973|
|Filing date||May 25, 1972|
|Priority date||May 25, 1972|
|Publication number||US 3771152 A, US 3771152A, US-A-3771152, US3771152 A, US3771152A|
|Inventors||Dettling J, Farnham J, Gaines S|
|Original Assignee||Mb Ass|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Referenced by (22), Classifications (5), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
ilte States atent [1 1 Dettling et al.
[ Nov. 6, 1973 INTRUSION DETECTOR  Assignee: MB Associates, San Ramon, Calif.
 Filed: May 25, 1972 21 Appl. No.: 256,760
Primary Examiner-David L. Trafton Attorney-4. King Harness et al.
v 57 ABSTRACT An intrusion detector of the electrostatic field responsive type wherein changes in the surrounding electrostatic field generate signals in an antenna which is electrically coupled to a detection circuit. The detection circuit generates a detection signal in response to a preselected change in the surrounding electrostatic field indicative of an intruders movement. Upon the genera- I tion of a detection signal, a lock-in circuit which is operatively associated with the detection circuit locks the detection circuit so that the detection signal continues to be generated irrespective to whether the intruder continues his movement. The lock-in circuit also initiates a first timing cycle, upon the completion of which the detection signal is terminated and the lock-in circuit unlocks. Upon termination of the detection signal, a second timing cycle immediately commences to begin arming the detection circuit. Upon completion of the second timing cycle, the detection circuit is again armed, or reset, so that movement of the same intruder or of a subsequent intruder can be detected. The second timing cycle is also initiated when the detector is initially switched on and affords the authorized person who has turned on the detector ample time to leave the surrounding area without generating a detection signal.
30 Claims, 1 Drawing Figure INTRUSION DETECTOR The present invention pretains to an intrusion detector and in particular to an intrusion detector of the electrostatic field responsive type.
Among the objects of the present invention are to provide an improved intrusion detector: which can be armed by an authorized individual without generating a spurious detection signal; which upon being tripped by an intruder will thereafter automatically reset itself so that subsequent intruders can be detected; which has an onmi-directional detection capability; which is not limited to line-of-sight operation; which can detect intruders around and/or through walls, barriers, objects, etc. so long as these do not electrically shield the detector; which can be packaged as a compact, protable unit and used wherever desired; which requires no complex adjustments preparatory to arming the detector; which can be readily manufactured from commercially available electrical components; and which in spite of its numerous advantages can be manufactured relatively simply and at a relatively low cost.
Additional objects and advantages of the. invention will become apparent upon reading the ensuing description which is to be taken in conjunction with the accompanying drawing.
The drawing discloses a preferred embodiment of the invention in accordance with the best mode presently contemplated for carrying out the invention. In particu-. lar, the drawing illustrates an electrical schematic diagram of the intrusion detector of the invention.
Turning now to the drawing, an electrostatic field responsive antenna is connected to the input stage 12 of the intrusion detector. Antenna 10 may be of any suitable type, but for the purpose of rendering the intrusion detector a compact, portable unit is preferably a telescopic antenna which may be extendable, for example, from a minimum length of 4 /& inches to a maximum length of 18 inches. Stage 12 comprises a field effect transistor (FET) 14, an NPN transistor 16, a resistor l8 and a capacitor 20. The power supply for the detector comprises a pair of 9-volt DC batteries 22 and 24 which supply the requisite voltage levels for the specific circuit components utilized in the preferred embodiment. The negative terminal 22b of battery 22 is connected to the positive terminal 24a of battery 24. An on-off control switch 26 couples batteries 22, 24 to a positive bus 28 and a negative bus 30 for the detector circuitry with the positive terminal 22a of battery 22 connected through contacts 264: of switch 26 to bus 28 and the negative terminal 24b of battery 24 connected through contacts 26b of switch 26 to bus 30. The junction of terminals 22b and 24a is connected directly to a common bus 32 for the detector circuitry.
FET 14 comprises a drain terminal 14d which is connected to bus 28 and a source terminal 14s which is connected through the parallel combination of resistor 18 and capacitor 20 to common 32. The antenna lead wire 17 is connected to the gate terminal 14g of FET l4. Transistor 16 comprises a base terminal 16b which is connected to gate terminal 14g and a collector terminal 160 which is connected to common-32. The emitter terminal 162 of transistor l6,is not connected in circuit, I
biased to a quiescent condition of relatively low con duction between terminals 14d, 14s. In this quiescent condition, the voltage at source terminal 14s is approximately 4 volts. This PN junction of transistor 16 also serves to clip the positive portions of signals received by antenna 10 so that only negative signal components are supplied to gate terminal 14g. The very high input impedance of PET l4 enables stage 12 to operate as a current amplifier without swamping out the signal from antenna 10 by excessive antenna loading. Thus, the amplified negative current signals are reflected as changes in the output voltage of stage 12 from its quiescent value, as measured at terminal 14s. These voltage changes represent amplified versionsof the negative portions of the signals received by antenna 10, at least at relatively low signal frequencies, which are the frequencies of interest insofar as the detection of intruders is concerned.
The output of stage 12 is coupled to the input of an amplifier stage 38. Amplifier stage 38 comprises a resistor 34, a capacitor 36, an operational amplifier 40, a resistor 42 and a capacitor 44. Operational amplifier 40 is a commercially available unit identified in the parts list at the conclusion of the specification. Amplifier 40 comprises five terminals 40a, 40b, 40c, 40d and 40e which are connected with the intrusion detector circuit. These terminals correspond to terminals 2, 3, 6, 4 and 7 respectively of the operational amplifier 40 identified in the parts list, and accordingly, it will be appreciated that the proper connection of amplifier 40 in the detector circuit will be readily apparent. For the sake of clarity, the details of amplifier 40 are not shown in the drawing and the amplifier is described in terms of its characteristics and the function it performs. One terminal of resistor 34 is connected to terminal 14s and its other terminal to plate 36a of capacitor 36. The
other plate 36b of capacitor 36 is connected to terminal 40a. Resistor42 and capacitor 44 are connected in parallel between terminal 400 and terminal 40a. Terminal 40d is connected to bus 30, terminal 40e to bus 28, and terminal 40b to bus 32. Operational amplifier 40 is a high input impedance, low output impedance amplifier with a relatively high gain. The illustratedconnection of amplifier 40 causes the amplifier to operate as an inverting amplifier which develops zero volt output at terminal 400 for zero current input to terminal 40a. In response to an increasingly positive input current into terminal 40a, the output voltage becomes increasingly negative unitl reaching negative saturation; correspondingly, in response to an increasingly negative input current, the output voltage becomes increasingly positive until reaching positive saturation. For the normal range of input current, the voltageat terminal 40a is always approximately at zero volts (i.e. the voltage of common bus 32). .Due to the very high input impedance of amplifier 40, the current flow into terminal 400 is always very small. Accordingly, essentially all the current flow through resistor 34 and capacitor. 36 passes through resistor .42 and capacitor 44. Stage 38 operates so that the voltage at terminal 400 varies in accordance with the current flow through resistor 42. More specifically the voltage at terminal 400 is equal to the current flow through resistor 42 multiplied by the value of resistor 42. Stage 38 in part determines the frequency response of the detector with resistor 34 and capacitor 36 primarily determining the lower halfl power frequency and resistor 42 and capacitor 44 cooperating with resistor 18 and capacitor 20 in determining the upper half-power frequency. Thus, if the frequencies of the signals developed in antenna by changes in the surrounding elastrostatic field are either above or below the pass band of the detector, these signals are prevented from influencing the output of amplifier 40. In order to detect the unauthorized entry of an intruder, the bandwith of the detector is selected to pass signal frequencies within a band extending from a frequency at a few tenths of a cycle per second to a frequency at substantially less than 60 cycles per second. By making the lower limit of the band on the order of a few tenths of a cycle per second, the detector is not responsive to drift in stage 12 or ambient changes in the electrostatic field which are due to changing atmospheric conditions and the like; and by making he upper limit substantially less than 60 cycles per second, 60 cycle noise problems are avoided. With input stage 12 in its quiescent condition, (i.e. terminal 14s at approximately 4 volts) amplifier stage 38 also assumes a quiescent condition wherein the output voltage of amplifier 40 at terminal 40c is at zero volts. At quiescence, capacitor 36 is charged such that plate 36a is positive with respect to plate 36b by an amount equal to the voltage at source terminal 14s, and capacitor 44 is uncharged. As will be seen later, the unique arrangement of the circuit components of stage 38 in cooperation with additional circuitry to be described, enables the detector to operate in an advantageous fashion.
A relay driver stage 46 is connected to the output of amplifier stage 38. Stage 46 comprises a resistor 48, a capacitor 50, a transistor 52 and a relay 54. Resistor 48 is connected between terminal 400 of amplifier 40 and the base terminal 52b of transistor 52 to provide suitable base current drive for transistor 52. Capacitor 50 has one plate 500 connected to the junction of resistor 48 and terminal 52b and its other plate 50b connected to the emitter terminal 52e of transistor 52. Emitter terminal 522 is connected to bus 32. Relay 54 has 'a coil 54a which is connected between the collector terminal 520 of transistor 52 and bus 28. Relay 54 further includes relay contacts 54b operable with energization of coil 54a; Contacts 54b are connected in an; alarm circuit 56 which comprises a battery 58, a warning buzzer 60 and a plug-in jack 62. Battery 58, buzzer 60 and contacts 54b are connected'in a series circuit. Jack 62 is intended to adapt contacts 54b to operate accessory warning circuits other than buzzer 60. Circuits 46 and 56 operate as follows. When a detection signal of sufficient amplitude is generated at terminal 400 of amplifier 40, transistor 52 conducts to energize relay coil 54a. Relay 54 in turn closes contacts 54b to energize buzzer 60 from battery 58 thereby sounding a warning to indicate the presence of an intruder. Buzzer 60 continues to sound until the detection signal at terminal 400 ceases, at which time, relay coil 54a is de-energized thereby opening contacts 54b and disconnecting buzzer 60 from battery 58. Resistor 48 and capacitor 50 have a filtering effect on the high frequency signals and tend to assist the resistor-capacitor pairs 18-20, 42-44.
A lock-in circuit 64 is operatively associated with amplifier stage 38 and cooperates with circuitry of stage 38 for resetting the detector after a detection signal has been generated at terminal 40c. Stage 64 comprises a transistor 66 and a pair of resistors 68, 70. The collector terminal 66c of transistor 66 is connected to the junction of resistor 34 and capacitor 36. One termi- The intrusion detector operates as follows. Upon an intruder entering the area in which the detector is located, the intruders movement disrupts the electrostatic field in the vicinity. Antenna l0 senses this change in the electrostatic field with the signals generated in the antenna being coupled to input stage 12. Stage 12 amplifies the negative portions of these signals, and the voltage at source terminal 14s drops from its 4 volts quiescent level (i.e. becomes less positive). Capacitor 36 tends to follow this voltage drop by establishing a discharging current from plate 36a through resistor 34, through the parallel combination of resistor 18 and capacitor 20, through amplifier 40, through the parallel combination of resistor 42 and capacitor 44 and back to the negative plate 36b. Accordingly, as capacitor 36 discharges, the current flow through resistor 42 causes amplifier 40 to develop a positive voltage at terminal 400. This positive voltage operates both relay driver 46 and lock-in circuit 64. Buzzer 60 immediately sounds to indicate the presence of an intruder and lockin circuit 64 immediately causes stage 38 to drive the voltage at terminal 40c to positive saturation. Upon actuation of lock-in circuit 64, transistor 66 essentially shorts plate 36a of capacitor 36 to common. As a result, the discharging current from capacitor 36 bypasses resistor 18 and capacitor 20, and now flows from plate 36a through the collector-emitter of transistor 66, through amplifier 40, through the parallel combination of resistor 42 and capacitor 44 and back to plate 36b. The discharge current magnitude increases, driving amplifier 40 to positive saturation. Amplifier 40 remains saturated to continue sounding buzzer 60 so long as capacitor 36 can supply sufficient current through resistor 42 to maintain the voltage differential between input terminal 40a and output terminal 40c of amplifier 40. When the charge of capacitor 36 has been depleted to a point where discharging current can no longer maintain this voltage, amplifier 40 comes out of positive saturation with the voltage at terminal 40c dropping back toward zero volts. Prior to the output voltage reaching zero volts, transistor 66 begins to switch off increasingly blocking the current flow through the collector-emitter circuit of the transistor. Capacitor 36 now tends to recharge to the voltage at terminal 14s which voltage, even when signals are being received, does not deviate very much from its 4 volts quiescent level. Positive current now flows into terminal 40a and the current flow through resistor 42 is such that stage 38 operates to develop a negative voltage at terminal 400. This rapidly turns off relay driver 46 to shut off buzzer 60, and likewise fully shuts off transistor 66. When capacitor 36 is recharged to approximately its four volt quiescent level, the output of amplifier 40 returns to zero volts, and the detector is again armed for detecting movement of the same or additional intruders. v
When lock-in circuit 64 may be responsive to the same magnitude of voltage as relay driver stage 46, it is possible for lock-in circuit 64 to be responsive to a slightly higher level of voltage at terminal 40c than is stage 46. Where this is the case, relay driver 46 is first actuated to energize relay 54. The energization of coil 54a may cause a drop in the voltage of bus 28 which will occasion a further reduction in voltage at terminal 14s. This further reduction in voltage will be coupled to stage 38 to further increase the output voltage at terminal 400 to a level sufficient to actuate circuit 64. Alternatively, if relay 54 is mounted in proximity to circuit 64, the radiated field created when the relay is energized may be sufficient to trigger operation of circuit 64.
The intrusion detector is advantageous in that it can be armed by an authorized person without accidentally setting off the detector. The authorized person can turn onthe detector by closing switch 26. The detector is not immediately armed upon closure of switch 26 because capacitor 36 is uncharged when the detector is off. Upon closure of switch 26, power is supplied to stage 12, and capacitor 36 charges as the voltage at terminal 14s rises to its quiescent level of approximately 4 volts. The charging current through capacitor 36 causes amplifier stage 38 to develop negative voltage at terminal 400 so that buzzer 60 can not sound. Since it requires approximately thirty seconds to charge capacitor 36 for the specific circuit components identified in the parts list, the person who has turned on the detector has 30 seconds in which to leave the area. For a unit having a range of 20 to 40 feet for example, this time interval provides sufficient time for the person to leave before the detector becomes armed. Once the detector is armed, any intruder entering the surrounding area will trip the detector to sound buzzer'60. Buzzer 60 will continue to sound for approximately thirty seconds even if the intruder freezes. After buzzer 60 stops, the detector automatically resets itself during the next 30 seconds by recharging capacitor 36. Once capacitor 36 is recharged, the detector is again armed and will signal any additional movement by the intruder. The detector is further advantageous in that its fast response provides hard on-off driving of relay 54 so that buzzer 60 does not chatter.
It will be observed that the solid state construction I renders the detector highly reliable and enables the detector to be packaged as a compact portable unit. The unique arrangement and utilization of circuit components for performing multiple functions permits the detector to be manufactures with a minimumnumber of parts thereby keeping its cost low and contributing to the overall reliability of the detector. The detector requires no adjustment except for the desired sensitivity which is quickly achieved by adjusting antenna to the desired length. Since the detector is entirely passive, in that it radiates no external signals, the intruder will be unable to determine the resence of the detector by means of radiation detecting equipment.
While it will be apparent that the invention herein disclosed is well calculatedto achieve the benefits and advantages as hereinabove set forth, it will be appreciated thatthe invention is susceptible to modification, variation and change without departing from the spirit thereof.
PARTS LIST Transistor l4 21*13819- Transistor 16 2N3S65 Transistor 66 2N5l72 Transistor 52 2N5l72 Amplifier 40 RC 741 DN (Raytheon) Resistor 18 10 K ohms Remain 3 76 ohms Resistor 68 l0 K ohms Resistor 70 4.7 K ohms Resistor 42 l M ohms Resistor 48 2.2 K ohms Capacitor 100 pf Capacitor 36 47 p.f Capacitor 44 0.1 pf Capacitor 50 22 pl We claim: 1. In an intrustion detector, the combination comprising antenna means responsive to the surroundingv means operatively coupling said reset circuit means to said detection circuit output circuit means and means operatively coupling said reset circuit means to said'detection circuit input circuit means, said reset circuit means being responsive to said detection signal for causing said detection circuit means to be electricaly reset and to terminate the detection signal so that upon a subsequent occurrence of said preselected change in the electrostatic field, said detection circuit means generates a subsequent detection signal.
2. The combination of claim 1 wherein said reset circuit means comprises switch means responsive to said detection signal and said means operatively coupling said reset circuit means to said detection circuit input circuit means comprises means operatively coupling said switch means in circuit with said detection circuit input circuit means, said switch means being operative in response to said detection signal for temporarily decoupling said antenna means from said detection circuit means.
3. The combination of claim 2 wherein said switch means comprises a solid state switch.
4. The combination of claim 3 wherein said switch comprises a transistor. I
5. The combination of claim 4 wherein said transistor is arranged to conduct in response to said detection signal. 1
6. The combination of claim 1 wherein said reset circuit means comprises a solid state switch arranged to decouple said antenna means from said detection circuit means and having three terminals, said means operatively coupling said reset circuit means to said detection circuit input circuit means comprises means operatively coupling two of said switch terminals to said detection circuit input circuit means, said switch being operative to decouple said antenna means from said detection circuit means via said two terminals, and said means operatively coupling said reset circuit means to said detection circuit output circuit means comprises means operatively coupling the third of said switch terminals to said detection circuit output circuit means for minal is operatively coupled with said detector circuit output circuit means.
9. The combination of claim 8 wherein said transistor is arranged to short circuit the connection between said antenna means and said detection circuit means in response to said detection signal thereby decoupling the antenna means from the detection circuit means.
10. The combination of claim 1 wherein said detection circuit means comprises amplifier means having an input and an output, said means operatively coupling said reset circuit means to said detection circuit input circuit means comprising means operatively coupling said reset circuit means to said amplifier means input and said means operatively coupling said reset circuit means to said detection circuit output circuit means comprising means operatively coupling said reset circuit means to said amplifier means output.
1 l. The combination of claim 10 wherein said amplifier means comprises an operational amplifier.
12. The combination of claim 11 further including feedback circuit means operatively ocupling the output of said operational amplifier to the input of said operational amplifier.
13. The combination of claim 12 wherein said reset circuit means comprises switch means operatively connected with said detection circuit input circuit means and forming a circuit path with said feedback circuit means, said switch means being responsive to the detection signal for causing a transient current flow from the amplifier output through said feedback circuit means to the amplifier input, said circuit path including means responsive to said transient current flow for resetting the amplifier at a selected time interval after the generation of the detection signal thereby terminating the detection signal.
14. The combination of claim 13 wherein said means responsive to the transient current flow comprises a capacitor.
15. The combination of claim 14 wherein said capacitor is connected in circuit between said switch means and said amplifier input.
16. The combination of claim 15 wherein said feedback circuit means comprises the parallel combination of a resistor and a capacitor.
17. In an intrusion detector of the type wherein an .antenna supplies an input signal to a detection circuit with the input signal varying in accordance with changes in the electrostatic field in the vicinity of the antenna, the combination comprising an operational amplifier having an input and an output, coupling circuit means operatively coupling the input signal to the input of said operational amplifier, said amplifier being responsive to a preselected level of the input signal for generating a detection signal at the amplifier output, feedback circuit means operatively coupling the output of said amplifier to the input of said amplifier and switching means operatively coupled with one of said circuit means and responsive to the detection signal for causing the input signal to be temporarily decoupled from said amplifier.
18. The combination of claim 17 including holding circuit means responsive to the detection signal for maintaining the detection signal for a selected time period while the input signal is decoupled from said amplifier.
19. The combination of claim 17 including holding circuit means responsive to the detection signal for holding the detection signal for a selected time interval and then terminating the detection signal prior to the time that the input signal is recoupled to said amplifier.
20. The combination of claim 17 wherein said switching means is operatively coupledwith said coupling circuit means.
21. The combination of claim 20 wherein said switching means when actuated by the detection signal forms a circuit path through said coupling circuit means and said feedback circuit means which creates a signal at the input of said amplifier which causes the amplifier to maintain the detection signal for a preselected time period.
22. The combination of claim 21 wherein said switching means terminates the detection signal at the end of the preselected time period and prior to the recoupling of the input signal to the amplifier.
23. The combination of claim 20 wherein said circuit means comprises an energy storage device operatively coupled to the input of said amplifier and said switch means, when actuated by the detection signal, causes a current to flow in a selected direction in said device and in said feedback circuit means and thereby maintaining the detection signal for a preselected period of time.
24. The combination of claim 23 wherein said cou- 'pling circuit means comprises means responsive to the termination of the detection signal for causing a current flow in said device and siad feedback circuit means in a direction opposite said selected direction and thereby preventing the generation of the detection signal for a preselected time interval subsequent to the termination of the detection signal.
25. The combination of claim 24 wherein said energy storage device comprises a capacitor.
26. The combination of claim 25 wherein said feedback circuit means comprises the parallel combination of a resistor and a capacitor.
27. The combination of claim 26 wherein oneplate of said capacitor is connected to the input of said am plifier and the other plate of said capacitor is connected to said switch means.
28. The combination of claim 27 wherein said switch means comprises a transistor.
29. In an intrusion detector for detecting changes in the surrounding electrostatic field in a frequency band between a frequency slightly greater than zero cycles per second and a frequency less than sixty cycles per second, the combination comprising receiving means for receiving changes in the surrounding electrostatic field, amplifying means for amplifying the received signals, said amplifying means generating an output signal in response to a selected change in the electrostatic field, circuit means responsive to the output signal for maintaining the output signal for a predetermined time interval and thereafter preventing generation of the output signal for a subsequent predetermined time interval.
30. In an intrusion detector, the combination comprising antenna means responsive to the surrounding electrostatic field, detection circuit means adapted to be armed for detecting a preselected change in the electrostatic field, means operatively coupling said antenna means to said detection circuit means and arming circuit means comprising delay circuit means operable for arming said detector means at a predetermined time interval after actuation of said arming circuit means so circuit means to in turn change the stored energy signal, said detection circuit means being armed in response to a preselected change in the stored energy signal, said energy storage means comprising a capacitor operatively coupled between said antenna means and said detection circuit means.
' UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,771,152 I Dated November 6, 1973 Inventor(s) Joseph R. Dettling, John F. Farnham, J-r., and Stephen T.
/ Gaines It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:
Column 3, 1ine 4 "elastrostatic" should be --electrostatic---;
line 8, "bandwith" should be -bandwidth".
- Column 4, line 62, "When" should be While.
Column 5, line'52, "resence" should be --presence--.
Column 7, line 1, "detector" should be --detection--; line 21, "ocupling" should be -,-coupling--. Column 8, line 18, after "said" insert --coupling--; lines 23 and 24;, "maintaining" should be --maintain--; line 29, "siad" (second occurrence) should be -said--; line 67, "detector" should be ---d etection circuit--.
' Column 9, line 2, "th" (2nd occurrence) should be --the--.
. Signed and sealed this 26th day of November 1974.
McCOY M. GIBSON JR. c. MARSHALL DANN Arresting Qffiice'r Commissioner, of Patents FORM PO-IOSd (was) i us coMM oc 0031s ps9 I U.$. GOVIINNENT PRINTING OFFICE l I." O'Sii'l"
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|International Classification||G08B13/26, G08B13/22|
|Sep 2, 1993||AS||Assignment|
Owner name: BANKERS TRUST COMPANY, NEW YORK
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