US 3775740 A
A train describer display apparatus displays train description information as a bright-up pattern of alphanumeric characters on the rasters of small cathode ray tubes by stepping a shift register operating with serial read-out in synchronism with the scanning circuits of the cathode ray tubes. The displayed data is changed by applying new information to a selected shift register from a store which is filled from a data highway, the data highway also operating in conjunction with an address highway to determine which cathode ray tube out of a selected group of cathode ray tubes is to receive a modified display.
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Description (OCR text may contain errors)
United States Patent [191 Douglas Nov. 27, 197
[5 DISPLAY APPARATUS 3,685,039 8/1972 Flanagan 340/324 [7 5 Inventor: Colin Grahame Douglas, London,
E l d Primary Examiner-Ralph D. Blakeslee Attorney-Roberts B. Larson et a].
 Assrgnee: Westinghouse Brake and Signal Company, Limited, London,
England  ABSTRACT  Filed: Nov. 29, 1971 A train describer display apparatus displays train (1 Appl. No.: 202,929
Foreign Application Priority Data Dec. 22, 1970 Great Britain 60708/70 References Cited UNITED STATES PATENTS 12/1970 Guzik 340/23 MODIFICATION scription information as a bright-up pattern of alph numeric characters on the rasters of small cathode r2 tubes by stepping a shift register operating with seri read-out in synchronism with the scanning circuits 4 the cathode ray tubes. The displayed data is change by applying new information to a selected shift regi ter from a store which is filled from a data highwa the data highway also operating in conjunction with 2 address highway to determine which cathode ray tut out of a selected group of cathode ray tubes is to n ceive a modified display.
3 Claims, 2 Drawing Figures EQ E R i i sIzA A IR Imam- F I .I GL/l REGISTER SIZI I BASE M We XI I Ea I 0 VA] I TB 1 INPUT I I u I I I REGISTER I 2 I I I i m I I I i 6H2 i R2 VAZ I i I I I I CPTZI I GL I4 sIzI I I X14 I l VAI4 I 62 I I lm PAR'TY I W I cTR14 ECKING I I I I MODULE i Isles I l i DD I h I RESS REGISTER I L I I TSIRC I A2 I y I I DREss I I DECODER I II )I I l I "-|\::I I L VA 56 U256 DISPLAY APPARATUS This invention relates to display apparatus and relates more especially to train describer display apparatus employing cathode ray tubes for displaying legible characters.
Train description apparatus is normally operable to present to an operator at a control panel representations of details of trains present in a railway track system represented by a track diagram of the area supervised by the operator. The track diagram is normally provided with such signal control switches and route setting and indication facilities as are required for the purposes of system control.
In response to received coded information concerning the states or conditions of operation of various portions of a railway track system, a computer may be provided to operate to apply to various ancillary functions via suitable data and address highways,'coded output information concerning indications to be displayed or functions to be performed. These may include point sensing, signal operation, points setting, alarms and teleprinter operations. The indications may include the illumination of signal and points indication lights and track occupancy lights, together with displays of legible characters indicating to an operator details of trains and various positions in a railway territory covered by the system control.
According to the present invention there is provided display apparatus including a plurality of concomitantly scannable display units upon which characters are displayable the characters being formed-by the presence or absence of excitation (such as bright-up signals) in allotted discrete positions, a plurality of groups of main storage means, one such means for each display device and each said main storage means having a plurality of data storage locations for storing bits representing the desired excitation of corresponding positions of the respective display unit and the main storage means being provided with means for operating them in synchronism with the respective display means to present the appropriate bits in sqquence to the display means, the apparatus also including for generating the bits in the main storage means a shift register and an input register operable on recognition of a received address code to receive group by group from a data highway groups of bits and in turn to apply said received groups of bits to the shift register and means responsive to a further address code for selecting the group of main storage means which contains a specific main storage means to which bit-contents of the shift register are to be transferred.
Preferably, the means for selecting groups of storage means to which the contents of the shift register is to be applied is responsive to further addressing means and means responsive to further received data bits in the input register for selecting the storage means in a selected group.
In order that the invention may be more clearly understood and readily carried into effect, the same will be further described by way of example with reference to the accompanying drawing of which,
FIG. 1 illustrates in schematic form a cathode ray tube train describer apparatus employing the invention and FIG. 2 illustrates the format of character display on each cathode ray tube.
Referring to FIG. 1 of the drawing, the apparatus erates to provide displays of four legible characters each of 5 6 cathode ray tubes CRTl, CRT2 CR. These cathode ray tubes are divided into four group 14 tubes the first two and the fourteenth of the 1 group of these tubes and the last of the last gro namely the fifty sixth tube are shown. Conventic scanning time base circuits are provided representec block TB for scanning all the tubes CRTI to CR'l concomitantly and cyclicly to display characters in cordance with applied excitation or bright-up sign The scanning takes place in response to a master ch generator C which also governs the progression of bright-up signals to the display tubes and provi clock pulses to the other parts of the apparatus D/ and SRA. The scanning of the tubes is such that four characters displayed on each tube are produced five by seven dot patterns arranged side-by-side as in cated by the four frames shown in FIG. 2. The scann is arranged to operate line-by-line vertically proceed across the respective displays of the four characte Thus, the scanning proceeds down one seven-dot li: up the next seven-dot line and so on, the time b: waveform leaving a space between each display character as also indicated in FIG. 2.
For the purposes of supplying the excitation bright-up signals for the first group of cathode ray tul CRTl to CRT14, a first group of commercially avz able integrated circuit shift registers SR1 to SR14 provided. Three further such groups SRB, SRC, SI of shift registers are provided and shown dotted in 1 drawing, for the three other groups of 14 cathode 1 tubes, all the shift registers being operated in step the master clock. The signals derived from these reg ters are applied via suitably available video-amplifii (the first two VAl, VA2 and two others VA14 a VA56 of which are shown) to the respective catho ray tubes CRTl to CRT56. The video-amplifiers V4 to VA56 are typically conveniently provided in circ modules each of which may comprise 28 amplifiers, t arrangement thus requiring two such modules for t 56 tubes provided. 7
As shown, the shift registers such as SR1 to SR14 a each provided with cycling paths such that the four d play characters on each tube are presented repetitive to produce in known manner a visually continuous (I play.
For the purposes of establishing or changing the si nals in the shift registers SR1 to SR56, there are pr vided a plurality of gates GL/l to GL/56 in the inpl. to these shift registers (only GL/ 1, GL/2 and GL/l4 which are shown) via which modified display data f a given tube can be applied to the respective shift reg: ter from a modification word register MWR of a displ; access module DAM. The modification word regist derives data bits from an input register IR in modu DAM which is arranged when addressed to recei eleven 14-bit words successively in parallel fashir from a 16-bit data highway DH. The first 10 won comprise, as will be explained hereafter, one hLll'ldl't and 40 modification bits for subsequent serial readto the modification word register MWR and the ele enth word of the input register IR has a single suitab positioned bit to indicate on one of output lines X1 1 X14 the destination register in the display storag means of one selected group SRA, SRB, SRC or SR of 14 registers the contents of which is to be modifier In addition to the 14 bits presented at any given time to the input register [R from the data highway, the remaining two bits positions afi'ord two further bits for the purposes of parity checking of the input 14-bit words to the input register 1R. These parity bits are applied from the 16-bit data highway to the parity checking module PCM a check output from which is applied as one control input to a gate G2, the second control input to gate G2 is derived from an address decoder AD connected to the 8-bit address highway AH. The address decoder also has four further address decode outputs to an address register AR the addresses affected by this register AR being the gates G1 to G14, G to G28, G29 to G42 and G43 to G56 associated with the respective groups of display storage shift registers referred to above.
In operation of the apparatus shown in FIG. 1, it will 9e appreciated from the foregoing that four alphaiumeric characters can be displayed on each of the 56 :athode ray tubes at one time. Bright-up data for the :athode ray tubes is stored in the 150 bit shift registers 3121 to SR56 and the bits in these registers are shifted me place to the right each time that the cathode ray ube beams are deflected to a new dot position on the creen. The stored pattern in the shift registers is thus hifted along 140 times during the time taken to scan he whole face of a cathode ray tube. The further 10 hifts provided by the one hundred and fifty bit regisers do not produce output digits to the respective dislay tubes but serve to accommodate the time base flyack time for the tubes. As each bit of the bright-up attern attains the end of the register it is displaced on he cathode ray tube and returned to the front of the egister. The re-circulating train description characters 1 each shift register are thus stored and displayed conlnuously until, when required, new data is substituted 3r it.
Whenever the input conditions to the train describer ictate that a movement of a train from one berth to nother is required to be displayed the computer which not shown in arranged to feed the new data to the 16- it data highway DH and to the address highway AH a ode pattern corresponding to the train description roup SRA, SRB, SRC or SRD which contains the dislay data which is to be changed and inserts it into the ore associated with the new berth position. The 16-bit ords from the computer shared between the input :gister IR and the parity check module PCM contain, mentioned above, 14 data bits and two parity check ts. The 14 data bits therefore correspond to two vertill columns of a character to be displayed on a given lthode ray tube. The address decoder AD of the disay access module DAM answers to a total of five adess codes.
The first address indicates to DAM that the data asciated with it is part of a train description bright-up .ttern and is decoded as an input to G2 whilst the her transmitted one of four addresses is employed to iicate the one group of shift registers, as referred to ove, containing the one shift register the contents of lich is to be changed.
The individual shift system is indicated by a bit in the ta word associated with these other four addresses.
In order to up-date a given cathode ray tube display,
1 data words have 'to be transferred to the data access :1 modify module DAM accompanied by a first ad- :ss code Al to which the module responds to provide an input to G2, followed by an eleventh word accompanied by one of the other addresses to together determine which display tube of a selected group of 14 cath ode ray is to be modified. When the first of the group of words is output from the computer to the module DAM, the parity is checked by the parity check module PCM and if the parity is correct and the appropriate address is received by AD, the data thus checked is gated into the input register IR by an input signal from gate G2, and then shifted serially into the first 14 positions of thelSO-bit shift register MWR. The signal from G2 also provides a data-accepted" signal back to the computer on line KC. The subsequent transfers from the computer to the input register IR occur in a similar fashion and are progressively shifted serially into the modification word register MWR until all bits of new data have been received and stored in MWR. The eleventh word of the group, if its paritysis correct, is gated into the input register but not shifted into the shift register. At the same time, the address A2, A3, A4, A5 with which the eleventh word is associated is registered in the address register AR. As indicated above this address along with the single bit eleventh word in IR dictates via the gates GL/l to GL/56, the shift register out of SR1 to SR56 of shich the contents is required to be up-date. As shown in the drawing a connection is shown between the time base unit and DAM. At the commencement of the next complete time base scan of the registers SR1 to SR56, as given by a signal over the said connection the cycling path for the selected -bit register is interrupted by gate means (not shown) for the duration of the scan and the bright-up pattern stored in the shift register MWR is transferred serially during this cycle into the appropriate selected shift register. At the end of this particular time base cycle, the cycling path for the selected 150- bit register is reclosed and the display continues to proceed as before, the selected shift register now containing the newer modified display bright-up pattern.
Apparatus embodying the present invention can be constructed in modular form employing integrated circuit storage using techniques which are known of themselves and most failures which may occur may be arranged to result in the loss of the output to one cathode ray display tube only. Other facilities moreover may be visualised by those skilled in the art. For example, in the event that it is required to clear the display on all or a selected number of cathode ray display tubes, the stores SR1 to SRS6 may be selected and in one cycle by suitable gating means the contents of the thus selected registers can be cleared. It is not therefore necessary to employ 56 cycles (for example) to clear the 56 stores.
Having thus described our invention what we claim is:
1. Display apparatus including a plurality of concomitantiy scannable display units upon which characters are displayable, the characters being formed by the presence or absence of excitation in allotted descrete positions, a plurality of groups of main storage means, one such means being associated with each display device and each said main storage means having a plurality of data storage locations for storing bits representing the desired excitation of corresponding positions of the associated display unit and the main storage means including means for operating said main storage means in synchronism with the associated display means to present the appropriate bits in sequence to the display means, the apparatus also including means for generating the bits in the main storage means, a shift register and an input register for responsive to the recognition of a received address code, receiving, group by group from a data highway, groups of bits and for, in turn, applying said received groups of bits to the shift register and means responsive to a further address code for se lecting the group of main storage means which contains a specific main storage means to which bit-contents of formed by the presence or absence of excitation sigr operable corresponding to allotted positions, a m storage shifting register associated with each said vice including a plurality of data bit storage locatit for storing bits in the desired excitation pattern, me for stepping the registers in synchronism with scann of the display units to present the excitation signal: the appropriate sequences to the display means, input register for receiving up-dating data from a d highway for transfer to a said shift register and a sel tion code for determing which of the registers of a lected said group is to be selected, an address decor responsive to an address presented on an address hi way for determining which is the selected said gro a modification word register for receiving from input register successive received words to make u word to be transferred and gate means responsive to address decoded by the address decoder and a selt tion code from the input register for transferring a W( in the modification word register to the selected In:
storage shift register.