|Publication number||US3777227 A|
|Publication date||Dec 4, 1973|
|Filing date||Aug 21, 1972|
|Priority date||Aug 21, 1972|
|Also published as||CA993566A, CA993566A1|
|Publication number||US 3777227 A, US 3777227A, US-A-3777227, US3777227 A, US3777227A|
|Inventors||S Krishna, J Davis|
|Original Assignee||Westinghouse Electric Corp|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Referenced by (48), Classifications (28)|
|External Links: USPTO, USPTO Assignment, Espacenet|
United States Paten ['19] Krishna et al.
' 145']- Dec. 4, 1973 DOUBLE DIFFUSED HIGH VOLTAGE,
HIGH CURRENT NPN TRANSISTOR  Inventors: Surinder Krishna, Greensbul'g; John R. Davis, Jr., Export, both of Pa.
 Assignee: Westinghouse Electric Corporation,
221 Filed: Aug. 21, 1972 211 App]. No.2 282,624
 US. Cl. 317/235 R, 317/235 AJ, 317/235 AM, 317/235 AN, 317/235 AQ  Int. Cl. H01] 5/00  Field .of Search 317/235  References Cited I UNlTED STATES PATENTS Schnable 148/ l .5
57 ABSTRACT An NPN transistor with high voltage and high current capacities is provided in a semiconductor body having a thin internal portion and a thick integral peripheral portion. The thin portion has a substantially uniform width of greater than about 28 microns and oppositely facing surface areas each of greater than about 0.10 cm The thick peripheral portion has a width greater than about 150 microns and annular dimension i.e. radial width greater than 10 microns. Thebase region has two contiguous impurity portions. A first impurity portion adjoins a major, preferably planar surface of the semiconductor body at the peripheral portion and has an impurity concentration of boron of at least l X 10 atoms per cubic centimeter at the surface and a steep impurity concentration gradient to provide good ohmic and thermal properties. A second contiguous impurity portion is in internal portions of the body be- 3,697,827 10/ 1972 Simon 317/235 tween itt d ll t i n d ha a lower 2 g g f i at impurity concentration of gallium and/or aluminum 3O88'888 1963 no son et 204143 and shallower impurity concentration gradient than 218291999 4/1958 Gudmundsen.... 148/33 P impufity F and 3,487,276 12/1969 Wolley 317 235 P the base are formed by the simultaneous difi'usion of boron and gallium and/or Primary Examiner-John W. Huckert aluminum Assistant ExaminerE. Wojciechowicz Attorney-F. Shapoe et al. 4 Chums 9 Drawing g res 42 I8 -34 36 39 l2 '37 4| I8 42 I8 v l4 \\y\\-1\\1\ v 5O 38 40 I7 29 32 I3 35 3| IO 32 3o DOUBLE DIFFUSED HIGH VOLTAGE, HIGH CURRENT NPN TRANSISTOR FIELD OF THE INVENTION The present invention relates to semiconductor devices and particularly transistors. It is useful in providing a transistor with high voltage capacity, e.g. 2000 volts, as well as high current capacity, e.g. 100 am- 7 peres.
BACKGROUND OF THE INVENTION Junction transistors are well known in the art. They are formed in single crystal semiconductor bodies or wafers having two opposed major surfaces. They have emitter and collector regions of one semiconductive type of impurity adjoining the major surfaces and a base region of the opposite semiconductive type of impurity in the interior of the body between the emitter and collector regions. Two PN junctions are thus present, one at the transition between the emitter and base regions and the other at the transition between the base and collector regions.
Efforts in the past have been directed primarily to optransistors having high voltage, high speed and high current operating characteristics. Solutions to a number of the difficulties have been presented in the copending applications Ser. No. 257,088, filed May 26,
- 1972, Ser. No. 249,981, filed May 3, 1972, Ser. No.
218,300, filed Jan. 17, 1972 and Ser. No. 259,404, filed June 5, 1972. But a problem still remains of making transistors with both high voltage and high current capacities and in particular NPN transistors with such capacities that are complimentary to PNP transistors, i.e. have the same operating characteristics.
In order to increase the current capacity of a high voltage transistor, it has been known to increase the impurity concentration in the base region adjacent the ohmic contact at the surface of the semiconductor body. In this way the voltage drop between the emitter and base regions with the collector region open (i.e. VEBO) is decreased and the injection efficiency and current gain correspondingly increased. However, an added diffusion step with attendant increases in expense and decreases in quality control has heretofore been required. Moreover, difficulty was encountered in making complimentary pairs of NPN and PNP transistors because of the differing diffusion rates of N and P type impurities.
The present invention overcomes these difficulties and provides an inexpensive NPN transistor with both high voltage and high current capacities, and with complimentary performance characteristics to available PNP transistors.
SUMMARY OF THE INVENTION An NPN transistor with high voltage and high current capacities is provided in a semiconductor body of greater than 150 microns in thickness having opposed major surfaces. The body has a thin internal portion with a substantially uniform width of greater than about 28 microns and preferably greater than 94 microns and oppositely facing surface areas each of greater than about 0.10 cm. The body also has an integral thick peripheral portion with a width corresponding to the thickness of the body and an annular dimension i.e. ra-
' timizing the transistor structure to produce economical dial width greater than 10 microns. An abrupt transition is hence made between the thin internal portion and the thick peripheral portion.
The base region of P type impurity has two contiguous impurity regions. A first impurity portion adjoins a major, preferably planar surface of the semiconductor body at the peripheral portion and has an impurity concentration of boron of at least l X 10 atoms per cubic centimeter at the surface and a steep impurity concentration gradient to provide good ohmic and thermal properties. A second contiguous impurity portion is in internal portions of the body between emitter and collector regions and has a lower impurity concentration of gallium and/or aluminum and shallower impurity.
concentration gradient than the first impurity portion. Preferably the first and second impurity portions of the base region are formed by the simultaneous diffusion of boron and gallium and/or aluminum into a major surface of the semiconductor body.
By way of explanation, it should be noted that the impurity concentration gradient is the change in impurity concentration with a change in distance from a reference point such as a surface or junction of the transistor. A steep gradient is one which has relatively large and abrupt changes in impurity concentrations with changes in distance. A shallow gradient is one which has relatively small and gradual changes in impurity concentrations with changes in distance.
Other details, objects and advantages of the invention will become apparent as the following description of a present preferred embodiment and a present preferred method of practicing the same proceeds.
BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings, the present preferred embodiments of the invention and thepresent preferred methods of practicing the invention are illustrated in which:
FIGS. 1-8 are cross-sectional views in elevation through the center of an NPN transistor at various stages of manufacture;
FIG. 8 is a cross-sectional view through the center of a finished NPN transistor; and
FIG. 9 is an impurity concentration profile of the NPN transistor of FIG. 8.
DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1,- a circular silicon semiconductor wafer or body 10 of a thickness of greater than 150 microns, such as 250 microns, has a given level of N-type impurity therethrough corresponding to a resistivity of greater than 30 ohm-ems and preferably greater than ohm-cms. Preferably the body has a resistivity therethrough of at least to ohm-ems corresponding to a low impurity concentration of about 6 X 10 atoms per cubic centimeter or less.
Body 10 is disposed in a diffusion furnace. It has simultaneously diffused into opposed major surfaces 11 and 12 and curvilinear side surfaces 13 boron and gallium and/or aluminum to form P impurity region 14 adjoining said surfaces preferably to a depth of from 20 to 75 microns and most desirably about 30 microns. The diffusion is preferably performed in an inert atmosphere, e.g. argon, in a closed or open quartz tube, e.g. at about 1235C. for about 30 minutes. If a closed tube is used, solid difiusion sources are necessarily used; if an open tube is used, gas diffusion sources are preferably used where possible. For further description of the simultaneous diffusion of boron and gallium, see application Ser. No. 218,097, filed Jan. I7, 1972, and assigned to the same assignee as the present invention.
P impurity region 14 divides itself by virtue of the diverse diffusion rates of boron and gallium and/or aluminum into first and second impurity portions 15 and 16. First impurity portion 15 adjoins surfaces l1, l2 and 13, has a high impurity concentration, such as greater than I X 10 atoms per cubic centimeter at the surfaces, and has a steep impurity concentration gradient, such as from about 2.5 X 10 atoms/cm (a 40 micron depth diffusion of l X 10 atoms/cm surface concentration) to 1.0 X 10 atoms/cm (a 10 micron depth diffusion of 1 X l atoms/cm surface concentration). Second impurity portion 16 is contiguous with the first impurity portion 15 and extends into the interior of body 10. Second impurity portion 16 has a lower impurity concentration than the first impurity portion 15, e.g. ranging from about 1 X 10 to l X l0 atoms/cm, and has a shallower impurity concentration gradient than the first impurity portion 15, e.g. ranging from about 1.3 X 10 atoms/cm (a 75 micron depth diffusion of l X 10 atoms/cm surface concentration) to about X 10 atoms/cm (a 20 micron depth diffusion of l X 10 atoms/cm surface concentration).
Relative widths of first and second impurity regions and 16 can be controlled to provide the desired electrical characteristics of the transistor. The ratio of the width of the first impurity region 15 to the width of the second impurity region 16 is controlled by varying the ratio of the concentration of boron to the concentration of gallium and/or aluminum. If a closed tube is used, the ratio is governed by saturation conditions in the tube; and the saturation conditions are a function of the temperature and pressure in the tube. With standard pressure, the temperature can range from the minimum temperature to vaporize the particular diffusion sources (e.g. about 1 100C.) to the temperature at which the semiconductor body 10 becomes plastic (e. g. about l325C.). For optimum electrical characteristics, maximum impurity concentrations are provided at the surfaces. It is therefore preferred that closed tube diffusion be performed as near 1235C. as practicable. Most desirably, however, the open tube technique is used because it provides greater flexibility in controlling the ratio of boron to gallium and/or aluminum. With the open tube, the ratio is not limited to the saturation conditions which can be obtained, but can be varied to provide the desired electrical characteristics in the transistor.
The result of forming P impurity region 14 in body 10 by diffusion is the formation of N- impurity region 17 extending throughout the remainder of the interior of body 10. A PN junction is formed at the transition from P impurity region 14 to N- impurity region 17.
Referring to FIG. 2, P impurity region 14 is removed from adjacent surfaces 11 and 13 preferably by standard lap etching techniques. P impurity region 14 is thus maintained only adjacent major surface 12. Oxide coating 18 is thereafter formed over surfaces ll, 12 and l3'to mask the surfaces for diffusion. The oxide coating is preferably formed by heating the body 10 in an oxygen rich atmosphere such as steam or oxygen for a short period of time, e.g. 30 to 60 minutes.
Still referring to FIG. 2, bonding layer 19 of a metal having strong bonding properties to silicon oxide and to metals is formed over oxide coating 18 at major surface 11. Suitable metals for this purpose are titanium, chromium, aluminum, zirconium, molybdenum, vanadium, columbium, tantalum and tungsten. Preferably bonding layer 19 is formed by depositing the metal by evaporation by procedures well known in the art to a thickness typically of about 500 Angstroms.
Vapor deposited metal layer 20 is subsequently formed over bonding layer 19 to form an adherent metal layer over oxide coating 18 at major surface 11. Preferably the metal selected should be resistant to various etchants that will etch oxide coating 18 and body 10, as well as be readily electroplatable. Suitable metals for the vapor deposited layer are the Group 18, VIA and VIII metals, and particularly gold, platinum, nickel, palladium and tungsten. Preferably, layer 20 is formed by depositing the metal by evaporation by procedures well known in the art to a thickness typically of about 2000 Angstroms.
Thereafter a photomask layer 21 of a type well known in the art is placed over the metal layer 20.
Referring to FIG. 3, coincident windows 22, 23 and 24 are provided in layers, 2.1, 20 and 19, respectively, to expose selected internal areas of oxide coating 18 at surface 11. Window 22 is formed in photomask layer 21 by methods well known in the art, e.g. masking the selected internal portions; exposing the remaining peripheral portions to light to make those portions waterinsoluble; and washing away the unmasked watersoluble portions to leave window 22 in selected internal portions of photomask layer 21. v
Window 23 is then formed by etching through vapor deposited metal layer 20 with a suitable etchant to which photomask layer 21 and bonding layer 19 are resistant. Such etchants vary with the specific metal selected to form layer 20 and are well known to those skilled in the art. For example, a widely used recipe to etch gold is an aqueous solution having 3 parts hydrochloric acid, 1 part nitric acid and 4 parts water.
Thereafter, window 24 is formed in bonding layer 19 by etching through layer 19 with a suitable etchant without attacking the oxide coating 18, the body 10 and other layers. Such etchants also vary with the metal selected to form layer 19, and are widely known and used in the art. For example, a recipe used to etch titanium is a buffered aqueous solution having 1 part ammonium fluoride, 2 parts hydrochloric acid and'5 parts water.
Referring to FIG. 4, photomask layer 21 is removed and etchant resistant metal layer 25 is electroplated over the remainder of layer 20 by standard electroplating methods typically to a thickness from 500 to 10,000 Angstroms and possibly on the order of 2 mils. Etchant resistant layer 25 may be formed by the same metal used to form layer' 20. The elecroplating closes pin holes developed in the layer 20 and forms a continuous etchant resistant coating for the subsequent deep etching step.
Thereafter, the remaining portions of oxide coating 18 at surfaces 12 and 13 are masked. A low solid wax such as Apiezon paraffin or a dental wax is spread over substrate 26 (e.g. one-eighth to one-fourth inch in thickness) of polytetrafluoroethylene, stainless steel coated with gold or glass. The prepared semiconductor body 10 is then embedded in the wax, and the wax solidified to form protective coating 27 over oxide coating 18 at surfaces 12 and 13.
Still referring to FIG. 4, well 28 is etched in semiconductor body to provide body 10 with thin internal portion 29 and a thick peripheral portion 30. Body 10 is immersed in an etchant suitable for etching body 10 and oxide coating 18, and resistant to layer 25 and protective coating 27. The body is continuously agitated in the etchant under carefully adjusted conditions to provide well 28 with a substantially flat foundation surface 31 that is substantially parallel to major surface 12. The composition of the etchant will vary with the composition of body 10 and etchant resistant layer 25. A suitable etchant for etching silicon semiconductor bodies coated with gold is an acid solution having 3 parts hydrofluoric acid, 5 parts acetic acid and parts nitric acid. Adjustments and conditions for obtaining flat foundation surface 31 are known in the art, e.g. turning the container and solution in which body 10 is immersed on an obliquely positioned turntable at a few revolutions per minute.
By precisely controlling the etching conditions (i.e. the concentration of the etchant, length of etching and agitation rate) the dimensions of well 28 and in turn internal portion 29 can be precisely controlled. Internal portion 29 has a substantially uniform width of greater than about 28 microns for 400 volts capacity and preferably greater than about 94 microns for 1000 volts (e.g. 150 microns for 2000 volt capacity, and 190 microns for 3000 volt capacity), and opposed surfaces each of greater than 0.l0 cm in area. Peripheral portion 30 is the width of the starting semiconductor body 10 (e.g. 250 microns) so that there is an abrupt transition from internal portion 29 to peripheral portion 30 at the transition from foundation surface 31 to curvilinear sidewalls 32, which approach parallelity'with side surfaces 13.
In this procedure, the annular dimension of the peripheral portion 30 is also precisely controlled by the size of windows 22, 23 and 24 and the etching rate. As shown, the annular dimension of the peripheral portion 30 is less than the corresponding radial dimension of internal portion 29, and preferably is as small as practicable to minimize the stored charge in the peripheral portion and in turn increase the switching speed of the transistor; see co-pending application Ser. No. 249,981, filed May 3, 1972, and assigned to the same assignee as the present invention. The annular dimension of the peripheral portion 29 must, however, be greater than about l0 microns to provide the handling requirement needed in the manufacture of the transistor.
Referring to FIG. 5, metal layers 19, and 25, substrate 26 and protective coating 27 are removed. Lay-' ers 19, 20 and 25 are removed by a repetition of the etching steps above described in forming windows 23 and 24. Substrate 26 and protective coating 27 are removed by liquifying the wax composition composing coating 27.
Window 33 is then formed in silicon oxide coating 18 at surface 12 by methods, i.e. masking and etching, widely known in the art to expose internal portions of major surface 12.
Referring to FIG. 8, N+ impurity region 34 is formed by diffusing an N type impurity (i.e. phosphorus, antimony, and/or arsenic) and preferably phosphorus into the exposed internal portions of major surface 12. The diffusion is accomplished by heating body 10 in an inert atmosphere containing an impurity producing comfusion time is controlled to determine the concentration and penetration of the impurity. The diffusion is precisely controllable because the geometry of the body 10 permits the formation of a shallow (e.g. as little-as 5 to 10 microns) highly concentrated (e.g. l X 10 atoms/cm") emitter region. In any event, N+ impurity region 34 extends into body 10, e.g. about 20 microns, to adjoin the second impurity portion 16 of P impurity region 14 at internal portion 29 and to form a PN junction therewith.
Also second N+ impurity region is formed, preferably simultaneously, with N+ impurity region 34, by diffusion of N-type impurity into the exposed foundation surface 31 and sidewalls 32 to a desired depth (e. g. 5 to 20 microns). Impurity region 35 reduces the resistivity adjoining the surfaces and provides good ohmic contact to N-impurity region 17.
An alternative procedure is to mask for diffusion with oxide coating 18 after'the thin internal portion 29 is formed by deep etching. To effect this, the wafer or body 10 is cleaned with a suitable etchant and coated with an oxide by heating body 10 in an oxygen-rich atmosphere such as steam or oxygen after layers 19, 20 and 25, substrate 26 and protective coating 27 are removed from the surfaces of the body. The portions of the oxide coating at selected portions of surfaces 11 and 12 are then masked, and the exposed'portions of the oxide coating etched away to expose foundation surface 31 and sidewalls 32 as well as selected internal portions of major surface 12. The above described procedure is then followed to, preferably simultaneously,
- diffuse N+ impurity regions 34 and 35 into the semiconductor body. This alternative, however, increases the number of production steps and the handling after internal portion 29 is formed, and in turn increases the number of rejects during production.
The NPN transistor thus formed has emitter'region 36 corresponding to N+ impurity region 34, base region 37 corresponding to P impurity region 14, and collector region 38 corresponding to N- impurity region 17. Second N+ impurity region 35 is discounted in the transistor operation; it provides good ohmic contact between collector region 38 and metal contact 43. PN junction 39 is formed at the transition between emitter and base regions 36 and 37, and PN junction 40 is formed at the transition between base and collector regions 37 and 38.
The reverse breakdown voltage of N- impurity region 17 is higher than the collector reach-through voltage at internal portion 29. The width of the collector region 38 at peripheral portion 30 is at least 20 percent greater than the collector width at internal portion 39. In turn, the channeling effects at side surfaces 13 are substantially reduced and the voltage capacity of the transistor is governed by the potential across the carrier depletion region at the internal portion of body 10 at collector reach-through.
Referring to FIG. 8, metal contacts 41, 42 and 43 are affixed to semiconductor body 10 to make separate ohmic contacts with emitter region 36, base region 37 and collector region 38, respectively. Metal contact 41 is affixed to major surface 12 at internal portion 29 to contour emitter region36, preferably as closely as possible and thereby optimize the current capacity of the transistor. Metal contact 42 is affixed in an annular shape to major surface 12 at peripheral portion 30.
And metal contact 43 is affixed to contour foundation surface 31 and sidewalls 32; it may also, if desired, extend into peripheral portion 30 at major surface 11, where N+ impurity region 35 is extended correspondingly to provide good ohmic contact. As shown, metal contacts 41., 42 and 43 are formed by providing additional windows 42A in coating 18 at surface 12, evaporating aluminum onto selective portions of the exposed surfaces through windows in the oxide coating to a thickness typically of about 70,000 to 100,000 Angstroms. Preferably, however, metal contact 43 is greater in thickness possibly to even fill-in well 28 completely to'provide a heat sink for the transistor and in turn low, efficient operating temperatures in the transistor.
To complete the making of the transistor, body 10 is spin-etched by known procedures to taper side surfaces 13 to shape the electric fields found in the transistor and in turn further reduce edge leakage and localized voltage breakdown during operation. This tapering is important to reduce surface breakdown above 500 volts capacity and is essential above 2000 volts capacity. Then side surfaces 13 may in some cases, particularly at high voltage capacity, be coated with a protective coating formed by incorporating, for example l,2-dihydroxyanthraquinone (also called alizarin) alone or in a silicone or epoxy resin, to substantially reduce atmospheric effects on the transistor. In any event, an NPN transistor shown in FIG. 8 is thereby formed.
To further explain the invention, the concentration profile of the NPN transistor, shown in FIG. 8, is set forth in FIG. 9. The impurity concentration in P impurity region 14 (base region 37) is the addition of the boron and gallium concentrations minus the residual N- type impurity concentration extending throughout body 10. The impurity concentrations in N+ impurity region 34 (emitter region 36) are the level of impurity concentrations originally present in body 10 plus the N- type impurity diffused into body 10 minus the gallium and boron impurities there present. And the impurity concentration in N- impurity region 17 the active collector region 38) corresponds to the residual impurity concentration throughout the body 10. N+ impurity region 35 is also shown for making good ohmic contact to collector region 38.
The resulting NPN transistor has both high voltage and high current capacities. The transistor action is primarily in the thin internal portion 29 with thick peripheral portion 30 functioning only to maintain the voltage capacity of the transistor. The performance characteristics of the transistor can thereby be optimized. The
impurity level throughout the starting semiconductor 1 body 10 and the width of the collector region at internal portion 29 can be controlled with precision so'that the collector reach-through voltage in the internal portion 29 is just below the design reverse breakdown voltage. No higher voltage capacity need be provided-for safe operating conditions. In addition, the high impurity concentrations in the base region adjacent the contact 42 permits the external voltage drop between the emitter and base regions (collector open) to be decreased and in turn the injection efficiency of the transistor to be increased without reducing the breakdown voltage of the transistor. In turn, the gain and the current capacity of the transistor are correspondingly increased.
While the presently preferred embodiments of the invention and methods for performing them have been specifically described, it is distinctly understood that the invention may be otherwise variously embodied and used within the scope of the following claims.
What is claimed is: I
1. An NPN transistor comprising: a semiconductor body of resistivity of greater than 30 ohm-cms having first and second opposed major surfaces and thin internal and thick peripheral portions; said thin internal portion being of substantially uniform thickness of greater than about 28 microns and having opposed surfaces each of greater than about 0.l0 cm in area, and said thick peripheral portion being of thickness greater than about microns and having an radial width greater than about 10 microns; a base region adjoining a major surface at the peripheral portion of the body and comprising first and second impurity portions, first impurity portion adjoining said major surface and having an impurity concentration of boron of at least I X 10' atoms per cubic centimeter at said major surface and steep impurity concentration gradient to provide good ohmic and thermal contact properties, and a second contiguous impurity portion in internal portions of the body between emitter and collector regions, and having a lower impurity concentration than the first impurity portion of at least one member of the group consisting of aluminum and gallium and a shallower impurity concentration gradient than the first impurity portion; and an emitter region of N-type impurity concentration adjoining the same major surface as the base region at at least the internal portion of the body and extending into the body to adjoin the second impurity portion of the base region and form a PN junction therewith.
2. An NPN transistor as set forth in claim 1 wherein the impurity concentration of the second impurity portion of the base region is gallium.
3. An NPN transistor as set forth in claim 1 wherein the major surface that the base and emitter regions adjoin is planar in shape.
4. An NPN transistor as set forth in claim 1 wherein the resistivity of the semiconductor body is greater than
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US2829999 *||Mar 30, 1956||Apr 8, 1958||Hughes Aircraft Co||Fused junction silicon semiconductor device|
|US3088888 *||Mar 31, 1959||May 7, 1963||Ibm||Methods of etching a semiconductor device|
|US3186879 *||Aug 28, 1961||Jun 1, 1965||Philco Corp||Semiconductor devices utilizing cadmium alloy regions|
|US3322581 *||Oct 24, 1965||May 30, 1967||Texas Instruments Inc||Fabrication of a metal base transistor|
|US3487276 *||Nov 15, 1966||Dec 30, 1969||Westinghouse Electric Corp||Thyristor having improved operating characteristics at high temperature|
|US3615932 *||Jul 16, 1969||Oct 26, 1971||Hitachi Ltd||Method of fabricating a semiconductor integrated circuit device|
|US3697827 *||Feb 9, 1971||Oct 10, 1972||Unitrode Corp||Structure and formation of semiconductors with transverse conductivity gradients|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US3872494 *||Feb 8, 1974||Mar 18, 1975||Westinghouse Electric Corp||Field-contoured high speed, high voltage transistor|
|US4001864 *||Jan 30, 1976||Jan 4, 1977||Gibbons James F||Semiconductor p-n junction solar cell and method of manufacture|
|US4402001 *||Jan 12, 1978||Aug 30, 1983||Hitachi, Ltd.||Semiconductor element capable of withstanding high voltage|
|US5274265 *||Apr 3, 1992||Dec 28, 1993||Rohm Co., Ltd.||Bipolar transistor with a particular electrode structure|
|US5420458 *||Sep 21, 1994||May 30, 1995||Rohm Co., Ltd.||Semiconductor device and method of manufacture thereof|
|US6620738 *||Jan 18, 2000||Sep 16, 2003||Matsushita Electronics Corporation||Etchant and method for fabricating a semiconductor device using the same|
|US6682981||Feb 5, 2001||Jan 27, 2004||Elm Technology Corporation||Stress controlled dielectric integrated circuit fabrication|
|US6713327||Feb 5, 2001||Mar 30, 2004||Elm Technology Corporation||Stress controlled dielectric integrated circuit fabrication|
|US6765279||Feb 5, 2001||Jul 20, 2004||Elm Technology Corporation||Membrane 3D IC fabrication|
|US7138295||Dec 18, 2003||Nov 21, 2006||Elm Technology Corporation||Method of information processing using three dimensional integrated circuits|
|US7176545||Jan 27, 2004||Feb 13, 2007||Elm Technology Corporation||Apparatus and methods for maskless pattern generation|
|US7193239||Jul 3, 2003||Mar 20, 2007||Elm Technology Corporation||Three dimensional structure integrated circuit|
|US7223696||Jan 27, 2004||May 29, 2007||Elm Technology Corporation||Methods for maskless lithography|
|US7242012||Mar 7, 2003||Jul 10, 2007||Elm Technology Corporation||Lithography device for semiconductor circuit pattern generator|
|US7302982||Nov 26, 2003||Dec 4, 2007||Avery Dennison Corporation||Label applicator and system|
|US7307020||Dec 18, 2003||Dec 11, 2007||Elm Technology Corporation||Membrane 3D IC fabrication|
|US7385835||Dec 18, 2003||Jun 10, 2008||Elm Technology Corporation||Membrane 3D IC fabrication|
|US7402897||Aug 8, 2003||Jul 22, 2008||Elm Technology Corporation||Vertical system integration|
|US7474004||Dec 18, 2003||Jan 6, 2009||Elm Technology Corporation||Three dimensional structure memory|
|US7479694||Dec 19, 2003||Jan 20, 2009||Elm Technology Corporation||Membrane 3D IC fabrication|
|US7485571||Sep 19, 2003||Feb 3, 2009||Elm Technology Corporation||Method of making an integrated circuit|
|US7504732||Aug 19, 2002||Mar 17, 2009||Elm Technology Corporation||Three dimensional structure memory|
|US7550805||Jun 11, 2003||Jun 23, 2009||Elm Technology Corporation||Stress-controlled dielectric integrated circuit|
|US7615837||Jan 24, 2005||Nov 10, 2009||Taiwan Semiconductor Manufacturing Company||Lithography device for semiconductor circuit pattern generation|
|US7670893||Nov 3, 2003||Mar 2, 2010||Taiwan Semiconductor Manufacturing Co., Ltd.||Membrane IC fabrication|
|US7705466||Sep 26, 2003||Apr 27, 2010||Elm Technology Corporation||Three dimensional multi layer memory and control logic integrated circuit structure|
|US7763948||Oct 22, 2004||Jul 27, 2010||Taiwan Semiconductor Manufacturing Co., Ltd.||Flexible and elastic dielectric integrated circuit|
|US7820469||Jun 11, 2003||Oct 26, 2010||Taiwan Semiconductor Manufacturing Co., Ltd.||Stress-controlled dielectric integrated circuit|
|US7911012||Jan 18, 2008||Mar 22, 2011||Taiwan Semiconductor Manufacturing Co., Ltd.||Flexible and elastic dielectric integrated circuit|
|US8035233||Mar 3, 2003||Oct 11, 2011||Elm Technology Corporation||Adjacent substantially flexible substrates having integrated circuits that are bonded together by non-polymeric layer|
|US8080442||Jun 21, 2008||Dec 20, 2011||Elm Technology Corporation||Vertical system integration|
|US8269327||Jun 21, 2008||Sep 18, 2012||Glenn J Leedy||Vertical system integration|
|US8288206||Jul 4, 2009||Oct 16, 2012||Elm Technology Corp||Three dimensional structure memory|
|US8318538||Mar 17, 2009||Nov 27, 2012||Elm Technology Corp.||Three dimensional structure memory|
|US8410617||Jul 4, 2009||Apr 2, 2013||Elm Technology||Three dimensional structure memory|
|US8587102||May 9, 2008||Nov 19, 2013||Glenn J Leedy||Vertical system integration|
|US8629542||Mar 17, 2009||Jan 14, 2014||Glenn J. Leedy||Three dimensional structure memory|
|US8791581||Oct 23, 2013||Jul 29, 2014||Glenn J Leedy||Three dimensional structure memory|
|US8796862||Aug 9, 2013||Aug 5, 2014||Glenn J Leedy||Three dimensional memory structure|
|US8824159||Mar 31, 2009||Sep 2, 2014||Glenn J. Leedy||Three dimensional structure memory|
|US8841778||Aug 9, 2013||Sep 23, 2014||Glenn J Leedy||Three dimensional memory structure|
|US8907499||Jan 4, 2013||Dec 9, 2014||Glenn J Leedy||Three dimensional structure memory|
|US8928119||Mar 17, 2009||Jan 6, 2015||Glenn J. Leedy||Three dimensional structure memory|
|US8933570||Mar 17, 2009||Jan 13, 2015||Elm Technology Corp.||Three dimensional structure memory|
|US9087556||Aug 12, 2014||Jul 21, 2015||Glenn J Leedy||Three dimension structure memory|
|US9401183||Mar 17, 2009||Jul 26, 2016||Glenn J. Leedy||Stacked integrated memory device|
|US20040077168 *||Oct 16, 2003||Apr 22, 2004||Hidetoshi Ishida||Etchant and method for fabricating a semiconductor device using the same|
|EP0641485A1 *||Apr 2, 1993||Mar 8, 1995||LEEDY, Glenn J.||Membrane dielectric isolation ic fabrication|
|U.S. Classification||257/578, 257/619, 148/DIG.400, 148/DIG.850, 148/DIG.151, 257/586, 148/DIG.135, 257/621, 148/DIG.510, 148/DIG.157, 148/DIG.121|
|International Classification||H01L21/00, H01L29/73, H01L29/00, H01L21/331|
|Cooperative Classification||H01L21/00, Y10S148/157, Y10S148/051, Y10S148/151, Y10S148/121, H01L29/00, Y10S148/085, Y10S148/04, Y10S148/135, H01L29/73|
|European Classification||H01L29/73, H01L21/00, H01L29/00|