US 3781529 A
Description (OCR text may contain errors)
tent 1 Abramson et al.
[ DIGITAL TIMING SYSTEM  Inventors: Paul B. Abramson, 3042 Mountain Shadow Dr., Lakewood, Colo. 80215; Robert G. McConnell, 5851 S. Sherman Way, Littleton, Colo. 80121  Filed: May 25, 1972  Appl. No.: 256,808
 US. Cl...... 235/92 GA, 235/92 T, 340/347 DD  Int. Cl G04! 9/00, G06m 3/06  Field of Search 235/92 T, 92 GA;
 References Cited UNITED STATES PATENTS 3,508,034 4/1970 Toyama et al. 235/92 GA 3,368,028 2/1968 Windels et al. 178/17.5 3,594,643 7/1971 Hunt 235/92 T Primary ExaminerThomas A. Robinson Attorney-Reilly & Lewis START CLOCK FINISH FINISH FINISI;
MEMORY LANE I LANE 2 LANE 4 LANE 3 LANE 5 CIRCULATE STOP PRINT CLOCK PRINT PRINT AND CIRCULA COUNTER .001 SEC TOIMIN FINISH LANE 6 CIRCULATE SENSOR SHIFT REGISTER DECODER PRINTER Dec. 25, 1973 [5 7] ABSTRACT In a digital timing system for simultaneously timing a plurality of events such as swimming races there is provided a signal generator for producing a plurality of distinct binary coded signals in a parallel form representing elapsed time data, each distinct binary coded signal representing a different time digit. Storage apparatus responsive to the end of each event is operative to store the coded signals in a serial form, one event at a time, and upon command present the time data signals in a parallel form one event at a time. Print-out apparatus including a decoder which monitors the parallel outputs from the storage apparatus and a printer responsive to said parallel outputs prints out the time data for each event preferably in a permanent, visible form. A command circuit is operative to cause the storage apparatus to transfer the coded signals into storage in a serial form one event at a time, and recirculates the signals back into the storage apparatus. Event identification, place,-and split times may be printed out upon actuation of the command circuit.
20 Claims, 4 Drawing Figures COUNTER IO MIN FIRST LANE FINISH I7 17 I I7 FINISH FINISH FINISH FINISH 7 IO LANE B MEMORY LANE 9 LANE 7 LANEIO PRINT COMMAND ENABLE 1 DIGITAL TIMING SYSTEM 'Thisinvention relates, generally to timing systems and more particularly to anovel and improved digital timing system for simultaneously timing a plurality of events.
'In competitive sporting activites such as swim meets, track .and field races, and horse races there is a need for accurate and reliable .timing of each event with a readily usable read-out and particularly a visible permanent print-out. Timing systems have heretofore been provided for such purposes but they have not been entirely satisfactory from the standpoint of cost of manufacture, accuracy and the form of read-out of the elapsed "time of each event. Moreover, many timing systems presently available do not afford sufficient information for each event. Accordingly, it is a general object of *.this invention to provide a novel and improved timing system for racing events and the like having a number of participants.
Another object of this invention is to provide an improved digital timing system which eliminates a substantial :amount of the circuitry heretofore utilized to simultaneously time a number of events and record the elapsed time at least to one one-thousandth of a second.
Yet a further object of this invention is to provide a novel timing system capable of providing immediate timing results for each event of a multi-event' race in a Another object of this invention is to provide a novel timing system using digital circuits in which the timing datalis received in a parallel form, stored serially one event at a time to reduce the apparatus required for multiple events.
Still a further object of this invention is to provide a novel digital timing system in which split times are available for each lap and the place for each event is readily available.
in accordance with the present invention in a preferred form shown is provided in a single clock, generating timing pulses of a selected frequency and a single read-out device in the form of a line printer capable of providing a print-out in a permanent, visible form. The output of the clock circuit is gated on by the actuation of astart device when the race begins. A counting system made up of decade counters is coupled to the output of the clock and is operative to provide a plurality of distinct binary coded digital signals representing elapsed time data, each distinct binary coded digital signal representing one of a plurality of time digits ranging preferably from ten minutes to a thousandth of a second. The time data binary coded signals aresimultaneously applied in parallel to a memory for each event. A finish pulse is generated in a finish circuit when each event is ended. At the instant the event is ended, the time data signals are transferred in a parallel form into the memoryfor an associated event. Once all of the events have been terminated, the time data in a signal form is serially shifted out of the memories, one event at a time, into an access storage device by circulate pulses. When the time data signals for each event are in the access storage device, the time .data binary coded signals are decoded and the printerprints out the elapsed time for the associated event in arabic numbers in a permanent, visible form and the data is also circulated back into the associated memories for subsequent printout so that upon each command the source time data may be again printed out. A first event finish circuit is responsive to the first event to finish and couples the most significant time digit signal directly to the decoder for printing. Event identification, place and time is printed out for all events.
Other objects, advantages and capabilities of the present invention will become more apparent as the description proceeds taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a general block diagram of a digital timing system in accordance with the present invention.
FIG. 2 is a more detailed electric circuit diagram of the digital timing system of FIG. 1.
FIG. 3 is a more detailed electric circuit diagram of the decoder circuit and portions of circuitry for the printer; and
FIG. 4 is a detailed electric circuit diagram of the place circuit.
The timing system described herein is suitable for timing a plurality of events which usually take place simultaneously in separate lanes and may be used to time any number of different competitive activities such as swimming, track and field, horse races and the like. The embodiment described herein for the purposes of illustrating the present invention is capable of timing the events taking place in ten swimming lanes but it is understood that this is for illustrative purposes only and that the present invention is in no way restricted as to the number of lanes or events or the type of competitive activity being timed. The term event as used herein is generic for each activity timed and lane is more specific to a physical location and has specific reference to a swimming lane for which the preferred embodiment shown and described herein is particularly suitable.
The apparatus and operation of a digital timing system in accordance with the present invention will first be described generally with reference to the block diagram of FIG. 1. The digital timing system shown in FIG. 1 comprises a single start circuit represented in two parts as a start sense circuit 11 and a start clock circuit 12 operatively coupled together and having an output coupled to the input of a counter system represented as counter circuit 13 and counter circuit 14, the output of the counter system being coupled to the input of a first lane finish circuit 15. A reset circuit 16 is provided to reset the counter circuits 13 and 14 and first lane finish circuit 15 and other logic circuits described in more detail hereinafter. The end of each race is signaled by having the contestant actuate contacts in a finish circuit 17 for each event, each finish circuit 17 having an output coupled to the input of the first lane finish circuit 15. The first lane finish circuit 15 is responsive to each. finish circuit to couple the signals representing the ten minute time digit to the decoder 26 once an event finishes.
A clock in the start clock circuit 12 is gated on by a start pulse or signal received from the start sense circuit 11. The clock time is converted in the counter system to distinct binary coded digital signals in a parallel form representing elapsed time data, each distinct signal representing a time digit, the signals being simultaneously applied to storage apparatus including a separate memory 18 for each event lane. The time data binary coded signals are accepted into a memory 18 when a finish pulse is generated from an associated finish circuit 17. At the instant the finish pulse is generated the elapsed time data binary coded signals are transferred to the memory 18 associated with the respective event. Once all of the events have ended and the time data has been stored in the memories 18, the time data binary coded for each event may be shifted out serially successively, one event at a time, into a printer access storage device specifically in the form ofa serial in, parallel out, shift register apparatus 19. The time data binary coded signals in the memories 18 are shifted into shift register apparatus 19 by circulate pulses provided'by a print and circulate command circuit 21 comprised of a print command 24, circulate sensor circuit 23 and a print circuit 22, which print circuit 21 is operable to shift the time'data signals back into the memories 18 for reaccess.
After the time data binary coded signals for an event have been shifted into the shift register circuit 19, a decoder 26 is enabled by an enable signal from the print command circuit 24 causing the printer 25 to print the time data for each event.
The time data binary coded signals for each event are received by the printer shift register 19 and first lane finish 15 via the decoder in a parallel form and are decoded and printed out in a permanent, visible form on a sheet of paper or the like when a print pulse is applied to the line printer 25 from the decoder. A place circuit 27 is coupled to the decoder and receives signals from the finish circuits 17 to give chronological order of finish of each event or lane. A lane input into the decoder 26 from the circulate sensor 23 is operative to associate the time data signals with a particular lane.
START CIRCUITS The start sense circuit 11 indicates that the race has begun. The start sense circuit which is a single unit for a plurality of events includes a pistol or the like with an electric signal device having a pair of contacts operatively associated therewith which is represented in FIG. 2by a battery 31 and a normally-open, momentarily closed, electric switch 32 arranged so a start signal or pulse is generated upon the closure of the switch 32, which switch automatically opens after closure. A single start clock circuit 12 is coupled to the start sense circuit 11 comprising a conventional crystal oscillator 33 having its output gated via a NAND gate 34 to the input of the counter system comprised of circuits 13 and 14. The D flip-flop 35 latches in one position to gate the NAND gate 34 to couple the output of the oscillator 33 to the input of the counter system.
COUNTER SYSTEM The counter system comprises counter circuits 13 made up of six identical four-bit, divide-by-ten, decade countersdesignated 37, 38, 39, 40, 41 and 42. Proceding from left to right the counters are identified 0.001 seconds, 0.01 seconds, 0.1 seconds, 1 second, seconds and one minute to correspond with the particular time digit output associated with each and are coupled in series so that an output of one is connected to the input of the other proceeding from left to right. Between the 10 second counter 41 and one minute counter 42 is a divide-by-six counter 43 for establishing minute timing. A one shot 45 is coupled from the output of the divide-by-six counter 43 and to the input of the 10 second counter 41 to reset the 10 second counter on the 60th second. In the counter system illustrated, the oscillator 33 has an output frequency of 10 1-12 to provide the counting range above described. It is understood that the l0 Hz is the frequency shown for the counter system shown but that the frequency may be increased as for example to l0H2 or l0 Hz and divided down by counters to provide greater timing accuracy. The ten minute counter circuit 14 is comprised of a single divide-by-ten decade counter designated 44 which has an input coupled to the output of the one minute counter 42. Each of the counters 37 through 44, inclusive, has a reset input connected to the reset circuit 16 described more fully hereinafter. 1
Each of decade counters 37 through 42 inclusive, has four outputs providing a distinct binary representation or binary coded digital signal for a distinct time digit. The time digits being designated 7, 6, 5, 4, 3, and 2, respectively for the range of one thousandth second to one minute. The ten minute counter 44 is coupled via a latch 46 in the first lane finish circuit 15 which latches when any participant wins or is first in time to activate the associated finish circuit, the four line digital output of the latch designated l being coupled to the input of the decoder circuit 26 (See 'FIG. 3) until reset. Counters 37 through 42 and 44 are arranged to count continuously until reset.
The reset circuit 16 comprises a battery 47 connected in series with a double-pole, double-thrc momentary switch 48. When switch 48 is closed, a CL terminal of the switch goes from low to high and CL terminal of the switch goes from high to low.
TIME DATA STORAGE The memory 18 for each event or lane comprises a group of three, eight-bit, parallel in, serial out shift registers designated 51, 52 and 53. Each group of three shift registers for each lane are connected in series with one another and in series with similar groups of three, eight-bit, parallelin, serial out shift registers, for each of the other nine lanes represented in FIG. 2 by a single block at 54 to form a chain.
The time data binary coded signals provided by parallel counter outputs designated 7, 6, 5, 4, 3, and 2 is entered into the group of three registers for each event upon command by the finish circuit 17 for each event.
The shift register apparatus or printer access storage 19 comprises a group of three, eight-bit serial in, parallel out shift registers 55, 56 and 57 connected in series in a chain and in series with the output and input of the chain of parallel in, serial out, shift registers 51 through 54 above described.
FINISH CIRCUIT The finish circuit 17 for each event includes a finish sensing device at the finish line of each event which indicates that the event has ended or a lap has been concluded. The finish sensing device may take a variety of conventional forms such as a contact platewhich activates a pair of electric contacts and is herein represented schematically as a DC battery 58 and a normally-open-momentary switch 59 providing a pair'of contacts connected in series with the battery so that a separate finish signal is provided for each event uponthe closure of a switch 59 associated with the event whichmay occur when the swimmer engages a contact plate at the end of a lap or the race or alternatively for example activates a photoelectric sensing device or the like capable of generating a finish signal upon a completion of the event or a lap of the event. The finish signal for each event is coupled to the input of a D flipflop 61 having one output designated Q and a second output of the D flip-flop 61 is connected to the input of a oneshot 62, the one shot 62 having one output designated 0* and another output designated Q*, the output 0* being coupled to an input of each of the shift registers 51, 52, and 53 of each lane memory. When the D flip-flop 61 goes high, it triggers the one shot 62, which provides a single pulse transferring the count or time data binary coded signals at that instant for a particular event or lane into shift registers 51, 52 and 53 associated with that event or lane. For each lane or event 2 through 10, the accumulated time count is transferred in a like manner into the three shift registers for an associated event represented at 54. When each event is finished, there is stored in each group of three shift registers the time data of six time digits designated (2 through 7) for the associated event.
In each finish circuit 17 for each event there is provided a delayed reset circuit for the D flip-flop 61 comprised of a timer 66 connected to an input of the D flipflop 61. The output signal via switch 59 is connected to input of timer 66. A reset of the D flip-flop 61 by the timer allows the time data binary coded signals transferred into the shift registers 51, 52 and 53 to be updated by the reclosure of switch 59 which may recur on each lap of the event. This'allows the printing out of split times if desired. Timer 56 preferably is two one shots connected in series, the first one shot providing a command signal. The principal reason for the timer 66 is to avoid a time count in the event of a false multiple closure. This may occur in a swimming race if the swimmer hits the finish contacts first with the hand and then with the foot upon turnaround.
FIRST LANE FINISH CIRUCIT The 6 output of the D flip-flop 61 for each finish circuit 17 is also connected to each of the inputs of the first lane finish circuit comprised of a ten input NAND gate 63, having an output coupled to the input of a one shot 64, which in turn has an output coupled to one input of a two input NAND gate 65. The output of the NAND gate 65 is coupled to an input of the latch 46. The purpose of the first lane finish circuit is to lock the time data signals for the highest time digit into the decoder for all events once an event is finished without having to provide additional memories therefore. At any time one of the inputs to the ten input NAND gate 63 goes low, the. input of the one shot 64 goes high triggering the two input NAND gate 65 which gives a single pulse to transfer the time data signals from the ten minute counter 44 to the output of the latch 46, where it is applied as an input to the decoder of FIG. 3 avoiding the necessity of running the highest digit through the memories. The time data signals remain at the output of the latch until there is a reset pulse applied from the reset terminal CL to the two input NAND gate 65. The reset pulse CT is also coupled to each of the counters 37 through 44, inclusive, to reset the accumulated count in each counter of the counter system.
PRINT AND CIRCULATE COMMAND CIRCUIT The accumulated count time data signalsin the memories 18 are shifted out therefrom into the shift register circuit 19 by actuating the print circuit 22 including a print-out, momentary switch 67 with a pair of contacts connected in series with a battery 68 to provided a printout signal which will set a D flip-flop 69. The output of the D flip-flop 69 is coupled to an input of a three input AND gate 71 which in turn has an output designated circulate coupled to an input of each shift register 51, 52 and 53 and to similar inputs of memories for lanes 2 through 10 designated 54 and via an inverter 70 to an input of each shift register 55, 56 and 57.
Another of the inputs of the AND gate 71 has a clock pulse applied thereto from the start clock 12. The third input to AND gate 71 designated hold comes from the print command circuit 24 and goes high when exactly 24 pulses or one events information has been circulated into the associated memory. Twenty-four pulses are required to circulate all of the bits of data six distinct input groups (2-7) and four lines per group.
When the print-out switch 67 is closed there is a sequence of pulses from the clock 12 coupled via the AND gate 71 sent simultaneously to each shift register 51, 52 and 53 and the shift registers in memories 54 and via the inverter 70 to the shift register 55, 56 and 57 which shift the time data binary coded signals in the chain for a given number of pulses into the circulate sensor circuit 23. The number of pulses is determined by the circulate sensor circuit 23 which includes a divide-by-six circuit 75 having inputs connected to the output of the inverter 70 so that an inverted circulate pulse is applied thereto. The output of the divide-by-six counter 75, identified as place, is applied to the place circuit of FIG. 4 described more fully hereinafter.
At the end of the twenty fourth pulse, which means that the time data signals from one event have been circulated into the shift registers 55, 56 and 57, a pulse is generated through a one shot 74 having an input coupled to the output of the divide-by-twenty-four counter 73, the one shot 74 having an output coupled to the input of a D flip-flop 76 (FIG. 3) in the print command circuit 24. The print command circuit 24 applies a hold signal to an input of the AND gate 71 of the print circuit 22 to momentarily stop the data from circulating until the time data in the shift registers 55, 56 and 57 is decoded and printed. At this time the hold" signal is released from the print command circuit 24. The output of a divide-by-eleven circuit 60 has a binary coded digital output designated lane representing the lane or event data in registers 55, 56 and 57 at a particular instant. An output of the divide-by-eleven circuit 60 actuates a one shot 50 on the eleventh count providing a stop print pulse which resets the D flipflop 69. This disables the print circuit 22 when all ten events or lanes have been printed and circulated back into the associated memories 18 for each event. The divide-by-eleven covers ten events and the eleventh returns data back to respective memories for each event. The divide-by eleven counter 60 and divide-by-twenty four counter 73 also have inputs coupled to the output of a one shot 72 which insures a reset to zero for counters 60 and 73.
DECODER CIRCUIT AND LINE PRINTER Referring again to FIGS. 1 through 3, the readout apparatus used herein is a line printer 25 which preferably is a Miniature Line Printer Type LP manufactured by Tokyo Electric Ltd. Tokyo,-Japan. It is understood that other read-out apparatus such as a visual sign-type display may be used. This line printer 25 herein described and used in the embodiment herein comprises a print drum driven by an induction motor, print hammers actuated by solenoids, a magnetic pickup to detect the timing signals of printing, and a ribbon and paper feed mechanism actuated by solenoids. All of the print characters including numbers, letters and special symbols are engraved around the circumference of the print drum that is rotating continuously in front of a series of hammers. Each hammer'corresponds to a print position on the line. To print a specific character in a given column on the line, the appropriate hammer is actuated by an input printing pulse just as the character passes the hammer. Printing on all the columns of a line is made during one rotation of the drum. The print-out paper and ribbon are fed by a paper feed input pulse after completing a line-print. The time data at the parallel outputs of the shift registers 55, 56 and 57 is designated 7', 6', 5, 4, 3, and 2' for time digits from a thousandth of a second to minutes. These outputs are applied to half (four) of the inputs of six, four-bit magnitude comparators designated 81, 82, 83, 84, 85 and 86 shown in FIG. 3 which comprises a part of the decoder circuit 26 and function to decode the time data signals. The line output pulse from the line printer 25, representing the angular position of the print drum is applied to the input of a divide-by-two counter 78 in thedecoder circuit which in turn is applied to a decade counter 79 having a four line output which corresponds to the position of the printer drum at any one time. The four line output of the counter 79 designated B is applied to' four inputs of each of the four bit, magnitude comparators 81, 82, 83, 84,85, and 86, each comparator'corresponding to a time digit so that the count from the line output pulse is present at all of the comparators in a binary form. The output B of the decade counter 79 is also applied to comparators 87, 88 and 89 representing lane, place and digit one (ten minute), respectively. In the comparators, the binary representation of the time digits corresponding to the time for each event in a signal form is compared with the binary coded line output pulse signal at the output of decade counter 79 representing drum printer position. When the magnitude of the output of decade counter 79 equals a magnitude corresponding to any of each time digit output from shift registers 55, 56 and 57, two outputs are provided from each comparator. Each of the comparators 81 through 89 inclusive, set an associated AND gate 91 when both inputs to the AND gate 91 are high. The output of each AND gate 91 is applied to a solenoid drive circuit 92 which actuates a solenoid coil 93 in the printer to imprint on the paper the arabic number in the drum opposite the print hammer associated with the solenoid at a given instant which is exactly the same number of the binary coded number representation from the shift register 19 to be printed. A typical example of the time print-out for the above described apparatus is as follows:
Lane Time 6 l l0:2l.00l 7 2 l0:2l.003 8 1() l2:l5.222 9 9 1210110 0 8 1200.102
Once the type D flip-flop 76 in the print command circuit 24 provides an input to a two input NAND gate 94 in the decoder circuit 26, the decoder circuit 26 is ready to decode the binary coded time data signals from the shift registers 55, 56 and 57 and the lane, place and digit one ten minute time data signal. Before decoding can actually begin however, a synchronous pulse must be sent from the print to a one shot 95 in the decodercircuit 26. The synchronous pulse signals the beginning of a revolution of the drum in the printer.
. The synchronous pulse is also applied to an input of the divide-by-two counter 78 and decade counter 79. The presence of signals at both the inputs of the two input NAND gate 94, triggers a divide-by-two circuit 96, having an output Ii coupled to the input of a one shot 97. The first synchronous pulse (begin revolution of drum) sets and R output of the divide-by-two circuit 96 high which is simultaneously applied to each of the magnitude comparators 81 through 89. This signal enables each of the comparators and allows each of them to compare the time data binary coded signals from the shift registers 55, 56 and 57 with the binary coded signal B from the decade counter 79. The second synchronous pulse from the printer (end of revolution of drum) sets the R output of the divide-by-two circuit 96 low and disables the comparators and at the same time the R output of the divide-by-two 96 triggers the one shot 97. The pulse from the one shot 97 is applied to an input and the D flip-flop 76; This will reset the D flip-flop 76 and remove the signal from the D flip-flop 76 to the two input NAND gate 94 cannot couple the synchronous pulse to the divide-by-two circuit 96 and the comparators 81 through 89 remain disables until the D flip-flop 76 is again triggered. Resetting of the D flip-flop 76 also removes the hold" signal at its other output and allows the clock pulse from the clock to circulate in another block of time data signals for one event and this event time data in signal form is circulated into the serial in parallel out shift registers 55, 56 and 57. When D'flip-flop 76 receives another pulse from one shot 74, it applies an input signal to the two input NAND gate 94 and the decoder circuit 26 is then enabled and as previously explained the decoding and printing sequence is repeated.
PLACE CIRCUIT The function of the place circuit 27 is to assign a number to the event or lane to indicate its place in chronological order. is first, second, third etc. Referring now to FIG. 4, the place circuit 27 is made up of a ten input NAND gate 101 having an output coupled to the input of an inverter 102 which in turn has an output coupled to the input of a decade counterl03. The decade counter 103 has a binary coded output signal designated C corresponding to the count from the counter which is coupled to each input of ten,'four-bit, parallel in, serial out, shift registers designated 105, 106, 107, 108, 109, 110, 112, 113 and 1,14. The shift registers through 114 inclusive, are connected in series with a four-bit, series in, parallel out shift register 1 15.
When any given event or lane finishes, a low going pulse is coupled from the output 6* of the associated lane finishes. The binary coded digital output signal of the decade counter 103 designated C which corresponds to the place the given lane has finished is applied simultaneously to each of the ten, four-bit parallel in, serial out shift registers.
The binary coded digital signal C at the input of each parallel in, serial out shift registers 105-114 inclusive, is transferred into a given shift register when the Q* input for that lane goes high. Since the Q* is the complement of 6*, the count out of thedecade counter 103 is advanced one count and an input is simultaneously entered into the respective shift register for that lane at Q*. When all events or lanes have finished the race, there will be binary coded number stored in each parallel in, serial out shift register 105 through 1114 inclusive corresponding to the place that the respective lane has finished. This place data is sequenced out one event or lane at a time, into the serial in, parallel out shift register 115 with a place circulate pulse from the divide-by-six counter 75 which is applied to a circulate input of each shift register 105 through 114.
The four-bit binary coded place signal designated D from the serial in, parallel out shift register 115 is applied to the decoder circuit for printing on the printout sheet with the time data. In this way the print-out sheet will include a numerical identification of the event i.e. lane, the time for each event, and the order of finish or place for that event. In order to obtain a split time the print-out switch 67 is closed immediately after the swimmer finishes a lap and hits the finish switch.
' SUMMARY OF OPERATION binary coded signals from the counter system with the exception of the ten minute digit are then entered into the memories 18. Once all of the events have terminated the time data binary coded signals are serially shifted out of the memories 18 one event at a time into shift register or access storage apparatus 19 by a circulate command pulse produced by the closure of printout switch 67. The shift register apparatus 19 outputs the time data signals for each time digit in a parallel form to of decoder 26 and printer 25 which then prints out the event identification, place and time. The printout switch 67 may be depressed at any time during the race to get a print-out time for each event. This is important for obtaining a split time in swimming races and the like. With the recirculation of the time data back into memories 18 the same time data results may be printed out any number of times by successively depressing printout switch 67. The place circuit 27 is responsive to the finish circuits 17 of each event to provide a chronological order The finish. The lane input 6 into the decoder is operative to identify each lane. A closure of the reset switch 48 uncouples the clock from the counter system and resets the counters 37 through 44 to zero and they remain in that condition until the start switch 32 is again closed and the timing-sequence begins again.
By way of illustration only and not by way of limitation, there is listed below device which have been found to be suitable for illustrated system:
National Semiconductor Company 4. Serial in, parallel out shift DM 8370 registers (-57) 5. Magnitude comparators (SI-'87) From the foregoing description it is apparent that the present invention minimizes the electric components needed thereby increasing the reliability and further makes efficient use of the electric components. The electric components are minimized by eliminating the need for a separate clock circuit for each event and eliminating theneed for separate lines from each lane or event storage device to the print out access storage. For example when timing ten events, normally there would be two hundred and forty lines needed to transfer the time data associated with a six-digit timing signal for each event. The system of the present invention requires only two lines. Moreover the present invention eliminates the need for separate print-out access storage for each event by sharing a common access storage device and further eliminates the need for multiplexing techniques by putting the time data binary coded signals with a selected number of circulate pulses. No separate display unit for each event is required because a single printer utilized is a common display unit for all events.
Although the present invention has been described with a certain degree of particularity, it is understood that the present disclosure has been made by way of example and that changes in details of structure may be made without departing from the spirit thereof.
What is claimed is: 1. In a digital timing system for individually timing each of a plurality of events, the combination comprismg:
signal generator means responsive to the start of the events providing a plurality of distinct coded signals in a parallel form representing elapsed time data, each distinct coded signal representing a time digit; storage means responsive to the end of each event operative to store the time data coded signals from said signal generator means in a serial form, one event at a time, and present the time data as coded signals in a parallel form, one event at a time;
read-out means monitoring the coded signals from the storage means in a parallel form for displaying the time data for the events whereby upon command the time data coded signals are transferred from the storage means to the read-out means in a parallel form one event at a time.
2. In a digital timing system as set forth in claim 1 further including command means operative to transfer the time data coded signals from the storage means to the readout means in a parallel form one event ata time and to recirculate the time data coded signals back into storage in said storagemeans in the original serial form after display. 7
3. In a digital timing system asset forth in claim 1 wherein said signal generator means includes:
a clock for generating timing pulses of a selected frequency;
start sense means for producing a start signal and;
a'counting system responsive to said start signal for counting the timing pulses.
4. In a digital timing system as set forth in claim 3 wherein said clock includes anoscillator having an output frequency of at least 1000 Hz, said counting system includes seven decade counters connected in series with one another in a chain, each said counter having a four-bit output for each time digit, the least significant time digit being thousandths of a second and the largest time digit being ten minutes.
1 5. In a digital timing system as set forth in claim 4 wherein said time digits are, thousandths of a second, hundredths of a second, tenths of a second, seconds, tens of seconds, minutes and tens of minutes.
6. In a digital timing system as set forth in claim 1 wherein said storage means includes,
a memory for each event, said memories being connected in series with on another in a chain and,
a read-out access storage coupled in series with an output and an input of said chain of memories for receiving time data coded signals from said chain of memories in a serial form and returning the time data coded signals to the chain of memories in a serial form, said read-out access storage presenting the time data coded signals in a parallel form.
7. In a digital'timing system as set forth in claim 6 wherein each said memory is parallel in, serial out shift register apparatus.
8. In a digital timing system as set forth in claim 6 wherein said read-out access storage is serial in, parallel out shift register apparatus.
9. In a digital timing system as set forth in claim 1 fur- I ther including a first event finish circuit responsive to the finish of each event arranged to enter the coded signals of the most significant time digit into the read-out means for displaying each event after the first event finishes.
10. In a digital timing system as set forth in claim 1 wherein said read-out means includes:
a line printer having means to print out time numbers in a visible form, said printer producing a printer signal representing a position corresponding to a particular number at which a print-out will occur, and
a decoder having a comparator for each time digit,
each said comparator having input means to receive the parallel coded signals from the storage means whereby when the magnitude of the printer signal is the same as that from the storage means the printer prints out an associated number.
11. In a digital timing system as set forth in claim 1 wherein said command means includes:
print means for simultaneously applying a number of command pulses to the storage means corresponding to the total number of time data bits; and
means for stopping the application of the command pulses to the storage means until the time data coded signals in the storage means is decoded and printed; and means for disabling the print meanswhen all of the time data signals have been printed and circulated back into the storage means for each event.
12. In a digital timing system as set forth in claim 1 including a place circuit responsive to the finish of each event operative to cause said read-out means to indicate the chronological order of finish of each event in the time data read-out.
13. In a digital timing system asset forth in claim 1 including an event circuit responsive to a selected number of command pulses corresponding to the number of events operative to cause said read-out means to identify each event with a relation to a particular time.
14. In a digital timing system for individually timing each of a plurality of events, the combination comprismg:
signal generator means responsive to the start of the events providing a plurality of distinct binary coded signals in a parallel form representing elapsed time data, each distinct binary coded signal representing a time digit; v
a memory for each event, said memories being connected in series with one another in a chain;
finish sensing means responsive to the end of each event operative to enter the time data binary coded signals provided by said time generator means into an associated storage memory at the end of the associated event;
a printer access storage coupled to the input and output of said chain of memories for receiving binary coded signals from said memories in a serial form and returning the time data binary coded signals to the chain of memories in a serial form, said printing access storage presenting the time data binary coded signals in a parallel form;
print-out means monitoring binary coded signals in parallel form from the printer access storage for printing out the time data for each event upon command; and
command means operative to transfer the time data binary coded signals from the memories to the I printer access storage serially, one event at a time, and transfer the time data binary coded signals from the printer access storage to the print-out means in parallel, one event at a time, and to recir-- culate the time data binary coded signals from the memory for each event after print-out for reaccess.
15. In a digital timing system as set forth in claim 14 wherein said finish sensing means includes an electric power source and a pair of contacts connected to said power source, said contacts being actuated by the participant of an event whereby to generate a finish signal for that event and means responsive to said finish signal for enabling said memories to receive the time data binary coded signals from the signal generator means when the event finishes.
16. In a digital timing system as set forth in claim 15 including delay means operative to delay the application of said finish signal to said memories to avoid a false finish signal occuring within a preselected time interval after said pair of contacts are actuated.
17. In a digital timing system for individually timing each lane of a plurality of lanes in a swimming race the combination comprising:
printer access storage back into the associated a clock for generating timing pulses including an oscillator having an output frequency of lOOOl-lz; start sense means including a pair of contacts adapted to close when the race beings to generate a start signal;
a counting system responsive to said start signal including six decade counters connected in series in a chain, each said counter having a four-bit parallel output presenting a binary coded signal representing one of the time digits of thousandths of a second, hundredthsiof a second, tenths of a second, seconds, tens of seconds, minutes, and tens of minutes and a seventh decade counter coupled to an output of the minute counter having a four-line parallel output for producing a binary coded signal representing a ten minute time digit;
a first group of shift registers for each lane, each said group having eight-bit parallel inputs coupled to two associated four-bit outputs of said counters, said first group of shift registers for each lane being coupled in series in a chain of shift registers; finish sensing means including an electric power source and a pair of contacts connected thereto for each lane to provide a finish signal for each lane when the participant actuates the contacts, said finish signal being operative to provide an input signal to each group of shift registers in the chain to enter the binary coded signals from the counters into the associated group of shift registers;
a second group of shift registers connected in series in a chain and connected in series with said chain of first groups of shift registers to receive the time data binary coded signals therefrom in a serial form and recirculate said signals beack into the chain of shift registers, said second group of shift registers having a four-bit output corresponding with each of said six digits;
a print and circulate command circuit including a print circuit having an electric power source and a pair of contacts connected thereto to generate a printout signal upon the actuation of the contacts, a circulate sensor circuit including a first counter for providing a selected number of circulate pulses, a second counter providing a selected number of circulate pulses, a second counter providing a selected number of lane pulses, and a print command circuit to selectively apply said circulate pulses to said first group of shift registers and said second group of shift registers, said print command circuit providing a hold signal to stop the time data from circulating after the final circulate pulse, for the time data for one lane, said lane pulses recirculating the data back into said first group of shift registers and disabling the print circuit when all of the lanes have been printed and the time data binary coded signals have been circulated back;
a place circuit comprising a parallel in, serial out shift register for each lane connected in series in a chain and a four-bit serial in, parallel out shift register connected in series with said chain, a decade counter responsive to each of said finish circuits to provide a count for each finish, each said place circuit parallel in, serial out shift register responsive to a signal from the finish circuit, whereby when each lane finishes a binary coded number is stored in each place circuit parallel in, serial out shift register to transfer the data into the place circuit serial in, parallel out shift register;
a lane circuit coupled to said decoder and responsive to said lane pulses operative to cause the printer to identify each event with a particular time;
a line printer having print-out means to print numbers in a permanent visible form, said line printer having means for generating a line output pulse representing the position of the printer at any time and a synchronous pulse indicating the start position for the printer;
a decoder circuit including a comparator for each time digit and for said lane and place circuits, each comparator having a four-bit parallel in, input coupled to the output of each of the said group of three serial in, parallel out shift registers and from the lane circuit and place circuit.
18. In a digital system as set forth in claim 17 wherein each of said first group of shift registers are three parallel in, serial out devices.
19. In a digital timing system as set forth in claim 17 wherein said second group of shift registers are three serial in, parallel out shift register devices.
20. In a digital timing system as set forth in claim 17 wherein said first counter is a divide-by-twenty four device providing twenty-four circulate pulses and said second counter is a divide-by-six counter providing eleven lane pulses and said place circuit having ten parallel, in serial out shift registers.