|Publication number||US3781874 A|
|Publication date||Dec 25, 1973|
|Filing date||Apr 3, 1972|
|Priority date||Apr 3, 1972|
|Publication number||US 3781874 A, US 3781874A, US-A-3781874, US3781874 A, US3781874A|
|Original Assignee||Pertec Corp|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (1), Referenced by (17), Classifications (6), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
United States Patent [1 1 Jennings KEYBOARD ENTRY SYSTEM 7 Primary ExaminerJohn W. Caldwell Assistant ExaminerRobert J. Mooney Att0meyRobert l-l. Fraser et al.
ABSTRACT A keyboard entry system includes a keyboard, a read only memory (ROM) addressed by activation of a key on the keyboard and a digital timing circuit. The tim- Dec. 25, 1973 ing circuit includes a pair of flip flops which are sequenced through successive mutually exclusive states to control the output of encoded signals to an information receiving device in response to key activation. These sequenced states provide timing for three basic functions. First, the memory must be addressed for a sufficiently long period of time to permit dissipation of switch bounce so that possibly erroneous memory 10- cations will not be addressed at the time information stored in the ROM is transferred. Second, a relatively short strobe pulse is generated for transferring keyed information to the system; and third, the sequencing of the flip flops is blocked to permit control of subsequent repeating of the sequence. In addition, advantage is taken of commercially available ROM configurations by addressing the ROM in a manner effectively doubling the word length by halving the number of words. The blocking function is terminated when there is a new key activation or, in the event an automatic repeat key is depressed, at the conclusion of first and subsequent periods of continuous key depression. The first period is relatively long to prevent unwanted automatic repeat and the subsequent periods may be chosen to provide automatic repeat at either 10 or 20 cycles per second.
KEYBOARD ENTRY SYSTEM BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to keyboard entry systems more particularly to a keyboard entry system having a digital timing circuit controlling the transfer of keyed information to a data receiving device.
2. History of the Prior Art Key input systems have been used to provide encoded data for typewriters, key-to-tape systems, keyto-disk systems and other devices requiring the input of encoded information. Because switch bounce may cause an incorrect encoded signal to be generated, such circuits generally utilize a delay to generate a strobe signal several milliseconds after activation of a key. This strobe signal, which occurs after switch bounce has dissipated, causes the encoded keyed information to be transferred to the device utilizing the information. Further delays may be utilized to provide automatic repeat functions if a key remains continuously activated. However, as further timing and sequencing functions are added, such delay circuit timing arrangements become excessively complicated and expensive to manufacture.
SUMMARY OF THE INVENTION A key input system in accordance with the invention includes a keyboard, a read only memory and a digital timing circuit. The timing circuit includes a plurality of bistable elements such as flip flops providing in combination at least three mutually exclusive states. Control logic responsive to the keyboard sequences the flip flops throughout at least three of the mutually exclusive states, the flip flops remaining in each state for a controlled period of time. Control signals, including a data strobe signal, are generated by logic responsive to at least one of the mutually exclusive states. Multiple outputs from a frequency divider connected to a high frequency clock signal provide the necessary timing signals and outputs from the flip flops are connected to control the sequenced operations.
In a particular arrangement, advantage is taken of commercially available memory configurations by a two'step addressing technique. The timing circuit first causes a location in a first half of the memory to be read to produce a first half of the encoded data signal. The timing circuit then latches the output from the first half of the memory and causes a location in a second half of the memory to be addressed to obtain the second half of the encoded data signal. A strobe pulse is then generated to cause both halves of the encoded signal to be transferred to a device which is connected to receive the data. The timing circuit then allows this sequence to be repeated only when there is a new activation of a key or when an automatic repeat key is continuously activated and predetermined timing requirements are satisfied.
BRIEF DESCRIPTlON OF THE DRAWING A better understanding of the invention may be had from a consideration of the following detailed description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a partial block diagram and partial schematic diagram of a keyboard entry system in accordance withthe invention;
FIG. 2 is a timing diagram illustrating the relationship of various signals utilized by the keyboard entry system shown in FIG. 1; and
FIG. 3 is a timing diagram illustrating in greater detail the relationship of some of the signals illustrated in FIG. 2.
DETAILED DESCRIPTION As shown in FIG. 1, a keyboard entry system 10 in accordance with the invention includes a conventional keyboard 12, a read only memory 14 (ROM) and associated timing and control circuitry.
Keyboard logic circuits l6 operate in response to the keyboard and in response to signals from the system receiving data (not shown) to generate signals used in controlling the operation of the keyboard entry system. The signals from the system receiving data play no direct part in the timing and sequencing of the keyboard entry system and are therefore shown only generally.
One set of control signals from the keyboard logic 16 is a set of partial address signals for the ROM 14. These partial address signals uniquely identify the activation of a key for which there is to be an encoded data signal having at least 6 bits transferred to a data receiving device. However, because a ROM is not commercially available in an optimum configuration, economical use is made of a ROM 14 having a 256 word by 4 bit configuration by providing half of an encoded data signal in each of two separate steps. A first half of the ROM 14 is addressed to obtain a first half of the data signal and then a second half of the ROM 14 is addressed to obtain the second half of the encoded data signal. A latch 18 preserves the first half of the data signal while the second half of the ROM 14 is being addressed.
Other outputs from the keyboard logic circuit 16 include signals used to sequence and control the keyboard entry system 10. A reset signal, here designated ORSTK, indicates that a reset key from the keyboard 12 is being activated when true. When a second signal (OKDl) is true, it indicates that exactly one of a selected group of keys to which it is responsive is being activated. This group includes the data keys for which encoded data signals are generated. Use of this OKDl signal permits implementation of a two key rollover feature. A roll over occurs when a second key is activated before a first key is released. This generally creates an error condition in conventional data entry systems. However, by using the OKDI signal, if the first key is activated long enough before the second key is depressed, it merely appears to the timing and sequencing circuits as though no key is activated during the time that both keys are activated. After the first key is released, the entry system it) proceeds as if the second key were just activated. A ORPTK (repeat) signal goes true when a key is activated from a predetermined group for which automatic repeating (simulating repeated release and activation) is to be provided when the key remains depressed. Also provided as outputs from the keyboard logic circuit are a IRETK signal which goes false when a return key is activated, a IRELK signal which goes false when a release key is activated and a OKLOK signal which goes true when a keyboard lock condition exists. This may occur following power turn-on, during an automatic machine operation, or as a result of a mismatch during a verify operation. The reset, release and return keys are interpreted in the keyboard entry system in a secondary manner independent of their normal function to override a keyboard lock condition when two of them are depressed simultaneously. Simultaneous depression of the reset and return keys allows a strobe signal to be generated which controls removal of a keyboard lock situation. Simultaneous depression of the reset and release keys permits a retry after an error signal has occurred during a previous attempt.
Basic timing is provided by frequency divider circuits 20 which are connected to receive a 1.28 MHz clock signal from a clock signal generator 22. Because the multiple outputs from the frequency divider circuits 20 are used for additional timing circuits which are not part of this disclosure, a clear input thereto is connected through a NOR gate 24 from both the OKDl signal and a signal from the additional circuits. Only when both of these signals are false are the frequency divider circuits cleared and constrained to the false condition. In this way neither function will be interrupted in the middle of a sequence. Among the signals output by the frequency divider circuits 20 is a signal having a period T= 6.25 microseconds and signals further illustrated in FIG. 2 which are labeled as signals F, F/2, PM and F/8 having half periods of T/2 6.4, 12.8, 25.6 and 51.2 milliseconds respectively, and a clock signal having a half period T/2 409.6 milliseconds.
Two flip flops such as .l-K flip flops KA 26 and KB 28 are sequenced through four mutually exclusive stable states to provide control of sequential functions. The flip flops 26, 28 are sequenced in order through the states 00, 01, II and l respectively when the OKDl signal goes true. When this signal is false they are constrained to the 00 state by connection of the OKDl signal to negative clear input terminals.
A third J-K flip flop RP 30 controls the automatic repeating function and is similarly constrained to a false or cleared state so long as the OKDl signal is false. RF 30 has its .l input connected to the ORPTK signal and its clock input connected to the f/ 2 4Q 9 6 millisggond signal whose positive going transition clocks the flip flop RF 30 only after 409.6 milliseconds have elapsed subsequent to the activation of a key. The ORPTF output signal therefrom then goes true only if the ORPTK signal was true when the repeat function flip flop RF 30 was clocked. A true ORPTF signal is used as a precondition to an automatic repeat sequence. In this way automatic repeating can occur only when a key from a predetermined group of automatic keys has been activated and a delay of about half a second (409.6 MS) has occurred. This relatively long delay gives an operator time to release a key prior to automatic repeating if only a single entry is desired.
An AND gate 32 has inputs of DI; the negative output of flip flop KB 28, and the clock signal F which goes true after a half period of 6.4 MS. The AND gate 32 is connected to provide flip flop KA 26 an input J QEZ' 6.4 MS. The K input to flip flop KA 26 is connected to the Q or true output of flip flop KB 28 and is thus controlled by the logical function K, Qppg. Both flip flops 26, 28 have negative clock inputs connected to be clocked by the negative going transition of the clock signal having a period T 6.25 microseconds.
A strobe disable logic circuit 33 responds to the OKLOK, ORSTK, IRETK and IRELK to provide a strobe disable signal OSTDA OKLOK ORSTK (Tm IR'EZ'IK). This signal is used to prevent generallows the keyboard to be used by novice operators who cannot handle the high speed repeat without impairing the efficiency of experienced operators who can handle high speed repeating.
The J input to the KB flip flop 28 is connected to the Q or true output of the KA flip flop 26 to attain the logical function J Q A K input logic circuit 36 responds to the signals F, F/2, F/4, F/8, Fast Repeat, ORPKF, OSTDA and O and is connected to drive the K input to the KB flip flop 28 with the logical function K 6.4 MS (Fast Repeat+ 51.2 MS) 25.6 MS m ORPTF O OSTDA. This signal permits the flip flops 26, 28 to be sequenced through new cycles only at the conclusion of each first and subsequent period of continuous key depression. The first period ends only after the ORPTF signal goes true, indicating that a repeat key has been activated for more than 409.6 MS. Subsequent periods end only when the timing condition 6.4 MS (Fast Repeat 51.2 MS) 25.6 MS 12.8 MS becomes true. This happens about 20 times per second if the Fast Repeat signal is true and about 10 times per second otherwise. The O term requires that the KB flip flop 28 be in the true state before its K input goes true. Since the third state, 11, has a much shorter duration than 409.6 MS, the flip flops 26, 28 will always be in the fourth state, 10, when the K input goes true, causing the KB flip flop 28 to switch to the false condition. The OSTDA signal prevents the input to K from going true unless the keyboard lock signal is either false or overridden.
A negative input AND gate 38 has its two inputs connected to the Q or true outputs of the flip flops 26, 28 to generate a logical signal OHLF1= QT; QR. The OHLFI signal is thus true only when the flip flops 26, 28 are in the first mutually exclusive state, 00. The OHLFI signal is connected to complete the addressing of the ROM 14 and is also connected to control a latch 18 which is also connected to receive as inputs the encoded data signals from the ROM 14 and provide as outputs the first half of the data signal which is transferred from the keyboard entry system 10 to an associated data processor. When the OHLFl signal is true, a first half of the ROM 14 is addressed and the output of the latch 18 is free to change to reflect its input. When OHLFI goes false as the flip flops 26, 28 switch from the first state, 00, to the second state, 01, the then appearing output from the first half of the ROM 14 is latched and the second half of the ROM 14 is addressed. This occurs after exactly one key has been depressed for 6.4 MS. This 6.4 MS interval allows sufficient time for switch bounce to dissipate.
The flip flops 26, 28 then remain in the second mutually exclusive state, Ol, for 6.25 us until the output from the second half of the ROM 14 stabilizes. The flip flops 26, 28 then switch to the third mutually exclusive state, Ill. The strobe pulse OKSTR is generated throughout the duration of this third state which lasts 6.25 as. The flip flops then switch to the fourth state, l0, where they remain until constrained to the first state, 00, by loss of the exactly one key down signal OKDI or until they are switched to the first state, 00, by the occurrence of the preconditions for automatic repeating.
Timing diagrams illustrating the signal timing relationships of a key entry circuit in accordance with the invention are shown in FIG. 2 and FIG. 3. FIG. 2 illustrates the overall timing relationships, but because of the tremendous disparity in the frequencies of the clock signal T and the timing signals, F, F/2, F/4i and F/S, the actual switching sequences are not drawn to a consistent time scale in FIG. 2. An actual switching sequence is therefore illustrated separately in FIG. 3 where the time scale is greatly enlarged in comparison to the time scale of FIG. 2.
1 Prior to time t the OKDI signal is false, causing the frequency divider circuits 20 as well as flip flops KA and KB to be constrained to the reset state. At time t exactly one data key is depressed, causing OKDI to go true and activating the frequency divider circuits 20. After the lapse of 6.4 p. sec, at time t,, the signal F goes true, causing J, to go true as most clearly indicated in FIG. 3. At time t which occurs 6.25 1.1. sec after 1,, the clock signal T has a negative going transition to clock flip flop KA to the one state, defined by Q going true. During the interval T to T the flip flops are in the 00 or first mutually exclusive state and the first half of the memory 14 is addressed.
At time 1 the flip flops enter the 01 or second mutually exclusive state, the output from the first half of the memory 14 is latched and the second half is addressed.
As flip flop KA enters the one state at time t signal .I goes true and when the next negative going transition of clock signal T occurs 6.25 p. see later at time t KB switches to the one state, defining the 11 or third mutually exclusive state in the sequence. The strobe pulse is generated throughout this ll portion of the sequence which lasts another 6.25 ,u. sec until time t.,. As the output Q of flip flop KB goes true at time K, also goes true so that when the next negative going transition of clock signal T occurs at time t.,, flip flop KA is switch back to the zero state.
At time t,, the flip flops KB, KA enter the or fourth mutually exclusive state in the sequence and hold in that state until cleared by the absence of the OKDI signal or the initiation of an automatic repeat.
The timing for automatic repeating is illustrated in FIG. 2. If an automatic repeat key remains depressed for approximately 409.6 ,u. see, time t,, is reached and the proper logic conditions occur to make signal K go true. 6.25 p. sec later clock signal T produces a negative going transition causing both flip flop KB and signal K to switch to the zero state. The flip flops KB, KA enter the mutually exclusive state 00 at this time and a new switching sequence is begun. Each of the switching sequences are identical so that the time t in FIG. 1 can be superimposed on the first repeat time and subsequent repeat times t t I The signals K and Q at time L, are represented in FIG. 3 as dotted lines 50, 52 respectively in order to illustrate such superposition.
As illustrated in FIG. 2, if the automatic repeat switch is on, subsequent timing sequences occur at approximately 0.05 second intervals as indicated by times t, and However, if the fast repeat switch is not on, automatic repeating occurs only when signal F/8 is false and the repeating rate is reduced by one-half from approximately times per second for fast repeating to approximately 10 times per second for slow repeating.
Although there has been described above a specific arrangement of a keyboard entry system in accordance with the invention for the purpose of illustrating the manner in which the invention may be used to advantage, it will be appreciated that the invention is not limited thereto. Accordingly, any modifications, variations or equivalent arrangements which may occur to those skilled in the art should be considered to be within the scope of the invention. What is claimed is: I. A digital timing circuit controlling the input of data from a keyboard to a device accepting key input data comprising:
a plurality of bistable elements having in combination at least three mutually exclusive stable states;
means responsive to the keyboard for sequencing the bistable elements through at least three of the mutually exclusive states, thesequencing means causing the bistable elements to remain in the sequenced states for controlled periods of time; and
means responsive to the sequenced states of the flip flops for generating at least one control signal including a data strobe signal causing the transfer of keyed information to the device accepting key input data.
2. The circuit as set forth in claim 1 above, wherein the bistable elements include two flip flops having in combination four mutually exclusive states.
3. The invention as set forth in claim 2 above, wherein the flip flops have the following states in sequential order, 00, 01, ll, 10.
4. The invention as set forth in claim 3 above, wherein the sequencing means constrains the flip flops to the 00 state unless exactly one key of a selected first group of keys is depressed and sequences the flip flops from the 10 state to the 00 state only when a key of a selected second group of keys is depressed and, in addition only at the conclusion of first and subsequent periods of predetermined length throughout which exactly one key from the first group and one key from the second group has been continuously depressed.
5. The invention as set forth in claim 4 above, wherein the first period has a duration of approximately 0.4 seconds and the subsequent periods each have a duration of at least 0.05 seconds.
6. The invention as set forth in claim 3 above, wherein the data strobe signal is generated whenever the flip flops are in the 11 state.
7. The invention as set forth in claim 1 above, wherein the sequencing means includes a frequency divider circuit having multiple outputs at successively lower frequencies connected to provide timing for the sequencing means.
8. A keyboard unput system comprising:
a keyboard having a plurality of keys, at least one of the keys being an automatic repeat key;
means for providing an encoded signal indicative of an activated key in response to the activation of a y;
a keyboard logic circuit responsive to the keyboard and generating a one key down signal whenever exactly one key of a selected group of keys is activated and generating a repeat signal whenever a repeat key is depressed;
at least two flip flops having in combination a plurality of mutually exclusive stable states;
means for sequencing the flip flops through at least three of the mutually exclusive stable states including a first state and a last state in response to the one key down signal, the sequencing means causing the flip flops to remain in sequenced states for predetermined periods of time, constraining the flip flops to the first state in the absence of a one key down signal and sequencing the flip flops from the last state to the first state only when the repeat signal is being generated; and
means responsive to the sequenced states of the flip flops for generating at least one control signal including a data strobe signal causing the transfer of the encoded signal to a device connected to receive key input data, the data strobe signal being generated when the flip flops are in a selected stable state intermediate the first and last states.
9. The invention as set forth in claim 8 above, wherein there are two flip flops which are sequenced through four stable states and an additional condition for sequencing of the flip flops from the last stable state to the first stable state is the conclusion of each first and subsequent period of time during which the one key down signal is generated without interruption, the first period being approximately 0.4 second and the subsequent periods being at least 0.05 second.
10. For use in a key input system having a keyboard having a plurality of keys including a reset key, a return key and a release key; means for providing an encoded signal indicative of a particular activated key in response to the activation of a key; a keyboard logic circuit generating a first signal (ORSTK) in response to activation of the reset key, a second signal (OKDl) in response to activation of exactly one key from a selected group of keys, a third signal (RPTK) in response to activation to a key from a selected second group of keys, a fourth signal (IRETK) in response to nonactivation of the return key, a lRELK signal in response to non-activation of a release key, and a fifth signal (OKLOK) signal in response to the presence of a predetermined set of conditions for which the keyboard is to be locked; a high frequency clock signal generator; and a divider circuit generating clock signals at selected submultiples of the high frequency clock signal rate in response to the high frequency clock signal; a timing circuit comprising:
a repeat flip flop generating a sixth signal (ORPTF) when in a true state, the repeat flip flop being constrained to a false state in the absence of the OKDl signal and being switched to the true state in response to a simultaneous occurrence of the ORPTK signal and a relatively low frequency clock signal from the divider circuit;
first and second flip flops, each having Q and Q outputs representing true and false output states respectively and true, false, clock and clear inputs, the clear inputs being connected to constrain the flip flops to the false output state in response to the absence of the OKDl signal, and the clock inputs being responsive to negative transition of a relatively high frequency clock signal from the divider circuit having a period at least as long as the time required for switch bounce to disappear after activation of a key on the keyboard;
means responsive to a true output state of the first flip flop for activating the true input to the second flip flop;
means responsive to manual control for generating a FIE the input logic activatfi g the false input to the second flip flop upon the occurren c e of th logi al Condition E AS P TJE F 3.) iE/ZJ E14" ORPTF Q where Q5 is tlieQ output from the second flip flop;
means connected to activate the true input to the first flip flop in response to the logical condition QB; F, where Q7 is the Q output from the second flip p;
means connected to activate the false input to the first flip flop in response to the Q signal; and
means responsive to the OSTDA and Qppg signals and a Q signal representing the Q output of the first flip flop for generating a data strobe signal causing the transfer of keyed information to a device accepting key input data, the data strobe signal being generated upon occurrence of the logical condition QFFI QFF2 OSTDA- 11. The invention as set forth in claim 10 above,
wherein the clock signal F has a period of approximately 12.8 milliseconds.
12. A key input system comprising:
a keyboard having a plurality of keys;
keyboard logic responsive to the activation of keys on the keyboard, the keyboard logic generating a first signal (OKDl) in response to the activation of exactly one key within a predetermined first group of keys, a second signal (ORPTK) in response to activation of a key within a predetermined second group of keys, and partial address signals uniquely identifying the activation of a key within a predetermined third group of keys;
a read only memory providing as an output multibit codes in response to memory locations addressed by the partial address signals and a third signal (OHLFl), a given arrangement of partial address signals defining a word location in a first half of the memory when the Ol-lLFl signal is true and a corresponding word location in a second half of the memory when the OHLFl signal is false;
a latch responsive to the output codes from the read only memory and the Ol-lLFl signal, the output codes from the read only memory being latched when the OHLFI signal changes from true to false and being output by the latch so long as the OHLFl signal remains false;
at least two flip flops defining in combination at least four mutually exclusive states;
means responsive to the ORSTK signal and the OKDl signal for sequencing the flip flops through at least first, second, third and last states respectively, the flip flops being (1) constrained to the first state in the absence of an OKDl signal, (2) sequenced from the first state to the second state only after a sufficient time delay to allow dissipation of keyboard switch bounce, (3) sequenced from the second state to the third state only after sufficient time delay to permit latching of an output code from the first half of the read only memory and establishment of an output from the second half of the read only memory, (4) sequenced from the third state to the last state only after sufficient time to allow the transfer of output codes from the key input system to a data receiving device, and (5) sequenced from the last state to the first state only at the conclusion of each first and subsequent period of time throughout all of which both the OKDl and ORPTK signals remain true, said first period of only when the flip flops are in the third state.
- 'g;;g UNITED STATES PATENT 0mm I m T; ("1 CERTEFXCA 1 E OF CORfiE I EON Patent No. 3 ,78l,874 Dated lieggmbe; Z5 1,223,
Inv encofls) Alafi K ,lg mingg I It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:
Column 6, line 55 "unput" should read --input-- (Claim 8, line 1) Signed and seeledthis 16th day of April 19m.
( SEAL) Attestt' 1 v EDWARD I'LFLETCHERJR. G MARSHALL DANN Attesting Officer Commissioner of Patents
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|U.S. Classification||341/26, 400/477|
|International Classification||H03M11/20, H03M11/00|
|Jun 17, 1991||AS||Assignment|
Owner name: SAND OPTICS, LTD A CORP. OF DE, CONNECTICUT
Free format text: RELEASED BY SECURED PARTY;ASSIGNOR:CONNECITITUCUNECT NATIONAL BANK, THE;REEL/FRAME:005760/0597
Effective date: 19910104
|Jun 17, 1991||AS17||Release by secured party|
Owner name: CONNECITITUCUNECT NATIONAL BANK, THE
Owner name: SAND OPTICS, LTD A CORP. OF DE 22 PRESTIGE CIRCLE
Effective date: 19910104
|Nov 5, 1987||AS02||Assignment of assignor's interest|
Owner name: PERTEC COMPUTER CORPORATION, (A DE. CORP.)
Effective date: 19871005
Owner name: SCAN-OPTICS, INC., TWENTY TWO PRESTIGE PARK CIRCLE
|Nov 5, 1987||AS||Assignment|
Owner name: SCAN-OPTICS, INC., TWENTY TWO PRESTIGE PARK CIRCLE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:PERTEC COMPUTER CORPORATION, (A DE. CORP.);REEL/FRAME:004812/0121
Effective date: 19871005