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Publication numberUS3798428 A
Publication typeGrant
Publication dateMar 19, 1974
Filing dateMar 20, 1972
Priority dateMar 20, 1971
Also published asDE2213460A1, DE2213460B2
Publication numberUS 3798428 A, US 3798428A, US-A-3798428, US3798428 A, US3798428A
InventorsIzawa M
Original AssigneeSeikosha Kk
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Electronic time-keeping apparatus
US 3798428 A
Abstract
An electronic time-keeping apparatus generating counting pulses for a time count. The counting pulses are stored in registers connected to input gates of adders that develop, from the counting pulses stored by the registers, output signals through gates corresponding to a time count. The adders develop carry signals that are temporarily stored by a carry memory register and are applied back to the adders under control of a carry signal controller and through the latter for developing the time count output of the adders for higher order places in the time count. The time count is displayed on visual display means as a time indication corresponding to the time count. Provision is made for initial counting errors by use of an automatic initial error preventive circuit that detects errors in the counting signals stored which may result from noise or at the start of the count and signals are developed that are applied to the adders thus varying the signal content received by the adders so that the time count output thereof is free of these initial errors. Control circuitry in the form of reset circuitry is provided for resetting the time count by applying signals at will to the adders to reset the time count output and thereby the time indication of the visual display means. The control circuitry includes time advancing circuitry by which the time count output is advanced by applying signals to the adders at will so that the time count indication is advanced and an advanced time or corrected time may be displayed. The apparatus may be embodied in small clocks.
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United States Patent [191 Izawa ELECTRONIC TIME-KEEPING APPARATUS [75] Inventor:

[73] Assignee: Kabushiki Kaisha Seikosha, Tokyo,

Japan [22 Filed: Mar. 20, 1972 21 App]. No.: 235,959

Minoru lzawa, Matsudo, Japan [30] Foreign Application Priority Data Mar. 20, 1971 Japan 46-15668 [52] US. Cl. 235/168, 58/23 R, 235/92 T [51] Int. Cl. G06f 7/385 [58] Field of Search 235/168, 170, 176, 92 SH, 235/92 T; 307/221 R; 58/23 R Primary Examiner-Eugene G. Botz Assistant ExaminerJames F. Gottman Attorney, Agent, or Firm-Robert E. Burns; Emmanuel J. Lobato [57] ABSTRACT An electronic time-keeping apparatus generating SHIF T RE 6/6 TER SH/FT REGISTER .S/f/FT REGISTER SHIFT REGISTER CARRY CONT r/nwa PULSE man mm Pl/ZSE arm D/SRLAY L TIN/N6 PULSE FRO/1 T/lfl/VG PULSE GEN RESET CKT RESET sw/m/ [4 1 Mar. 19, 1974 counting pulses for a time count. The counting pulses are stored in registers connected to input gates of adders that develop, from the counting pulses stored by the registers, output signals through gates corresponding to a time count. The adders develop carry signals that are temporarily stored by a carry memory register and are applied back to the adders under control of a carry signal controller and through the latter for developing the time count output of the adders for higher order places in the time count. The time count is displayed on visual display means as a time indication corresponding to the time count. Provision is made for initial counting errors by use of an automatic initial error preventive circuit that detects errors in the counting signals stored which may result from noise or at the start of the count and signals are developed that are applied to the adders thus varying the signal content received by the adders so that the time count output thereof is free of these initial errors. Control circuitry in the form of reset circuitry is provided for resetting the time count by applying signals at will to the adders to reset the time count output and thereby the time indication of the visual display means. The control circuitry includes time advancing circuitry by which the time count output is advanced by applying signals to the adders at will so that the time count indication is advanced and an advanced time or corrected time may be displayed. The apparatus may be embodied in small clocks.

10 Claims, 4 Drawing Figures TIMI/V6 PAIENTEDMAR 19 m4 3; 798,428

SHEEI 2 0F 4 HALF 54C ADDER 54d HALF 4000? m M) x HALF 56 ADDER JH/FT REG/675R l l I Eager-I SH/FT 56/5751? SH/FT REG/57H? l I I HALF ADDER 57d 5/17/7- PULSE FRO/1 STD PULSE GEN DECODER KEY 70 FIGURES -r/m/va PULSE F/6 H6 65b 66a 66a FROM 0500051? /05 2A 25 1 ELECTRONIC TIME-KEEPING APPARATUS BACKGROUND OF THE INVENTION This invention relates generally to time-keeping devices and more particularly to electronically controlled time-keeping devices.

An example of a hitherto used time keeping device that keeps time electronically is a device having counters in series serving only to count a required time after the output frequency of a quartz oscillator which generates a standard frequency divided by a frequency divider. The device counts the output signal of the abovementioned frequency divider thus indicating the time. For instance, when time is counted using the time unit of a second and using a 24 hour indication clock, the following counters are used: a decimal counter is provided for'use in counting the first place of a second, the first placeof a minute and the first place of an hour, and a hexadic counter is used for the tenth places of a second and a minute and a triadic counter for the tenth place of an hour. In addition circuitry is provided to reset at 24 hours minute 0 second. Time is displayed by supplying a time indicating element with a signal voltage through a decoder circuit for the output of each counter. But this requires input and output terminals to be needed in quantity and consequently, for example, when it is required to use an integrated circuit, especially a large scale integrated circuit, the number of terminals for input and output is limited. Ifa great number of terminals is needed, it could hinder the use of integrated circuits.

Resetting of the counters manually is generally required, and, therefore, resetting takes place only when a specific time unit or counter is off. Manual switches are used to correct the time and are provided at interstages among the counters for the purpose of controlling the driving of each. Accordingly the known circuitry using semiconductors must use them in large quantities and this results in large power consumption. Thus when a small size, and therefore small capacity, power supply is required, for example in a small-sized clock which uses a dry cell, the power source has generally not been suitable.

SUMMARY OF THE INVENTION The present invention overcomes the abovementioned difficulties and provides a newly improved electronically-controlled time-keeping device. An electronically-controlled time-keeping device according to the invention comprises register means storing a time signal; adder means are provided to add the output time signal of the register means and the time signal and to apply the added counting time signalto the register means. Carry memory register means are provided to store temporarily a carry signal generated by the adder means and to apply the carry signal to the adder means and add the carry signal to the time signal in a next place when the time signal in a next place is produced by the register means. Carry controlled means generate an output signal upon receiving the counting time signal at each time of the carry operations and.

allow the carry signal to be stored in the carry memory register. Clock pulse generating means generate clock signals controlling the above-mentioned respective operations, and display means display the counting time.

The device according to the invention is most suitable for being incorporated as [C circuitry and is very convenient for use with a secondary clock.

It is an object of the invention to provide a smallsized, electronically-controlled time-keeping device with low power consumption.

It is another object to provide an electronicallycontrolled time keeping device in which the terminals to a display means are small in number, and the output terminals of timing pulse generating means are used in common for advance means, reset means and display means so as to reduce the number of terminals thereby to be convenient for construction as an integrated circuit.

It is another object of the invention to provide an electronically-controlled time-keeping device capable of being reset at any suitable time at will because of its simple construction.

Still another object of the present invention is to provide an electronically-controlled time-keeping device capable of being reset when kept in storage in registers due to noise at the time of closing of a power supply, etc.

BRIEF DESCRIPTION OF THE DRAWINGS The nature of the present invention as well as other objects and advantages thereof will become more apparent from consideration of the following detailed description and the accompanying drawing in which:

FIG. 1 is an overall functional block diagram of an electronically-controlled time-keeping device in accordance with the invention;

FIGS. 2A and 2B are block diagrams of an embodiment of a system according to the invention; and

FIG. 3 is a table of memory contents of registers shown in FIG. 2A.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention is explained below as relating to a time-keeping device with a maximum time count of up to 12 hours. As shown in FIG. 1, the device comprises means to generate clock signals constructed as a clock pulse generating means 1. This clock means consists of a standard pulse generator 1a and a timing pulse generator 1b. The timing pulse generator lb is provided with a frequency divider having a 1/n dividing ratio and a decoder, and it generates timing pulses in turn at output terminals a a ...a,, of the timing pulse generator 1b every time it receives an output pulse of the standard pulse generator la. Shift registers 2, 3, 4, and 5 store the time count. Suppose this embodiment has a storage capacity of n bits and assume one bit storage position to be A1, A2...A B1, B2...B", C1, C ...C,,, D1, D2...D Half-adders 6,7,8 and 9 count time by adding the output of the shift registers 2,3,4 and 5 to a time signal. A carry memory register 10 stores a carry signal for each place of time which is kept in the memory temporarily as a carry signal of the half-adder 9.

A carry controller 11 to control the carry of each place of time generates an output pulse when supplied with the carry signal prestored in the carry memory register 10 and another signal from the timing pulse generator lb while the outputs of shift registers 2,3,4 and 5 are ready to carry at each place indicative of the time.

An initial error preventive circuit 12 resets the erroneous contents that happen to be stored in the shift registers 2,3,4 and due to noise or other disturbances. Gates 13,14... 17 connected to the shift registers are OR gates, and gates 18, l9...22 connected to the halfadders are AND gates. A display 23 displays the time. A time counting start switch 24 initiates the count. A reset circuit 25 is composed of gate circuits which generates a reset output signal by the operation of a reset switch 26 and resets a desired counting time in the shift registers 2, 3, 4 and 5. A time advance circuit 27 is used to advance a suitable time in the shift registers 2,3,4 and 5 and consists of flip-flop circuits and gates. A time advance switch 28 is used to operate the time advance circuit 27. A tIming pulse select switch 29 selects a suitable output pulse from the output terminals a,,a ...a,, of the timing pulse generator 1b.

OPERATION OF THE DEVICE The operation of this time-keeping device will now be explained. Upon closing of the time counting start switch 24, a given cycle of timing pulses is generated from the timing pulse generator 1b. The timing pulse generator lb operates in nth notation, and so when the nth pulse produces a pulse at an output terminal a of the timing pulse generator lb, after that the (n+l)th pulse, (n+2)th pulse....produces in turn a pulse at output terminals a man. For example, if time is counted to the order of a millisecond unit as a minimum, it will generate pulses to control the operation of time ranging to nine figures or places from the first place of the millisecond to the maximum time place, that is, to the tenth place of time because this embodiment takes up to a 12 hours display.

The shift registers 2,3,4 and 5 have a storage capacity covering from the place of the minimum time to the place of the maximum time. As explained above, this is n bits. And four bits consisting of four outputs of the shift registers 2,3,4 and 5 represent the time of each place. Now suppose all the shift registers 2,3,4 and 5 are reset at O, and the time counting start switch 24 is closed when they are under this condition. N pulses are supplied from the standard pulse generator to the timing pulse generator 1b, a logical output 1 is generated at the output terminal a, of the place of the minimum time and fed to the input terminal 6a of the halfadder 6 through an OR gate 17, while the above nth pulse works as a shift pulse for shift registers 2,3,4 and 5 and shifts the storage contents in the shift registers to the right by one shift. But since the shift registers 2,3,4 and 5 are reset at O, the contents of the storage positions (An, Bn, Cn, Dn) are (0, O, O, O), and it is O which is supplied to the input terminals 6b, 7b, 8b and 9b of the half-adders 6,7,8 and 9 through the OR gates 13,14,15 and 16. As a signal correspondong to l is applied to the input terminal 6a of the half-adder 6, its output terminal 60 produces a signal corresponding to l, which is then fed to the input terminal 18a of AND gate 18. As 1 is being supplied from the reset circuit 25 to the input terminal 18b of the AND gate 18, AND gate 18 produces an output I, which is then fed back to the input of the shift register 2 and stored at the storage position A Considering the half-adder 7, its input terminal 7a is connected with the carry terminal of the half-adder 6 and is maintained 0 because the carry signal is 0. Since the input terminal 7b is being supplied with storage contents 0 at the storage position Bn of the shift register 3 by the shifting operation described above, the output tenninal 7c of the half-adder 7 produces O. Consequently, the output of the AND gate 19 becomes 0 and is fed back at the storage position B, of the shift register 3. Similarly, O is stored at the storage positions C,,D, of shift registers 4,5.

Accordingly, l, O, O, O) are stored at the storage positions (A,,B,,C,, D,) of the shift registers 2,3,4 and 5. Then (n+1 )th pulse from the standard pulse generator la is produced, and the contents of the shift registers 2,3,4 and 5 are shifted to the right by one shift. Further by generated pulses (n+2)th, (n+3)th...(2n-l )th, the contents of the minimum time (1, O, 0, 0) are shifted at the storage positions (An,Bn,Cn,Dn) of the shift registers 2,3,4 and 5. At the 2nth generated pulse, the contents (l,0,0,0) of storage positions (An,Brz,Cn,Dn) of the shift registers 2,3,4 and 5 are supplied to each input terminal 6b,7b,8b and 9b of the half-adders 6,7,8 and 9. With the 2nth generated pulse, meanwhile, an output 1 at the terminal of the timing pulse generator lb is produced. The output 1 is fed to the half-adder 6 through OR gate 7. Accordingly, I 1 addition is performed by the half-adder 6. As a result, 0 is produced at the terminal 6c and stored at the storage position A of the shift register 2. On the other hand, at the carry terminal 6d, a carry output 1 is produced, which is then fed to the input terminal 7a of the half-adder 7. Since the input terminal 7b is being supplied with 1, the output terminal 7c produces 0, which is then stored at the storage position B of the shift register 3. As the outputs 8c, 9c of the half-adders 8,9 are 0 respectively, the storage positions C,,D, of shift registers 4,5 store 0, 0. Therefore, the contents of the place of the minimum time to be stored at the storage positions (A,,B,,C,,D- )of the shift registers 2,3,4 and 5 become (0,1 ,0,0) and if defined in decimal notation, it becomes 2. In this way time is counted.

THE DISPLAYING OPERATION When the contents of the shift registers 2,3,4 and 5 are shifted by shift pulses generated from the standard pulse generator 1a, and the outputs from the storage positions (An,Bn,Cn,Dn) are produced, display elements are selectively lighted by the above outputs and the outputs from terminals a ,a ...a,, of the timing pulse generator 1b. For example, if for the display elements in the display 23, Nixie tubes are used, the decoded outputs of the shift registers 2,3,4 and 5 select the common digit segments of each display element and the choice of display elements is made in a given cycle in turn from the place of the minimum time to the place of the maximum time with the outputs of the timing pulse generator lb. This lighting cycle is established within the after image time of the eyes, i.e. taking into consideration the image retention of human eyes, so the display appears as if it were lighted up almost continuously. This display method is well known in the prior art.

THE CARRY OPERATION An explanation is then made relating to the carry operation to shift a place of a certain time to the place of the next time by taking up the example from the case of the above-mentioned place of the minimum time. Suppose the place of the minimum time is expressed in decimal notation and (1,0,0,0) are stored at the storage positions (An,Bn,Cn,Dn) of the shift registers 2,3,4 and 5. Then if m th output 1 is generated from the output terminal a, of the timing pulse generator lb, the contents of the shift registers 2,3,4 and 5 are shifted to the right by one shift. Therefore, the carry controller 11 is operated by the outputs l, l of shift registers 2,5 and produces output 1, which is then supplied to the input terminals 6b,7b,8b and 9b of the half-adders 6,7,8 and 9 through OR gates 13,14,15 and 16. Since the abovementioned mth output 1 is being supplied to the input terminal 6a of the half-adder 6 through the OR gate 17, an output 1 is generated from the carry terminal 6a of the half-adder 6 and is then supplied to the input terminal 7a of the half-adder 7. It is thus added to the input 1 of the input terminal 7b, thereby causing the carry terminal 7d to produce an output 1. In the same way, half-adders 8,9 generate carry output I. A carry output generated from the carry output terminal 9d of half-adder 9 is stored at the carry memory register 10. Since all outputs from the output terminals 6c,7c,8c and 9c of the half-adders 6,7,8 and 9 are 0, (0,0,0,0) are stored at the storage positions (A B C,,D,) of the shift registers 2,3,4 and 5.

In addition, when the contents of the shift registers 2,3,4 and 5 are shifted by (m+l )th output I from the standard pulse generator 1a, the contents of time of one place higher than the minimum time which was stored previously at storage positions An,Bn,Cn,Dn, will be supplied to the half-adders 6,7,8 and 9. In the meantime, the above-said (m+l )th pulse takes out the carry output 1 of the minimum time prestored in the carry memory register 10 and supplies it to the input terminal 6a of the half-adder 6 through OR gate 17, and then it is added to the time of one place upper being supplied to each input terminal 6b,7b,8b and 9b of the half-adders 6,7,8 and 9.

The carry operation for shifting to the higher place is thus performed.

Depending upon the contents of the tenth place of time, especially in 12 hours, the carry state of the first place of the time varies. In other words while the tenth place of the time is in decimal notation, the first place of the time is carried with 9, If the tenth place of the time becomes 1, however, the first place carry must be performed with 2. For example, suppose the contents of the first place of the time such as (l,0,0,0) are now stored at the storage positions (An,Bn,Cn,Dn) of the shift registers 2,3,4 and 5. The carry contents of the first place of time is also stored in the carry memory register 10, and the contents of the tenth place of time, that is, (l,0,0,0) are stored up at the storage positions (An-l,Bn-1,Cn-l,Dn-l) of the shift registers 2,3,4 and 5. If the standard pulse generator 1a generates a pulse under thiscondition, the contents of the shift registers 2,3,4, and will be shifted to the right by one shift, and at the same time, the storage contents of the carry memory register can be taken out. The carry controller l l operates with the outputs l of the storage positions An,An-l and supplies 1 to the input terminals 6b, 7b, 8b and 9b of the half-adders 6,7,8 and 9 through OR gates 13,14,15and 16. As the input terminal 6a of the half-adder 6 is being supplied with the output 1 of the carry memory register 10, (0,0,0,0) are generated at the output terminals 6c,7c,8c and 9c of the halfadders 6,7,8 and 9 and then stored at the storage positions (A,,B,,C,,D,) of the shift registers 2,3,4 and 5.

The time is reset in this way, followed by a display beginning with 0 again.

INITIAL ERROR PREVENTIVE CIRCUIT It is most probable that due to noise produced when the time-keeping device is supplied with a power source, a numerical value more than 10, or (0, l ,O,l) in binary coded decimal notation may be stored in the shift registers 2,3,4 and 5. In order to prevent this, therefore, the initial error preventive circuit 12 is provided; and it is set in such a way as to generate a signal in case an output more than (0,l,0,l) is produced from the shift registers 3,4,5 and 6, so that the outputs of the half-adders 6,7,8 and 9 becomes 0 by its output and standard pulse. Now, for example, suppose that (l,l,0,l) are stored at the storage positions (An,Bn,Cn,Dn) of the shift registers 2,3,4 and 5 because of noise introduced by closing of a power supply. When the standard pulse generator, la generates a 7 pulse, the input of the initial error preventive circuit 12 is applied with (1,1) of the storage positions (Bn,Dn) and I is then produced for the output and supplied to the input terminals 6b,7b,8b and 9b of the half-adders 6,7,8 and 9 through OR gates 13,14,15 and 16. In the meantime, the output I of the initial error preventive circuit 12 is supplied to the input 6a of the half-adder 6 through OR gate 17, and accordingly, 0 is generated at the outputs 6c,7c,8c and 9c of the half-adders 6,7,8 and 9 and (0,0,0,0) are then stored at the storage positions (A,,B,,C,,D,) in the shift registers 2,3,4 and 5.

In the same manner, any number more than (0,1 ,0,1 being kept in the storage at the shift registers 2,3,4 and 5 is reset. However, even without using the initial error preventive circuit 12, the carry output on that occasion may be stored at the shift registers 2,3,4 and 5 if only the outputs of the half-adders become 0 after counting up to (1,1,1 ,1 and afterwards, complete normal operation is performed. For this reason, if an erroneous display at the initial operation can be ignored, the initial error preventive circuit 12 is not needed.

TI-IE RESET OPERATION Next, an explanation is given with regard to the reset operation. Resetting in this embodiment makes it possible to reset selectively not only the storage contents of the shift registers 2,3,4 and 5 but also the place of each time. First, by the timing pulse select switch 29, select, for instance, the output terminal a,, and close the reset switch 26, and the reset circuit 25 produces an output 1. However, if the output is produced at the terminal a,, the reset circuit 2 produces O and makes the input terminal of the AND gate 9 maintain 0. Accordingly, the output becomes 0 and allows (0,0,0,0) to be stored at the positions (A,,B,,C,,D,) of the shift registers 3,4,5 and 6, thus performing reset action for the place of the minimum time.

Similarly, by selecting any suitable terminal such as a,,a ...a,, with the select switch 29, any suitable place of time can be reset.

Next, the time advance function for the purpose of correcting time is explained below. From among the output terminals a,,a ...a,, of the time of the place advanced, select any suitable terminal, for example, a, with the select switch 29. And upon closing of the time advance switch 28, the output 1 is generated and stored once in a memory circuit of the time advance circuit 27 which produces an output, which is then applied to the input terminal 6b of the half-adder 6. It is added to the output of the shift register 2, thus a time advance operation is achieved. The contents stored in the memory circuit of the above-mentioned time advance circuit 27 are reset by a building-up of an adding pulse for advance.

DESCRIPTION OF PREFERRED EMBODIMENT The preferred embodiment of the invention is illustrated in FIG. 2 which shows a time-keeping device with a function of 24 hours display in which the minimum counting time is lOOps. Shift registers 30,31,32 and 33 store the counting time and have a storage capacity of 10 bits respectively. The storage positions of each bit are shown as A ,A ...A, B B mB C,,C ...C D,,D ...D, Each place of the counting time is represented by four bits stored at each of the storage positions (A B C D (A ,B ,C D .(A ,B ,C ,D Half-adders 34, 35, 36 and 37 carry out the counting of time in adding time signals to the counting time of the shift registers 30,31,32 and 33. F lip-flop circuit 38 constitutes a carry memory register and stores the carry signal of the half-adder 37 temporarily. Gates, consisting of OR gates 39,40...51, AND gates 52,53...68, NAND gates 69,70,73 and NOR gates 74,75, control logical operations. Inverters 76,77...100 produce phase inversion between their input and output pulses.

The above-mentioned OR gate 48 and AND gate 59 together compose an initial error preventive unit. AND gates 56,57,58 and OR gates 44,45 compose a carry control unit in hexa notation. AND gates 59,60,61 and OR gates 47,48 compose a carry control unit in decimal notation. and AND gates 62,63...66 and OR gates 49,50,51 compose a carry control unit in 24 notation. A standard pulse generator 101 in this embodiment generates a train of pulses of lO,u.s width with a one-half duty cycle.

A frequency divider 102 with a setting of dividing ratio l/lO generates timing pulses to correspond with the place of each time through a decoder 103. The decoder 103 is provided with output terminals, namely 103a, l03b...103j, which generate timing pulses, in turn, for each time of a place of loops, lms, l0ms, 100ms, 1 second, 10 seconds, 1 minute, 10 minutes, 1 hour and 10 hours. If the standard pulse generator 101 generates 10 pulses, the terminal 103a produces an output of pulse width 10p.s and the terminal l03b generates an output of a pulse width 10p.s when the llth timing pulse is produced. Similarly, pulses are generated at terminals 103e, 103d...103j in order every moment they are supplied with pulses transmitted from the standard pulse generator 101. Accordingly a pulse of 10 1.5 width in a lOOus cycle is generated from each output terminal 103a, 103b...103j. The abovementioned standard pulse generator 101, the frequency divider 102 and the decoder 103 compose a clock pulse generating unit 104.

Flip-flop circuits 105,106 are circuits for advancing time by manual operation. A decoder 107 converts the outputs of the shift registers 30,31,32, and 33 into codes to select the display elements of time of each place which compose a display 108. A reset switch 109 resets the shift registers 30,31,32 and 33 and a time advance switch 110 properly advances the counting time by generating an output from a flip-flop circuit 106, and a time counting start switch 111 controls a, time counting operation. A rotary switch 112 composes a timing pulse select switch for use in selecting a suitable output pulse of the decoder 103, consisting of an open contact 112a, output terminals for each place of time 1 12b, 1 12c...112k for each place of time and a segment 1121.

OPERATION OF THE PREFERRED EMBODIMENT Next, an explanation is given with respect to the operation. Assume an initial condition, power is supplied and the segment 1090 of the reset switch 109 is connected to the terminal 109b, while the segment 1106 of the time advance switch is connected to the terminal 110a. Under the assumed condition the storage contents of the shift registers 30,31,32 and 33 are 0. The normal output level of the decoder 103 is set to l and it is inverted to 0 when the decoder 103 generates the output. First, connecting a movable contact 111a of the time counting start switch 11 1 to the terminal lllb at the start side, the input terminal 68a of AND gate 68 becomes 1. Now suppose that a tenth pulse is generated from the standard pulse generator 101, the frequency divider 102 produces an output 0 at the output terminal 103a for lOOps place of the decoder 103 because of its dividing ratio l/ 10. The output then is inverted by the inverter 80, thus allowing the level of the input terminal 68b of the AND gate 68 to be inverted to 1. Accordingly, the output of the AND gate 68 is inverted to 1 and makes the input terminal 34a of the half-adder 34 reach to 1 level through the OR gate 43 (F IG. 2A). The contents of the shift registers 30,31,32 and 33 are shifted to the right by one shift when the above-mentioned tenth shift pulse is applied from the standard pulse generator 101 (FIG. 28). Since the contents of storage positions (A, ,B, ,C, ,D are (0,0,0,0), however, respective input terminals 34a,35a,36a and 37a of half-adders 34,35,36 and 37 are maintained at 0. Consequently, the terminal 340 of the half-adder 34 produces l, which then inverts an input of the AND gate 52 into 1. The other input of the AND gate 52 is maintained by an output level from NAND gate 69 (FIG. 2B), and the input terminal 690 of the NAND gate 69 is kept to an output level 0 of the NAND gate 70. For this reason the output level is maintained to l, and the input terminals 52b,53b,54b, and 55b of AND gates 52,53,54 and 55 are also kept at 1.

When the input terminal 52a of the AND gate 52 is inverted to l, the output then becomes 1, which is stored at the storage position A of the shift register 30. In the meantime, the carry output terminal 34d of the half-adder 34 becomes 0, and then the respective terminals 35a,36a,37a of half-adders 35,36, and 37 becomes O. Therefore, outputs 0 at the output terminals 35c,36c and 370 of half-adders 35,36 and 37 are fed back to shift registers 31,32, and 33 and stored as 0 at the storage positions B ,C and D and accordingly, (1,0,0,0) is stored at respective storage positions (A B C D The storage contents (1,0,0,0) of shift registers 30,31,32 and 33 are shifted in turn to the right by one shift when given the 1 1th and 12th shift pulses from the standard pulse generator 101 (FIG. 2B) and further shifted to the memory positions (A B C D of the shift registers 30,31,32 and 33 when given the 19th shift pulse. When the 20th shift pulse is generated from the standard pulse generator 101, outputs from the shift registers 30,31,32 and 33 or (1,0,0,0) are supplied to the input terminals 34b,35b,36b and 37b of half-adders 34,35,36 and 37. Simultaneously when the above-mentioned 20th pulse is generated, the terminal 103 a of the decoder 103 produces 0, which is then supplied to the input terminal 340 of the half-adder 34 through the inverter 80, the AND gate 68 and OR gate 43 (FIG. 2A). As a result, is generated from the output terminal 34c of the halfadder 34 and stored at the storage position A, through the AND gate 52. In the meantime, a carry output 1 generated from the output terminal 34d is supplied to the input terminal 35a of the half-adder 35, and an output l is then generated from the output terminal 350 and stored at the storage position B. As an output at the output terminal 35d of the half-adder 35 is 0, output 0 is generated from the output terminals 36c,37c of halfadders 36,37, and 0, 0 are stored at storage positons C D As mentioned above, (O,l,0,0) is stored at the storage positions (A ,B,,C ,D,). In this way counting time is performed in order.

A description is then given relative to the case in which counting time id displayed. Suppose 2 minutes are stored in the shift registers 30,31,32 and 33 and the time (0,l,0,0) in the first place of minute is shifted to storage positions (A, ,B, ,C, ,D, When the standard pulse generator 101 generates a pulse, the contents (0,l,0,0) of the storage positions (A B C D are then shifted to the right and supplied to the half-adders 34,35,36 and 37 and simultaneously to the decoder 107 (FIG.2A). The output of this decoder 107 selects one electrode of the display element for the first place of minute in the display 108. The aforementioned pulse generated from the standrad pulse generator 101 produces output 0 at the output terminal 103g for the first place of minute in the decoder 103 through the frequency divider 102 and then selects another electrode of a display element for the first place of minute in the display 108 through inverters 87,97. Thus a voltage is applied between the aforesaid one electrode and another electrode of the display element, lighting up 2. After lOus elapse, the standard pulse generator 101 generates a pulse, shifting the contents of the shift registers 30,31,32 and 33 which causes a resultant output to be generated for the th place of a minute, and exactly in the same manner as mentioned above, the display element electrode for the 10th place of a minute in the display 108 is selected. Simultaneously, another electrode of the aforesaid display element is selected by a pulse from the output terminal l03h of the decoder 103, thus the 10th place of a minute or O in this example is displayed. At every 1011.5, the lighting positions of the display elements are to be changed and respective elements are lighted in a lOOus cycle. Though lighting is intermittent, it looks as if it were to keep lighting continuously because the lighting cycle is l00us or within the scope of after image to the eyes.

THE CARRY OPERATION Next, the carry operation of each time is explained. Reference is made to a case in which the time now becomes 23 hours 59 minutes 59 seconds 9999 or the case in which the memory contents of the shift registers 30,31,32 and 33 are shown in FIG. 3. If the standard pulse generator 101 generates a pulse then, the storage contents of the shift registers 30,31,32 and 33 are shifted to the right by one shift, and the contents (l,0,0,1) of the storage positions (A, ,B ,C ,D are supplied to the input terminals 34b,35b,36b and 37b of the half-adders 34,35,36 and 37. Synchronous with this, the outputs l, l of the shift registers 30,33 are supplied to the AND gate 61 (FIG. 2A).

Since another input terminal 61a of the AND gate 61 is to be supplied with 1 from the output 103a of the decoder 103 through the inverter 80, the output terminal 61b of the AND gate 61 will become 1. Then this is applied to the input terminals 34b,35b,36b and 37b of the half-adders 34,35,36 and 37 through OR gates39, 40, 41, and 42. In addition, the output of the OR gate 46 is applied to the half-adder 34 through the OR gate 43. The two input terminals 34a,34b of the half-adder 34 become 1, producing 0 at the output 340, which is then stored at the storage position A of the shift register 30 through the AND gate 52. A carry output 1 is generated from the terminal 34d and applied to the terminal 350 of the half-adder 35. As the terminal 35b is being supplied with 1, the terminal 350 of the half-adder 35 is 0, which is then stored at the storage position B, of the shift register 31 through the AND gate 53. The carry output l at the carry terminal 35d is supplied to the input terminal 36a of the half-adder 36. In the same manner as described above, outputs at the output terminals 36c,37c of half-adders 36,37 become 0, and O is stored in the storage positions CD of shift registers 32, 33 through AND gates 54,55. As a result, the storage positions (A,,B,,C,,D,) will be (0,0,0,0). Then the carry output 1 of the output terminal 37d of the halfadder 37 is stored in the flip-flop 38.

When counting the time of 100;.ts is completed, in this way, the contents 1,0,0,l of time in the first place of a millisecond are stored at the storage positions (A, ,B, ,C, D Upon supply of a pulse from the standard pulse generator 101, the contents of the shift registers 30,31,32 and 33 are shifted to the right by one shift. Therefore, the input terminals 34 ,37, of half-- adders 34,37 become 1 while the input terminals 35 ,36 of half-adders 35,36 become 0.

The pulse generated from the standard pulse generator 101 is also supplied to the flip-flop 38 (FIG. 2A), and the carry output 1 of a previously stored place of time is taken out from the terminal 38,. One of the outputs thus taken out is supplied to the input terminal 34, I

of the half-adder 34 through the OR gate 43, and another one is supplied to the AND gate 60. A 0 at the terminal l03b for the first place of millisecond in the decoder 103 (FIG. 2B) makes the input terminal 60 of the AND gate 60 l through the NOR gate (FIG. 2A). And since the outputs 1, 1 of shift registers 30,33 are being supplied to the AND gate 60, the output 1 is to be generated from the AND gate 60 and supplied to the OR gate 47.

After the output 1 is transmitted through the OR gate 46, the one is supplied through OR gates 39,40,41 and 42 to the input terminals 34 ,35,,,36 and 37,, of the half-adders 34,35 and 36. The other is supplied through the OR gate 43 to the input terminal 34,, of the halfadder 34. This condition is exactly the same as the case in which the time of lOOps is added as mentioned above and (0,0,0,0) is stored at the storage positions (A,,B,,C,,D,). And a carry signal of the half-adder 37 is stored in the flip-flop 38. Similarly, when given pulses from the standard pulse generator 101, the contents of the shift registers 30,31,32 and 33 are shifted to the right by each shift, and at the same time addition is made by the half-adders 34,35,36 and 37 performing counting time relating to the first place, 10th place and 100th place of millisecond, and the first place of second entirely in the same way as mentioned above.

Next suppose the contents of 10th place of second (1,0,1 ,0) is stored at the storage positions (A, ,B ,C ,D The flip-flop 38 then has a stored carry signal of the first place of the previous time second. If a pulse from the standard pulse generator 101 shifts the contents of the shift registers 30,31,32 and 33 to the right by one place, outputs l, 1 from shift registers 30,32 will make the two input terminals 58 ,58 of the AND gate 58 1. On the other hand, the output of the standard pulse generator 101 takes out the carry signal of the previous time memorized in the flip-flop 38, thus making the terminal 58,, of the AND gate 58 to be I. The rest terminal of the AND gate 58 is supplied 1 from the decoder 103 (FIG.2B) through the NOR gate 74 (FIG. 2A.). The AND gate 58 then produces the output 1. The output 1 is transmitted through OR gates 45,46 and the one is supplied to the input terminal 34,, of the half-adder 34 through the OR gate 43. The other is supplied to the input terminals 34,,35,,,36, and 37,, through the OR gates 39,40,41 and 43. Accordingly, O is generated from the output terminal 34 and stored at the storage position A, of the shift register 30.

From the carry terminal 34 a carry output 1 is produced and supplied to the input terminal 35,, of the half-adder 35. Similarly as described above, 0 is generated at this output terminal 35 and a carry output 1 at carry terminal 35, In this way 0 is stored at the storage position 13, of the shift register 31. And so 0 is stored at the storage positions C,D and carry output 1 of the half-adder 37 is stored in the flip-flop 38. The first place and the th place of minute can be counted exactly in the same manner.

Next, an explanation is given relating to the counting time on the first place and the 10th place of an hour.

As mentioned above, suppose a carry signal of the 10th place of a minute is stored in the flip-flop 38, and the contents l, l ,0,0) of the first place of hour is stored at the storage positions (A, ,B ,C ,D, of the shift registers 30,31,32 and 33. If a pulse is then generated from the standard pulse generator 101, the contents of the shift registers 30,31,32 and 33 are shifted to the right by one shift, thus an output (l,l,0,0) of the first place of hour is generated. The output 1 of shift registers 30, 31 is supplied to the input terminal of AND gate 62. Consequently, the output I of the AND gate 62 is generated and supplied to the AND gate 66. An output of the storage position 13, of the shift register 31 is taken out at the input terminal 66,, of the AND gate 66. Accordingly, the contents of the 10th place of hour are (0,1,0,()) and so I is stored at the storage position B and this is supplied to the input terminal 66,, of the AND gate 65.

Moreover, the output pulse of the standard pulse generator 101 takes out the carry signal of a minute stored in the flip-flop 38 and supplies it to the input terminal 66,, of the AND gate 66. And 0 for the first place of an hour which produces at the output terminal 103] of the decoder 103 is inverted to 1 through the inverter 78 (FIG. 2A). The l is supplied to the terminal 66 of the AND gate 66. Since full inputs of the AND gate 66 maintain l in this way, 1 is produced at the output terminal 66,. This is supplied, one through OR gates 49,46

to the input 34,, of the half-adder 34, and another through the OR gate 43 to the input terminal 34,, of the half-adder 34. Therefore, it is added to l of the input terminal 34,, and it produces 0 at the output terminal 34, and a carry output 1 at the carry terminal 34,. Carry outputs 1 are generated in turn at the output terminals 35 ,36 of half-adders 35,36, and a carry output 1 at the output terminal 37,, of the half-adder 37 is stored in the flip-flop 38. And outputs 0 at the output terminals 34 ,35,,,36 and 37 of the half-adders 34,35,36 and 37 are supplied to the storage positions (A ,B,C,,D,) of the shift registers 30,31,32 and 33 where (0,0,0,0) is stored.

OPERATION OF INITIAL ERROR PREVENTIVE MEANS The operation of the initial error preventive means is now explained. It is often likely to occur that a number more than 10 in decimal notation is stored in the shift registers 30,31,32 and 33 due to noise at the time of the closing of the circuit to a power supply. This could be displayed as an unidentified error. In order to prevent such a false operation, the device is arranged to perform a reset action when the storage contents of the shift registers 30,31,32 and 33 happen to be more than 10. To give an example, suppose 12 or (0,0,l,l) is stored at the storage positions (A, ,B, ,C, ,D If these contents are shifted to the right, 1 at the storage position C maintains the input of the AND gate 59 1 through the OR gate 48, and l at the storage position C also maintains the other input of the AND gate 58 l. The other input of the AND gate 59 is maintained 1 through the NOR gate l, and therefore, the output of the AND gate 59 becomes l. The output 1 is transmitted through OR gates 47,46, one makes the inputs 34 ,35 ,36 and 37,, of the half-adders 34,35 36 and 37 to be 1. Since another is supplied to the input terminal 34, of the half-adder 34 through the OR gate 43, all outputs at the output terminals 34 35 36, and 37 of the half-adders 34,35,36 and 37 become 0, and (0,0,0,0) is stored at the storage positions (A,,B ,C ,D,) of shift registers 30,31,32 and 33 and a reset is performed.

The 24 hours display has been discussed above. But by addition of suitable circuits having similar construction, date and week day can also be displayed using 24 hours carry signals. For instance, only if the storage capacity of the shift registers 30,31,32 and 33 is increased by two bits and if the carry control circuits for the number 28,29,30 and 31 is adapted, the counting time corresponding to the date is achieved.

RESET OPERATION Then an explanation is made in regard to the reset operation of counting time contents. The reset mechanism of this invention has features of selective opera tion. As an example, the reset action for the place of lOOus will be explained. First, the contact 112, for selecting a timing pulse is connected to the contact point 112,, of IOOus. Then, the contact 109 of the reset switch 109 is connected to the contact point 109,, the input terminal of the NAND gate 70 ismaintained 0. Unless the carry output of ps is supplied, the output of the NAND gate 69 is kept 1, that is, the input terminals 52,53,54, and 55,, of AND gates 52,53,54 and 55 are maintained as 1. However, when after the place output 0 of 100ps of the decoder 103 is inverted to l through the inverter 80, the l is supplied to the input of the NAND gate 69, the output is maintained 0, and

input terminals 52 ,53,,,54 and 55,, of AND gates 52,53,54 and 55 become 0. In the meantime, the shift registers 30,31,32 and 33 are supplied with a shift pulse, and lOOus contents are then shifted and applied to the inputs of the half-adders 34,35,36 and 37. In consequence, if l is generated at either of the output terminals 34 ,35 ,36 and 37 of the half-adders 34,35,36 and 37, as the output terminals of AND gates 52,53,54 and 55 are maintained 0, and as a result, (0,0,0,0) are stored at the storage positions (A ,B,,C ,D,). Reset operation is completed in this way. After resetting is completed, the contact 109 of the reset switch 109 is connected to the contact point 109,, and the counting time start switch 111 set at the start side; the time after being corrected can be counted. The selection of the time of a unit place is as above described, but by providing a proper select switch to-select suitable terminals connected tothe contact points ll2,,,ll2,....l12,,. of the rotary switch 112, simultaneously, the time of a plurality of places can be automatically reset.

To cite an example, in case the first place and the 10th place of second and the first place and 10th place ofa minute are reset, the contact points 112,,1 12 ,112, and 112, of the rotary switch 112 are selected at the same time. Accordingly, every time the output is generated from respective output terminals 103 ,l03,,,103,, and 103; of the decoder 103, the outputs of AND gates 52,53,54 and 55 will become 0 as explained in the above-mentioned lOOus reset operation. Therefore, the storage contents of each time of the shift registers 30,31,32 and 33 are reset to 0. To reset all times, therefore, one must connect the output terminals of all times to a contact and exactly in the same manner as described above, all storage contents of registers 30,31,32 and 33 will be 0, and all places of time can be reset.

TIME ADJUSTMENT How to adjust the time is now explained. At first, select the time of place to be advanced with the rotary switch 112. Now, the following example is a case the time of 100us is advanced hereafter. The contact 112, of the rotary switch 112 is connected to the contact point 112,, and the contact 110, of the time advance switch 110 is changed to the contact point 110,, at the adjust side. Through this change-over, the output of the NAND gate 72 is inverted from 1 to 0. Accordingly, an output Q of the flip-flop 106 inverts from O to l, and the input 67,, of the AND gate 66 is maintained 1. Then if 0 is generated from the output terminal 103,, of the decoder 103, it is inverted to 1 through the inverter 80, and the other input terminal 67,, of the AND gate 67 is kept 1 through the rotary switch 112. As a result, the output of the AND gate 67 becomes 1, which is then supplied to the input terminal 34,, of the half-adder 34 through the OR gate 42.

On the other hand, when the above-mentioned 0 is produced from the output terminal 103. of the decoder 103, the time of l00p.s place at the storage positions (A, ,B ,C, ,D is shifted to the right by one shift and then supplied to the half-adders 34,35,36 and 37 through OR gates 39,40,41 and 42. It is added to 1 supplied at the input terminal 34,, of the half-adder 34, and the added product is then stored at the shift register 30. Since it is also shifted by the output pulse from the standard pulse generator 101, its output or time of lOOus place is supplied to the input terminal 34,, of the halfadder 34 and counted by addition.

The flip-flop 106 is reset by the output of the flip-flop inverted by the output pulse of the AND gate 67 or a building up of a lOOps time signal pulse.

The above explanation is given relative to the advance drive operation of a place of lOOus. This is the same as any other time. For example if the movable contact 112 of the rotary switch 112 is connected to the output contact point 112 for the first place of a minute, 1 is supplied to the input terminal 67,, of the AND gate 67 through the rotary switch 112 when the decoder 103'produes an output for the first place of a minute. The contact 110, of the time advance switch being connected to the contact point 110,, the output level of the NAND gate 71 becomes 0, and consequently, as l is generated at the output of the flip-flop 106, a pulse of the first place of a minute is generated at the output of the AND gate 67. Accordingly, it is supplied to the input terminal 34,, of the half-adder 34 through the OR gate 42, and added to the contents of the first place of a minute shifted from the shift register 30, and the added content is stored in the shift register 30. When the carry is generated it is stored in the shift registers 31,32 and 33 in order as mentioned above in detail.

In the above-described embodiment, counting time outputs are supplied to the carry control means, the initial error preventive means and the display means from the output terminals of the shift registers 30,31,32 and 33, but they are not always limited to these. For example, it is permissible that outputs taken from a suitable position between the half-adders 34,35,316 and 37 and the inputs of the shift registers 31,32,32 and 33 are supplied to the above-said means.

This kind of connection has an advantage in that the counting results can be directly displayed at the display means. Moreover, in the above embodiment halfadders are used as the adder means. However, except for OR gates 39,40,41 and 42, there may be full adders composed of three adder inputs. In the above embodiment, addition is made using four bits outputs of respective registers which are connected in parallel. But it may be arranged as follows: with all places of time stored in one register, the contents of the register are supplied by each one place to the input of one adder provided and after than, addition is made by the same construction as the above embodiment.

The device according to the invention can also be used as a stop watch.

What I claim and desire to secure by Letters Patent 1. An electronic time-keeping apparatus comprising, means generating pulsedcounting signals for a time count, register means storing the counting signals, adder means developing from the counting signals of said register means a time count output and developing carry signals corresponding to higher order places in the time count, carry signal memory register means temporarily storing said carry signals, carry signal controlled means controlling application of the carry signals to said adder means, display means displaying an indication of the time corresponding to said time count, and time-advancing means developing signals under manual control applied to said adder means for varying the stored contents of said register means received by said adder means to advance the time count output of said adder means to correspond to a desired time in advance of the time indicated at said display means.

2. An electronic time-keeping apparatus comprising, means generating pulsed counting signals for a time count, register means storing the counting signals, adder means developing from the counting signals of said register means a time count output and developing carry signals corresponding to higher order places in the time count, carry signal memory register means temporarily storing said carry signals, carry signal controlled means to receive the temporarily stored carry signals and apply them to said adder means to develop output signals corresponding to said time count output and representative of said higher order places of said time count, clock pulse generating means generating timing clock pulses applied to said carry signal controlled means controlling application of the carry signals to said adder means, display means displaying an indication of the time corresponding to said time count, and error preventive means automatically detecting initial errors in the stored counting signal content of said register means and developing signals applied to said adder means for varying in response to the detection of said errors the stored contents of said register means received by said adder means to correctly effect said time count.

3. An electronic time-keeping apparatus comprising, means generating pulsed counting signals for a time count, register means storing the counting signals, adder means developing from the counting signals of said register means a time count output and developing carry signals corresponding to higher order places in the time count, carry signal memory register means temporarily storing said carry signals, carry signal controlled means to receive the temporarily stored carry signals and apply them to said adder means to develop output signals corresponding to said-time count output and representative of said higher order places of said time count, clock pulse generating means generating timing clock pulses applied to said carry signal controlled means controlling application of the carry signals to said adder means, display means displaying an indication of the time corresponding to said time count, and start switch means for controlling the start of a time count, and error preventive means automatically detecting errors in the counting signal content of said register means developed at the start of a time count and correcting the time count output of said adder means to correctly effect said indication of time.

4. An electronic time-keeping apparatus comprising, means generating pulsed counting signals for a time count, register means storing the counting signals, adder means developing from the counting signals of said register means a time count output and developing carry signals corresponding to higher order places in the time count, carry signal memory register means temporarily storing said carry signals, carry signal controlled means connected to receive the temporarily stored carry signals and apply them to said adder means to develop output signals representative of said higher order places of said time count, time-advancing means for developing signals applied to said adder means varying the stored contents of said register means received by said adder means to advance the time count to correspond to an advanced time, error preventive means detecting errors in the stored counting signal content of said register means and developing signals applied to said adder means varying the stored contents of said register means received by said adder means upon detection of said error to correctly make said time count, clock pulse generating means generating clock pulses applied to said carry signal controlled means controlling application of the carry signals to said adder means, and display means receptive of the time count output and displaying an indication of the time corresponding to said time count.

5. An electronic time-keeping apparatus comprising: pulse generating means for developing a plurality of timing pulses and clock pulses; register means for storing and reading out a plurality of words of time data in synchronization with the clock pulses, adder means responsive to a given timing pulse of the timing pulses for incrementing the time data applied thereto from said register means and for applying the incremented time data to said register means; carry signal memory register means for temporarily storing a carry output from said adder means and coactive with said adder means to effect an increment in the time data of a higher order word of the time data in synchronization with the clock pulses, carry signal controlled means successively receptive of the words of time data, said timing pulses and the carry output of each word stored in said carry signal memory register, for controlling the coaction of said adder means and said carry signal memory register means to increment the time data in a higher order word of time data; and display means for displaying the words of time data.

6. An electronic time-keeping apparatus according to claim 5, including time-advancing means developing signals under manual control applied to said adder means for varying the stored time data of said register means received by said adder means to advance the time data output of said adder means to correspond to a desired time in advance of the time indicated at said display means 7. An electronic time-keeping apparatus according to claim 5, including error preventive means automatically detecting initial erroneous time data stored in said register means and developing signals applied to said adder means for varying in response to the detection of said erroneous time data the stored contents of said register means received by said adder means to correctly effect the time data.

8. An electronic time-keeping apparatus according to claim 5, including reset means to reset at will the time data of a selected word in said register means to a desired time data, thereby to indicate a reset time indication on said display means.

9. An electronic time-keeping apparatus according to claim 5, including start switch means for controlling the start of a time count, and error preventive means automatically detecting erroneous time data stored in said register means developed at the start of a time count and correcting the time data output of said adder means to correctly effect said indication of time.

10. An electronic time-keeping apparatus comprising: pulse generating means for developing a plurality of timing pulses and clock pulses; register means for storing and reading out a plurality of words of time data in synchronization with the clock pulses adder means responsive to a given timing pulse of the timing pulses for incrementing the time data applied thereto from said register means and for applying the incremented time data to said register means; carry signal memory register means temporarily storing a carry output from said adder means and coactive with said adder means to effect an increment in the time data of a higher order word of the time data in synchronization with the clock pulses; carry signal controlled means successively receptive of the words of the time data, and timing pulses and the carry output of each word of the time data stored in said carry signal memory register means for controlling the coaction of said adder means and said carry signal memory register means to increment the time data in a higher order word of time data; time advancing means for developing signals applied to said adders to vary the stored contents of said register means received by said adders to advance the time data to correspond to an advanced time; error preventive means'for detecting an error in the contents of any word stored in said register means and for developing signals applied to said adders to vary stored contents of that word in said register means received by said adders upon detection of said error and to correct the contents of that word; and display means receptive of the time data output words for displaying an indication of the time corresponding to said time data.

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Classifications
U.S. Classification708/684, 968/904, 968/903, 968/916, 377/20, 377/129
International ClassificationG04G3/02, G04G3/00, G04G5/00, G04G5/04
Cooperative ClassificationG04G3/025, G04G3/022, G04G5/043
European ClassificationG04G3/02D, G04G3/02B, G04G5/04C