US 3800177 A
There is disclosed an integral light display comprising a matrix of light emitting diodes in an integral structure which is scannable to produce an alpha numeric character display. The light emitting diodes are arranged in a plurality of rows and columns with the anodes of each diode connected by row address lines and the cathodes of each column being common, so as to be connectable to column address lines. A strobing format logic address system is provided for lighting the individual diodes to emission for producing an alpha numeric character or graphic display. The integral structure includes the transparent faceplate for the finished packaged device.
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Description (OCR text may contain errors)
United States Patent 1191 Russ 1,Mar. 26, 1974 INTEGRATED LIGHT EMITTING DIODE DISPLAY DEVICE WITH HOUSING  Inventor: Malcolm J. Russ, Scottsdale, Ariz.
 Assignee: Motorola, Inc., Franklin Park, Ill.
 Filed: Dec. 20, 1971 211 Appl. No.: 209,838
 U.S. Cl. 313/108 D, 313/324  Int. Cl. H051) 33/02  Field of Search 313/108 D, 324; 315/169 TV  References Cited UNITED STATES PATENTS 3,558,974 1/1971 Stewart 315/169 TV 3,631,285 12/1971 Laisi et al..... 313/108 3,641,390 2/1972 Nakamura 313/108 D X 3,330,982 7/1967 Dickson, Jr... 315/169 TV X 3,501,676 3/1970 Adler et al. 315/169 TV 3,290,539 12/1966 Lamorte 313/108 DV X Primary Examiner-Palmer C. Demeo Attorney, Agent, or Firm-Vincent J. Rauner; Henry T. Olsen  ABSTRACT There is disclosed an integral light display comprising a matrix of light emitting diodes in an integral structure which is scannable to produce an alpha numeric character display. The light emitting diodes are arranged in a plurality of rows and columns with the anodes of each diode connected by row address lines and the cathodes of each column being common, so as to be connectable to column address lines. A strobing format logic address system is provided for lighting the individual diodes to emission for producing an alpha numeric character or graphic display. The integral structure includes the transparent faceplate for the finished packaged device.
There is also disclosed a method of making the foregoing integrated light display, which includes the steps of forming the anodes of the light emitting diodes in a semiconductor substrate of a type opposite to that forming the conductivity of the anodes, preferably by diffusion. Anode connecting row address lines are then formed interconnecting rows of anodes, the contacts to the anodes being of annular form to provide an opening for the light emitting from the junction of the light emitting diode. After transparent faceplate is secured over the surface of the substrate and the row address lines, the substrate is then etched into a plurality of sections to separate the cathodes of the light emitting diodes into a plurality of columns. The backside of the substrate may be thinned prior to separation into the column lines to provide better electrical connection to the cathodes of the light emitting diodes. The package of the light emitting diode array is completed by securing the faceplate of the array into a suitable housing.
5 Claims, 9 Drawing Figures 2/ uzuzalj PMENIEMnzs m4 sum 2 or 2 BACKGROUND OF THE INVENTION This invention relates to alpha numeric displays and more particularly to an integral light emitting diode diplay. Still more particularly, the invention is related to a light emitting diode display which is scannably addressable.
Visual readout devices such as alpha numeric displays are available in several formats utilizing various light emitting devices such as incandescent lamps, gaseous discharge lamps, electroluminescent arrays and more recently light emitting diode arrays. Such devices are utilized for many purposes such as computer readouts, process control instrumentation, aircraft and automotive instrument panels, and various other indicators such as clocks and gauges. Since most, if not all of the aforementioned uses rely on semiconductor electronics, it is highly desirable that the alpha numeric display be compatible with the voltages and currents normally utilized in such semiconductor circuits and be compatible with its speed of operation. A major objection to the presently most widely used visual readout, the gaseous discharge lamp of the cathode glow variety is the high voltage required for initiating the glow discharge. Such readouts require the use of interface semiconductors having high reverse voltage breakdown characteristics. Obviously, the light emitting diode array format, being itself a semiconductor device, is highly desirable for a visual readout since it is inherently compatible with the electronics of the semiconductor circuits.
Some attempts have been made to provide alpha numeric displays utilizing light emitting diodes in either discrete, hybrid, or individually addressable diode bit arrays. In these formats, light emitting diode arrays have not been widely acceptable as they are costly, unreliable and relatively inconvenient to adapt to standard systems.
SUMMARY OF THE INVENTION It is a primary object of this invention to provide an integrally manufactured light emitting diode alpha numeric display device and method.
A further object of the invention is to provide an integral light emitting diode alpha numeric display which is relatively economic and compatible with standard systems.
In accordance with the aforementioned objects, there is provided a monolithic light display comprising a matrix of light emitting diodes in an integral structure formed on a transparent faceplate, said light emitting diodes being arranged in columns and rows, a first layer of metallization contacting the anodes of all of said light emitting diodes in each of the plurality of rows, said metallization having holes formed therein to permit the emission of light through said rows of metallization, and a column address metallization for contacting each of the cathodes of the plurality of columns of said diodes.
THE DRAWINGS Further objects and advantages of the invention will be obvious to one skilled in the art from the following complete description thereof and from the drawings wherein:
FIG. 1 is a plan view of an integral light emitting diode array in accordance with the preferred embodiment of the invention, depicted somewhat schematically;
FIGS. 2 & 3 are cross sectional views of FIG. 1, taken on lines 2 2 and 3-3 respectively; and
FIGS. 49 are cross sectional views depicting schematically successive stages in the manufacture of the light emitting diode array.
DETAILED DESCRIPTION While the following preferred embodiment of the invention is disclosed with particular reference to a monolithic array of gallium arsenide phosphide light emitting diodes, it will be appreciated that any optimum light emitting diode material such as gallium arsenide or gallium phosphide may be used. The transparent carrier substrate for the array may be of any suitable material having a sufficient transparency to the wavelength of light to be emitted.
Since one of the current limiting values for a light emitting diode and hence light output, will be based on the heat or power dissipation characteristics of the substrate to which it is attached, it may be preferable to use a relatively high thermal conductivity glassy material.
In accordance with the preferred embodiment of the invention as shown in FIG. 1, the light emitting diode array comprises a plurality of light emitting diodes 18 arranged in an integral support structure 19 in an orthogonal matrix of rows and columns. As shown, the matrix comprises five light emitting diodes in each row and seven light emitting diodes in each column, for a total of 35 light emitting diodes 21, comprising the array. Contacts B1437 are provided making contact with the anodes of each of the rows of the light emitting diodes and contacts C1-C5 are provided for contacting the cathodes of the light emitting diodes in each column. Thus, a suitable strobing or scanning type logic can individually address the light emitting diodes to cause each to emit light in a suitable alpha numeric, or graphic display, pattern. The pattern indicated by the aura around various of the light emitting diodes being depicted as indicating the numeral 4. Each column is addressed during a particular clock pulse of the logic and suitable of the light emitting diodes will be switched to emit light by addressing the desired anode through the row contacts. The crossing conductive paths comprising the column contacts C1-C5 and row contacts Bl-B7 will be explained hereinafter in greater detail.
The integral support structure 19 includes a transparent faceplate 20 to the backside of which is secured columns of common cathode light emitting diodes 21 to 25, by means of a transparent bonding layer 26. The anodes 27 (FIG. 3) of each of the diodes are regularly spaced within each column 21 to 25 (FIG. 2). The anodes of each row 81-87 are connected together by a metallization layer 28 extending across all of the columns intermediate the columns and the transparent faceplate 20. Each of the columns 21 to 25 is connected to contacts Cl-CS by leads 29, and each of the row metallizations 28 is connected to the row contacts Bl-B7 by leads 30. The entire array 19 is enclosed by a suitable housing 31 which includes a plurality of column contacting terminals 32 and a plurality of row contacting terminals 33. Each of the row address lines 28 have annular openings 34 therein (which are filled by the adhesive transparent layer 26) to permit light from the junction of each of the light emitting diodes 18 to be emitting through the transparent faceplate 20.
The successive steps in the manufacture of the light emitting diode array is depicted in FIGS. 4-9, which method has for its purpose obtaining relative electric isolation between the individual diodes 18, while interconnecting them in columns and rows which are scannably addressable in a unitary structure, which may be readily packaged. As shown in FIG. 4, a substrate 40 of monocrystalline semiconductor material, preferably N-type gallium arsenide phosphide, is provided with suitably spaced P-conductivity regions 41, thereby forming a plurality of PN junctions 42 defining light emitting diodes 18. These P-type regions are produced by suitable photolithographic techniques in which the P-regions are preferably formed by diffusion, although suitable epitaxial techniques might be utilized as well. The entire surface of the substrate with the P- conductivity regions 41 arranged in a orthogonal matrix therein is then covered by a suitably transparent dielectric layer 43. By utilization of a suitable photomasking technique, annular openings 44 are opened through the dielectric layer 43 over each of the P- regions 41, and a layer 45 of vapor deposited metal placed over the entire surface of the substrate. Row connectors 28 are then formed from the metallization layer 45 by etching away the metal between the rows. Preferably, simultaneously with the etching of the metal from between the row address lines 28, circular openings 46 are defined within the row address lines 28 to permit emission of lights from the junction 42 of the light emitting diodes 18.
Thus it will be noted that there is formed an annular contact 47 between the row address line 28 and the P- regions 41 with the generally circular openings 46 permitting emission of light from the junction 42 of the diodes through the dielectric layer 43 (FIGS. 5 and 6).
Following forming of the row address lines 28, the transparent faceplate 20, having metallized contacts C1-C5 and Bl-B7 arranged about its periphery, is then secured to the surface of the substrate by a suitable transparent adhesive layer 26. The adhesive layer 26 serves to fill the circular openings 46 in the row contact 28 and also the spacing between the row contacts. Since the matrix of diodes is now suitably secured in an integral or unitary structure with the faceplate 20, the substrate 40 may be partially removed to a lapline LL if it is desired to lower the voltage drop of the cathode regions of the diodes. In any case, following a suitable photomask step, moats 48 are etched through the substrate to the dielectric layer 43 to divide the substrate into the plurality of common cathode column members 21-25. It is to be noted that when the transparent faceplate with the metallized contact members Bl-B7 and Cl-CS is secured to the surface of the substrate 40, electrical contact between the row metallization 28 and the contacts Bl-B7 will be made. However, if it is desired, the metallization 28 may be exposed by suitable etching steps and contact lead members utilized to connect the row with its respective contact. Following division of the substrate into the plurality of columns, a suitable metallization layer 50 may be placed over the major surface of the columns to form electrical connection between the cathodes of the columns and the cathode contacts Cl-CS (FIG. 9), thereby eliminating the need for separate leads 29 and providing lower resistance connection to the individual cathodes. The integral structure 19 including faceplate 20 with the matrix of diodes 21 thereon may then be sealed into the housing 31 with the contacts 81-87 and Cl-C5 aligned with respective terminals 32 and 33 to make electrical contact therewith.
While the invention has been disclosed by way of the preferred embodiment thereof, it will be obvious to one skilled in the art that suitable modifications may be made therein without departing from the spirit and scope of the invention. For example, should it be desirable to diffuse the N-type regions rather than the P- type regions the cathodes would be uppermost rather than the anodes. Also, the aperatures through the metallization could be rectangular rather than circular and the metallization plated for better strength so that the columns separated by sawing rather than etching.
What is claimed is:
1. An integrated light display comprising a matrix of light emitting diodes in an integral structure which is scannable to produce an alpha numeric character display, said light emitting diodes being arranged in a plurality of rows and columns with a first electrode of each diode being connected by row address lines and the other electrode of each diode being connected by column address lines;
a transparent faceplate of dielectric material having a first group of metalized row contacts along one edge thereof and a second group of metalized column contacts along a second edge;
means for securing said matrix to said transparent faceplate;
means for electrically connecting each row address line to a metalized row contact at the periphery of the faceplate;
means for electrically connecting each column address line to a metalized column contact at the periphery of the faceplate;
a housing having a first and second group of terminals secured therein; and
means for securing said housing to said faceplate with said first and second group of terminals in electrical contact with said first and second group of metalized contacts.
2. An integrated light display as recited in claim 1 wherein said row address lines are between said light emitting diodes and said dielectric plate and said column address lines are located on the area of said diodes away from said dielectric face-plate.
3. An integrated light display as recited in claim 1 wherein said light emitting diodes are of a material selected from the group consisting of gallium arsenide, gallium arsenide phosphide and gallium phosphide.
4. An integrated light display as recited in claim 1 wherein said rows and columns are arranged orthogonally.
5. An integrated light display as recited in claim 1 wherein said row address lines are located intermediate said light emitting diodes and said dielectric face-plate, said row address lines being arranged with circular openings therein to permit light emitted from the junctions of the light emitting diodes to be transmitted through said row address lines.