Publication number | US3801955 A |

Publication type | Grant |

Publication date | Apr 2, 1974 |

Filing date | Dec 13, 1971 |

Priority date | Dec 13, 1971 |

Publication number | US 3801955 A, US 3801955A, US-A-3801955, US3801955 A, US3801955A |

Inventors | Howell T |

Original Assignee | Honeywell Inf Systems |

Export Citation | BiBTeX, EndNote, RefMan |

Referenced by (14), Classifications (5) | |

External Links: USPTO, USPTO Assignment, Espacenet | |

US 3801955 A

Abstract available in

Claims available in

Description (OCR text may contain errors)

United States Patent [1 1 I [111 3,801,955

Howell I [4 1 Apr. 2, 1974 CYCLIC CODE ENCODER/DECODER Primary Examiner-Charles E. Atkins on V [75] Inventor: Thomas Harold Howell, Attorney, Agent, F d Hughes and Scottsdale, Ariz. X: YY,Nic S M 1 ,1 by

[73] Assignee: Honeywell Information Systems [57] ABSTRACT Waltham, Mass- A cyclic code decoder is provided which has a feedg back shift register organized in two sections which to- [22] Filed: Dec. 13, 1971 gether form a cyclic code encoder. The first section [21] pp No 207 209 has a gated feedback connection in accordance with tively connected in series with the first section and has [52] U.S. Cl. 340/1461 AL, 340/ 146.1 AV gated feedback connections for the polynomial P (x). [51] Int. Cl. G06f 11/12 Addition l fe connections are pr i f r h [58] Field of Search ..'340/146.l AL, 146.1 AV first section, in accordance with the polynomial P (x) and these feedback connections are selectively con- [56] References Cited nected in series with the feedback to the second sec- UN STATES PATENTS tion of the shift register. A zero detector; comparator and counter are provided for error detection and iden- 3,159,s10 12 1964 Fire 340 1461 AL d l 1 3,512,150 5 1970 Ohnsorge 340 1461 AL ficamm as facmfe Po ynomla' 3,582,881 6/1971 Burton 340/146.1 AL 5 Chims, 5 Drawing Figures BUFFER REGISTER EG'TE W INPUT2 k 1 36 QZQTEFT LZERO DETECTOR the polynomial x 1. The second section is selec- PATENTEB APR 2 i974 SHEEIZBFZ 1 REGISTER COUNTER INPUT COMPARATOR ZERO DETECTOR CYCLIC CODE ENCODER/DECODER FIELD OF THE INVENTION This invention relates to the field of error correction and detection. In particular, it is concerned with faster error identification with the encoding and decoding of binary information, using cyclic codes.

DESCRIPTION OF THE PRIOR ART been of primary interest. Particularly where burst errors have been a major concern, Fire codes, defined by a polynomial of the form, P(x) P (x) (x l) have been important. (The operator is used to represent modulo 2 addition operation, which is equivalent to the exclusive OR operation, throughout this specification, unless otherwise indicated) Fire codes are normally defined as requiring the polynomial factor P,(x) to be irreducible. For the purpose of this disclosure, cyclic codes, in general, include those codes where P (x) is reducible.

However, with a code word length of n bits, k information bits, nk r check bits, error correction has normally required n operation cycles. This is becoding and decoding at a common site is lost. For example, in a disk peripheral subsystem for a computer, it is obviously desirable to have common hardware for both the encoding and decoding of code words. Accordingly, the object of the invention is to provide an encoder/decoder which has the advantages of the factored decoder and performs the necessary encoder functions.

SUMMARY OF THE INVENTION It has been discovered that for encoding and decod ing devices using cyclic code error correction, it is possible to use substantially the same feedback shift register structure for both encoding the check bits, R(x), and for identifying counts i and 1', indicative of an error location, together with the burst error patternj-This error identification time is approximately (e c 2)/n cause of the standard procedure of buffering a decoded message and if an all zeros syndrome (no error'detected condition) is not detected in the decoder shift register upon receipt of the encoded data, the buffered word is circulated and the shift register is serially shifted with feedback until a correctable error pattern is located. To impose upon a system the requirement that this error correction time be available, between code word transmissions, is a significant constraint.

It has been observed, by W. W. Peterson, Errorcorrecting Codes, M.l.'T. Press, 1961, Chapter 10 for example, that the code polynomial factors can be implemented by respective shift regiser portions. For an encoded word, F(x), F(x)/P (x) O and FOO/(x l) 0 is equivalent to F (x)/P(x) 0. Therefore, a faster error detector can be implemented with simpler hardware. Of greatest importance, is the advantage that when an error is detected, the time required for error identification can be substantially reduced, if desired. If the received code word is stored in a buffer shift register, and a feedback shift register implementing the polynomial P(x) is run in an error pattern identification mode, the number of shift cycles required for error identification is greatly reduced. The factor of improvement is approximately (e c 2)/n, where e is the value of the exponent to which P (x) belongs, e.g., the smallest positive integer such that x l is evenly divided by P(x). The advantages of the factored decoder described by Peterson are discussed in greater detail in the IEEE Transactions on Information Theory, January, 1969, pages 109-113, by R. T. Chien.

However, such va decoder cannot be used for encoding and accordingly the commonality feature inherent in the conventional polynomial implementation is lost'. Also, the capability of using the same hardware for enof the conventional error identification time.

BRIEF DESCRIPTION OF THE DRAWINGS A FIG. 1 is a block diagram of an encoder/decoder primarily showing the feedback connections for encoding for a representative generating polynomial.

FIG. 2 is a block diagram of the FIG. 1 encoder/decoder primarily showing the connections required for decoding.

FIGS. 3-5 are diagrams illustrating operation of the encoder/decoder.

. DETAILED DESCRIPTION OF THE INVENTION FIG. 1 is a serial Fire code decoder/encoder using a feedback shift register for the code polynomial: P(x)=.P,(x) (.x"'+ l)=(ir *+x+ 1) (15 l) =x +x +x +x +x+L Flip-flops 21-28 provide shift register positions and interconnections to mod 2 adder gates 31 -33 and 35-37 provide the desired feedback for the polynomial P(x) in the usual manner. Gate 11, when enabled, permits the generation of the n-k remainder check bits, R(x), by the feedback shift register during transmission, while the k information bits also pass through OR gate 16. Gate 12, inhibited during the generation of R(x), is then enabled and R(x) is transmitted through OR gate 16 with the input held at a logical zero. Gate 14, between shift register position 25 and mod 2 gate 36, divides the feedback shift register so that there is effectively a separable section including register positions 26-28. Gate 14 is enabled during encoding and therefore has no effect on transmission. Similarly, gate' 13 partitions the feedback path. Accordingly, gates 13 and 14 are enabled and gates 15 and 17 are inhibited during transmission and therefore have no effect on encoding. With gate 13 placed in the feedback path so that together with gate 14, the feedback shift register can be partitioned, whereby the high order section can be transformed into a decoder for the polynomial P (x) x x 1. Gate 15 is connected between register position 25 and mod 2 gate 32, providing a feedback path for decoding by (x 1). Gate 17 selectively connects the input to a mod 2 gate 34, between register position 23 and mod 2 gate 35, so that the input can be selectively applied to the low order section of the feedback shift register during decoding. A comparator 41, zero detector 42, and buffer shift register 43 are provided for decoding. The connections for these elements are shown in FIG. 2. Gates l3 and 14, are not shown in FIG. 2 because these gates are inhibited during error detection and identification. A counter 45, driven by encoder/decoder clock source 46, is required for fast error identification.

I During decoding, gates l1,.l5,and 17 are enabled so the code word is applied to upper and lower sections of the feedback shift in parallel. The higher order section serves to divide the received word by the polynomial P (x) x x l and the low order section serves to divide by the polynomial x 1. After the received word is checked, if the contents of all the register positions are zero, this composite syndrome indicates that no error was detected. For checking, comparator 14 serves as a zero detector. This zero result in conjunction with a zero detection at zero detector 42 terminates decoding. If the composite error syndrome is non-zero, the error identification procedure is followed. This procedure consists of providing a series of zero inputs to the low order register section via INPUT 2. That is, with gate 15 enabled, the clock shifts the low order section. When the zero detector 42 detects all zeros in register positions 24 and 25, this count is sotred in I register 47 from counter 45. The counter 45 is then cleared and a series of zeros is applied to the high order register section. The series of zeros is then continued until register position 21-23 compare exactly with the contents of the corresponding register positions 26-28, respectively. The contents of counter 45 is then i,,, which together with i determines the location of the error in the codeword. Also, the burst error pattern is now stored in the high order section of the feedback shift register.

The location i of the error pattern isdetermined by the relationship:

i= (ej, .[(nm-i mod 6] (:j [(n-mi,,) mod e1) mod n where j and j, are integers such that:

ej cj, 1 mod n where m is the maximum correctable burst length. For the FIG. 2 decoder, these relationships require: i= (7j,.[(32 i mod 5] Sj, [(32 i,) mod 7]) mod 35 and 7e, e, 1 mod 35. For example, with the composite error syndrome 110 and 01100, i O and-i 1. Also, e 3 e, satisfies the constraint on e, and e,. Therefore,

i= (7(3) [(32 mod +5(3) [(32 1) mod 7]) mod 35 (7(3) [2] 5(3) [3]) mod 35 (42+45) mod 35 17 The error pattern is accordingly:

E(x) x B(x) x" (x x) x x. FIG. 3 is a diagram illustrating the encoding operation of the FIG. 1 encoder/decoder operating as a conventional encoder with gate 11 enabled and gate 12 ini hibited. As the information word, C(x) x +x +x x l is serially transmitted through OR gate 16, the remainder check bits are formed, R(.'x) x x x x 1. After, G(x) is transmitted, gate 11 is inhibited and gate 12 is enabled. R(x) is then transmitted so that the coded word is FIG. 4 is a diagram illustrating the operation of the FIG. 1 encoder/decoder operating in the FIG. 2 configuration. Gates 11, 15 and 17 are enabled; and gates 12, 13 and 14 are inhibited. The received word has the form H(x) F(x) E(x),' where E(x) is an error, x x. The resulting syndrome is 01100110 in register positions 21-28, respectively. Since these are not all zeros, the error has been detected. If a series of zeros are then provided as an input, the error can be determined as illustrated in FIG. 5. If the buffer register 43 was shifted out at the same time, the received word could be corrected by adding the error pattern, mod 2, to the respective bits in the received word. This requires n 35 cycles, during which the device is unavailable for encoding or decoding. In general, it is necessary to provide a counter so that the correction operation will be terminated after n cycles. When an uncorrectable error pattern is received, the comparator 41 and zero detector never achieve the desired zero conditions.

In applications such as computer peripheral subsystems, conventional error correction is obviously undesirable because of the time required and the dedication of a buffer register for the error correction function is a significant cost. If the buffer register function is provided by other hardware, such as a shared read/write memory, there is additional complexity in the data transfer and control logic.

When code words of much greater length are considered, these disadvantages become more evident. For example, with a Fire code polynomial, such P(x) (.r x l) (x l), serious problems are encountered. In using the invention, the primary present interest is in long code words as is common in computer records. For example, with the last polynomial, code words up to 138,196 bits in length can be used, of which 79 bits are check bits. Such a code can correct burst errors up to 11 bits in length and clearly has very high efficiency. It is apparent that dedication of storage means to error correction buffer store is extremely costly. Accordingly, only one or two bytes should be buffered and then transferred to main memory. Where an error is detected, the error identification procedure is then performed and the data, i i, and the error pattern, are transferred to the computer where the error is corrected.

It isunderstood that the above-described encoder/decoder is only illustrative of the application of the principles of the invention. Numerous modifications and alternative arrangements can be devised by those skilled in the an. In particular, the invention is applicable to any feedback shift register encoder/decoder for any Fire code, provided c is greater than m.

What is claimed is:

1. An encoder/decoder for error detection and correction of code words consisting of n signal bits and k information bits, in which the encoding polynomial P(x) can be represented in the factored form P,(x) (x l) and the degree m of polynomial P,(x) is less than 0 comprising:

A. a feedback shift register having feedback connections realizing the Fire code polynomial P(x);

B. gating means connecting portions of said shift register for selectively i. partitioning said register between the x"and 2."

positions,

ii. disconnecting the feedback path beyond the x position of said register,

iii. connecting the output of the xposition to the input of the x position of said register.

2. An encoder/decoder for error detection and correction of code words consisting of in signal bits and k information bits, in which the encoding polynomial -6 P(x) can be represented in the factored form P (x) (x order positions of said register and for subsel) and the degree in of polynomial P (x) is less than quently counting the number of shifts of said high c comprising: a order section to produce an equals comparison for A. a low order feedback shift register section having the first m positions. 7

encoding feedback connections which realize the 5 4. The encoder/decoder of claim 2 further comprispolynomial P,(x); ingz' B. decoding feedback connections, connected tosaid G. a zero detector, connected to every position of low order register section realizing the polynomial said shift register sections, for detecting a zero x l; syndrome upon completion of decoding a code C. a high order feedback shift register section, con- 10 word;

nected in series with said low order section, having H. a counter, clocked in parallel with said shift regisfeedback connections with realize the polynomial ter sections; x P,(x); l. a register, responsive to'said counter, for storing D. encoder gating means interconnecting said registhe count required to shift an all zeros combination ter sections in such a manner as to enable the eninto the c-m most significant positions of said shift coder/decoder to encode k information bit signals register. in accordance with P(x); a 5. An encoder/decoder comprising:

E. decoder gating means interconnecting said first A. a first feedback shift register realizing the polynoand second register sections for selective parallel mial P (x), having degree rn: decoding; B. a second feedback shift register realizing the poly- F. error detecting means, responsive to each stage of nomial at 1, where c is an integer greater than m; said shift register sections for detecting 'a zero state C. first gating means for disconnecting the feedback in all positions of said register sections. of said second shift register;

3. The encoder/decoder of claim 2 further compris- D. second gating means for connecting the feedback ing: of saidfirst feedback register to said second feed- G. said error detecting means including comparator back register in accordance with the polynomial means between said high order register section and P,(x) (x 1) and for connecting the output of the the respective first m positions of said low order high order position of saidsecond shift register to register section; the low order position of said first shift register;

H. error identification means, clocked in parallel E. detection means for detecting an all zeros with .said shift register sections, for counting the syndrome in said shift registers and for comparing number of shifts of said low order section to prothe first In positions of said shift registers. duce an all zeros syndrome in the cm highest

Referenced by

Citing Patent | Filing date | Publication date | Applicant | Title |
---|---|---|---|---|

US4151510 * | Apr 27, 1978 | Apr 24, 1979 | Honeywell Information Systems | Method and apparatus for an efficient error detection and correction system |

US4168486 * | Jun 30, 1978 | Sep 18, 1979 | Burroughs Corporation | Segmented error-correction system |

US4413339 * | Jun 24, 1981 | Nov 1, 1983 | Digital Equipment Corporation | Multiple error detecting and correcting system employing Reed-Solomon codes |

US4698813 * | Apr 29, 1985 | Oct 6, 1987 | Siemens Aktiengesellschaft | Arrangement for correcting burst errors in shortened cyclical block codes |

US5381423 * | Jan 3, 1994 | Jan 10, 1995 | Italtel Societa Italiana Telecomunicazioni S.P.A. | Process and device for the decoding of a shortened, cyclic binary code using error correction |

EP0046963A2 * | Aug 24, 1981 | Mar 10, 1982 | Siemens Aktiengesellschaft | Circuit configuration for the recognition and correction of error bursts |

EP0046963A3 * | Aug 24, 1981 | Jan 5, 1983 | Siemens Aktiengesellschaft | Circuit configuration for the recognition and correction of error bursts |

EP0074627A2 * | Sep 9, 1982 | Mar 23, 1983 | Nec Corporation | Circuit for checking bit errors in a received BCH code succession by the use of primitive and non-primitive polynomials |

EP0074627A3 * | Sep 9, 1982 | Jan 29, 1986 | Nec Corporation | Circuit for checking bit errors in a received bch code succession by the use of primitive and non-primitive polynomials |

EP0159403A2 * | Dec 17, 1984 | Oct 30, 1985 | Siemens Aktiengesellschaft | Arrangement for correcting bundle errors in reduced-cyclic block codes |

EP0159403A3 * | Dec 17, 1984 | Nov 11, 1987 | Siemens Aktiengesellschaft | Arrangement for correcting bundle errors in reduced-cyclic block codes |

EP0200124A2 * | Apr 18, 1986 | Nov 5, 1986 | Hitachi, Ltd. | Decoding method and encoder-decoder for cyclic codes |

EP0200124A3 * | Apr 18, 1986 | Jan 17, 1990 | Hitachi, Ltd. | Decoding method and encoder-decoder for cyclic codes |

WO1991001598A1 * | Jul 18, 1990 | Feb 7, 1991 | Italtel Società Italiana Telecomunicazioni S.P.A. | Process and device for the decoding of a shortened cyclic binary code using error correction |

Classifications

U.S. Classification | 714/762 |

International Classification | H03M13/00, H03M13/17 |

Cooperative Classification | H03M13/17 |

European Classification | H03M13/17 |

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