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Publication numberUS3803556 A
Publication typeGrant
Publication dateApr 9, 1974
Filing dateMay 11, 1971
Priority dateMay 11, 1971
Publication numberUS 3803556 A, US 3803556A, US-A-3803556, US3803556 A, US3803556A
InventorsDuffy T
Original AssigneeConveyor Systems
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Conveyor control system
US 3803556 A
Images(7)
Previous page
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Description  (OCR text may contain errors)

United States Patent 1191 Duffy 1 1 Apr. 9, 1974 54] CONVEYOR CONTROL SYSTEM 3,328,597 6/l967 De Witt et al. 307/40 Inventor: o g L- y ar ty 3,6l0,l59 l/l97l Flckcmicher 340/l72.5

[73] Assignee: Conveyor Systems, Ine., Morton primary Examine, pau| l Hem)" Assistant Examiner-Paul R. Woods [22] Filed: May 11 1971 Attorney, Agent, or Firm-Coffee and Sweeney [211 App]. No.: 142,205

[57] ABSTRACT 52 s CL 340 1715 g 193 33 Individual tote pans which are to be diverted at se- [51] Int. Cl. 606k 17/00 lecled Stations along a conveyor are q y identi- [58] Field of Search 214/11; 209/122; 118/2; fled y a binary address which directly identifies a 2 3 7 40; 340 725 memory core address location. At a dispatch station, data identifying selected divert stations for a particular 5 Rekremes Cited tote pan is stored in a register. The address of that UNITED STATES PATENTS particular tote pan is then scanned and used to di- 3 593 308 7/197] F 340" 5 rectly address the memory core for transfer to core of agan 3'576540 4/19 Fair e a, I l I U 340M725 the divert station iderglficliltiorcli data. At each divert 3,313,014 4/1967 Lemelson 340/1725 x a winner 5 t e a dress adlacem 3,465,298 9/1969 La Duke et al 340/1725 dlrectly access memory- If the Stored 3.260349 M966 wag ng 335 7 73 data identifies that divert station, a divert mechanism 3,105,601 10/1963 Smoll r 214/11 is actuated. Additional controls provide safety over- 3,356,061 12/1967 Wiggins 118/2 rides and special handling capabilities for special role 3,198,351 8/1965 Paglee 214/11 pans and divert stations. 3,384,237 5/1968 Leonard 209/l22 3,272,354 9/1966 Harrison et a1, 214/11 22 Claims, 8 Drawing Figures -80 '82 STATIONZ 9/4 32' 4 DlVERT V DIVERT a? RIGHT I TATION3 1 1 8O 3O 7 7. 1m

DIVERT T4 STATION N L STOP (26 r 57 I cousoua =1 65 i 62 KEYBOARD 5 32 DISPATCH DISPATCH STATION CONTROL smnons 1 aw- 1 52 so ATENTEDAPR 9 ISM SHEET U 01'' 7 F|G5A 42 (I00 I037 7 READER SHIFT ADDRESS STATION REGISTER V V BUSS I E (II STAGE) I' fig 200 DRIvER I 40 46 L2|7 I 2 f 3Io SENSE VALID P. E. S CLOCK'NG READ X 220 232 INVALID READ RESET RESET RESET DELAY RE. 3m

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INVALID SET STATIDN DISPATCH 3I2 READ CONDITIONS STATION 7 I iTsg MET TURN ON RESET Z I STOP K 302 222 SOLENOID 69 Z I (I I MASTER CORE 2 gfg 'gr CLOCK TIMING 3 COUNTER 4 COUNTER I +6 5 :N l I ue [H8 PATENTEDAPR 9 1974 SHEEI 5 BF 7 FIGSB J:

' IOT1/CD ENTRY 571 I l FLAG ENTER.

SET 54 KEY S A CONSOLE RESET REGISTER KEYBOARD FPS I37 W325i Q E r327-N COMBWE 26: 327-2 I42 1 Y "i r 1 350-2 REGISTER ,34O-2 OUTPUT I INHIBITB CONSOLE 4, 230 3:2 7 ENTRY |3 5 MEMORY STATION OuT {344-2 E 2 2 STATION r RESET 2 I42 SET f MEMORY 342-3 MOQIFY OUT T/ STATION N 3 344-3 l25-N r" yRESET i N I I REGISTER R E G j T R MEMORY RESET OUT j STALION Z INHIBITB: 5TAT|0N A I29 CONSOLE N SET ENTRY q -340-N 344-N DATA 2. 350; DATA 24o OUT n4 n2 f READ INITIATE ADDRESS 126 MEMORY BUSS A WRITE INITIATE 7 CORE ADDRESS" INTERFACE 2 ZIIB L IN I07 A; IIO 322 ATENIEDAPR 9 I974 3.803.556

SHEET 8 BF 7 i /IO? r260 230 [I00 '0' I037 421 READER SHIFT ADDRESS STATION REGISTER FCK T 5 BUSS 2 a 3 (II STAGE) :STAGE DRIVER FIGSC 1, k

VALID STATION (BLOCKING READ 0N Z I42 1 1 260 EL 7 L REsET 1/209 344-2 SENSE DISA L 40 RE. is E OPERATE 205w INHIBIT "r252 EMER 4 FULL 254-2 -254-3 LEFT SSL/FULL T LEFT OIvERT LDIVERT FULL LEFT RIGHT RIGHT EMER 1f I 871/ FULL I40 2 I40 3 I RIGHT Z-I42 q 344-2 L344 N 344-3 ALL ALL zERO 2 STATION A 344 COMPARE 402 COMP RE 2 2 TO MEMORY OUT 4 ITENTEDAPII 9 Iqw SHEET 7 OF 7 :J/IO7 Z 230 u 46 1/ I I0 I03 7 READER SHIFT ADDRESS 42 4/ STATION REGISTER r g 5 BUSS N (n STAGE) {STAGE DRIVER 217m I I07 46 L I Z 232 VALID STATION CLOCKING READ ON Z 23 233- I g O 210 212 220 222 RESET 1 209 250 M20? 407 A f SENSE RE.

, OPERATE 4, 205 D'SABLE INHIBIT 252 M B7/1/- EFUEE A. 254

FULL ,ALFULL PE L DIVERT DISABLE 4 0 j N SPECA 1 I40-N FIGSD CONVEYOR CONTROL SYSTEM BACKGROUND OF THE INVENTION This invention relates to a conveyor control system, and more particularly to a control system for a material conveyor having a plurality of material carriers.

In a typical order-fill conveyor, individual material carriers such as tote pans are routed past various divert stations along a conveyor loop. A dispatch operator initially selects desired divert stations at which a particular tote pan is to be diverted. Numerous programmable controls have been developed to cause the particular tote pan to be diverted at the selected divert stations.

Often, each tote pan carries a coding of all possible divert stations in the system. Selected divert stations are coded by actuating the code elements on the tote pan which corresponds to the selected stations. Each divert station then searches for tote pans having an actuated code element corresponding to that divert station. Such a simple system is limited in applicability in that information in addition to selection of divert stations cannot be handled. For example, it is not possible to code information about the material being diverted, such as product identification, price, etc.

In order to overcome these problems, some material conveyors uniquely code each tote pan with an address, and then store data concerning the tote pan in a central memory. As each tote pan passes a scanner, the tote pan address is transmitted to a computer which is programmed to provide look-up tables or the like which access the proper memory location. Such systems are versatile, but are very costly in terms of the unused capacity of the computer and the software necessary for accomplishing correlating, look-up, and similar func tions.

SUMMARY OF THE INVENTION In accordance with the present invention, a conveyor control system is disclosed which provides all of the advantages of a computerized control system, yet eliminates a general purpose computer, software, and many other ingredients of prior conveyor control systems in order to substantially reduce the cost while still providing the advantages of the more versatile control systems now in use.

One object of this invention is the provision of a conveyor control system in which individual article carriers are directly coded with an internal memory address of a storage location which stores data concerning routing of the individual article carriers.

Another object of this invention is the provision of a conveyor control system having a simplified dispatch station for coding the routing of a carrier and other related information.

A further object of this invention is the provision of an improved material conveyor system having special handling and emergency capabilities for selected material, and improved control of routing of all material.

Further objects and features of the invention will be apparent from the following description, and from the drawings. While an illustrative embodiment of the invention is shown in the drawings and will be described in detail herein, the invention is susceptible of embodiment in many different forms and it should be understood that the present disclosure is to be considered as an exemplification of the principles of the invention and is not intended to limit the invention as to the embodiment illustrated.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a daigrammatic illustration of a conveyor system incorporating the invention;

FIG. 2 is a partly perspective and partly block diagram of an individual tote pan adjacent a typical scanner for one of the divert stations shown in FIG. 1;

FIG. 3 is a block diagram of the control system for the conveyor system of FIG. 1;

FIG. 4 illustrates the format of data stored at individual memory locations in the central memory shown in FIG. 3; and

FIGS. 5A, 5B, 5C and 5D are a single schematic dia gram of the control system shown in block form in FIG. 3, in which the sheets forming FIGS. 5A, 5B, 5C and 5D should be placed side-by-side from left to right, respectively.

GENERAL SYSTEM DESCRIPTION Turning to FIG. I, an exemplary conveyor sortation system of the type suitable for control by the invention is illustrated. A conveyor 20 formed by a moving belt, powered rollers, or other known type carries individual article carriers, such as tote pans 22, along a preselected route past selectively actuable divert stations, only some of which are illustrated. As seen in FIG. 2, each tote pan 22 may comprise an open container having generally rigid side walls for retaining or holding articles or material 24 therein. Each tote pan 22 carries on one external side wall a unique address 26, herein composed of a top row of IO binary digits or bits formed by the presence or absence of retro-reflective chips. In FIG. 2, the presence of a chip is indicated by a darkened square, and the absence of a chip at a bit location is indicated by an open square.

For parity checking purposes, the complement of the address 26 is carried immediately below the upper row of bits, and consists of a lower row of 10 bit positions formed by the presence or absence of similar retroreflective chips. Since the lower row forms a complemented address, each bit location along the top row which has a chip has no chip on the bottom row, and similarly each bit position along the top row which has no chip has a chip in the same bit position on the bot tom row. Of course, other conventional techniques for parity or error checking may be substituted for the illustrated complemented address system. As will appear, address 26 is an internal memory address of a storage location in a central memory.

Returning to FIG. 1, numerous photoelectric scanners are located throughout the conveyor system for sensing tote pans 22, the addresses 26, and other spe' cial codes as will appear. Each such photoelectric (P.E.) scanner, indicated in block form by both circles and squares, emits a photoelectric beam which crosses the conveyor 20 as illustrated by a dashed line. Certain of the photoelectric beams are directed towards reflec- .tors 30 which direct the beams back towards a photoelectric cell mounted in the scanner housing. Each scanner thus comprises a light source and a conventional coaxial photoelectric cell or detector. In order to read the addresses 26 of the tote pans, a photoelectric {P.E.) scanner or reader station 32 is associated with the divert stations and a dispatch station.

Each address reader or scanner 32 includes, as seen in FIG. 2, several P.E. detectors. A light source and coaxial photocell detector 36 read the presence or absence of the retro-reflective chips forming the top row of each adrress 26. A light source and coaxial photocell detector 38 read the complemented light reflective chips forming the bottom row of each address 26. A light source and coaxial photocell detector 40, labeled SENSE PE. and located upstream from detectors 36, 38 detects the presence of a tote pan 22 adjacent the reader station, and has an output beginning when the front or leading wall of the container breaks the photobeam and continuing until the rear or lagging wall of the container passes the reader station. Detectors 36 and 38 form a part of each reader station 42, the reader station for divert station N being illustrated in FIG. 2.

The output from the photocell detector 36 is coupled to a reader output driver 44 which has on an output line 46 an amplified serial bit train corresponding to the upper row of address 26. Both detectors 36 and 38 are coupled to a parity check comparator 48 which determines whether simultaneously appearing bits are always complemented. When the bits are complemented, comparator 48 has no output. If a complement error should occur, comparator 48 generates an error stop output on a line 49 which disables the reader output driver 44, blocking or terminating its output for at least one bit position. When the illustrated address 26 is read with no parity error, line 46 has a serial pulse train indicating the address 1001001110. If a parity error had occurred, less than bits would output on line 46. As will appear, a pulse train ofless than 10 bits disables the address circuits associated with the reader station 42 and thus prevents gaining access to the wrong control data.

Returning to FIG. 1, an operator places an empty tote pan 22 adjacent a dispatch station driver 52 when an incoming order is to be filled. Adjacent dispatch station 1 is located a console keyboard 54 having an individual switch 55 for each divert station in the conveyor system. The operator actuates individual pushbuttons connected with each switch 55 which correspond to stations at which the tote pan 22 is to be diverted in order to pick-up an order.

Divert station N is a special handling area, and tote pans will not be diverted at station N unless they have first been diverted at all other divert stations selected by the operator. Thus, divert station N may be used for subassembly of parts previously picked up, for example.

After the operator has selected the desired divert stations on switches 55, he actuates an enter switch 57 which causes a register to record or store all operator selections. At this time, the operator also actuates a conventional dispatch control switch 60, which initially energizes a stop solenoid 62 to activate a conventional mechanical stop 63 which blocks the passage of tote pans 22 traveling on the conveyor 20. After a short time delay, dispatch control 60 energizes a conventional dispatch station 152, causing a plunger 65 (or other mechanism) to push tote pan 22 onto the moving conveyor 20.

As the dispatched tote pan is moved by conveyor pass the P.E. scanner station 32, the address 26 of that tote pan is read by reader station 1 for that scanner 32 to cause the registered data from console keyboard 54 to he entered in a central memory storage location identified by the read address. Thus, a data word identifying the desired divert stations is automatically en tered into the proper memory location for the tote pan just dispatched.

If a parity error should occur during the dispatch read operation, caused for example by one chip of the address being masked by dirt, the reader station will not output all 10 serial bits of the address, and the registered data from keyboard 54 will not be entered in memory. If the register data is not entered in memory by the time tote pan 22 passes an invalid photoelectric scanner 68, a stop solenoid 69 is energized to activate a mechanical stop which blocks the passage of the just dispatched tote pan 22. Thus, the operator knows that the address 26 of the tote pan was not read, and hence the control system has not recorded the destinations entered on the keyboard 54.

In order to lower stop 70, it is necessary for the operator to manually remove tote pan 22 from conveyor 20, thus remaking the photobeam of the invalid photoelec tric scanner 68 and hence deenergizing stop 69 and causing the mechanical stop 70 to retract. The operator can then correct the cause of the error, as by cleaning the address area on the tote pan, and repeat the dispatch operation. When the address is correctly read, the control circuit disables or blocks actuation of stop solenoid 69. Meanwhile, the stop solenoid 62 is deener gized, allowing tote pans 22 on the conveyor 20 to con tinue around the conveyor loop, which serves as a floating storage system.

Each dispatched tote pan 22 passes the divert stations until it reaches a divert station originally selected on console keyboard 54 when the operator programmed the destinations of that tote pan. For example, as a tote pan passes the photoelectric scanner 32 for divert station 4, the tote pan address is read and directly accesses the central memory which outputs the stored destination data. If the stored data contains a bit corresponding to divert station 4, a divert station unit 74 is enabled to actuate a conventional divert mechanism 75 which removes the adjacent tote pan. The details of the divert station units 74 and divert mechanisms 75 form no part of the present invention, and may take any conventional form, such as a plunger which pushes a tote cart off the moving conveyor. Or, the divert mechanism 75 may comprise powered rollers on a yoke mechanism which rises through openings between powered conveyor rollers in order to drive the tote pans 22 in a particular direction, as left or right, off the conveyor 20. Such a two-directional exit is illustrated for divert station 2 and divert station 3.

After being diverted, each tote pan exits onto a side track which consists of free running rollers 82 having a generally downward slant so as to allow gravity to feed the tote pan 22 to a resting position at the end of the track 80. Each track 80 may be as long as desired in order to temporarily store any desired number of tote pans 22.

Each side track 80 includes a full indicator 85, such as a light source and concentric photocell for emitting a light beam across the track towards a reflector 30, in order to indicate when the side track holds its full capacity of tote pans 22 thereon. The full capacity may be from one to any number of pans, depending upon the length of the side track 80. When full, the control system prevents actuation of the associated divert station unit 74, and thus certain tote pans 22 are not diverted but are left on the loop conveyor 20 which continues to circulate the pan around the conveyor loop. This flexibility is very important in large installations, in that it is not necessary to coordinate the number of tote pans in the system which have been programmed for exit at a particular divert station with the capacity of that divert station.

In some installations, it may be desirable to provide for special handling capabilities, as can occur when a pan does not have sufficient capacity for a complete order, and further pans must be added to carry the order. All such pans must then be assembled in a special area in order to complete the order. On each side track 80 at which special handling capacbility is to be provided, the full bin indicator 85 is located at a position corresponding to less than the maximum capacity of the side track 80, allowing any desired number of additional tote pans to safely be diverted. An emergency full indicator 87, similar to full indicator 85, is located at the position of maximum capacity of the side track 80. The pair of indicators 85 and 87 indicate when the divert station is full with respect to ordinary orders, or at its maximum or emergency full position in which no orders of any kind can be handled.

In order to indicate that any given tote pan 22 is to receive special handling, a person at a divert station places a special retro-reflector 90, FIG. 2, on the tote pan 22. Reflector 90 is mounted on an elongated removable clip 92 which rises the reflector above the level of all material 24 which may be placed in the pan 22, and in line with the position of special photoelectric unit 94, which projects a photobeam into space above the level of the tote pans 22. When a special handling tote pan passes a divert station, the reflector 90 returns the photobeam to a photocell in the special RE. 94, and produces an output. The control system then activates the corresponding divert station 74, FIG. 1, so long as the emergency full indicator 87 is not actuated. Other general features of the control system will be apparent from the following description.

CONTROL SYSTEM A block diagram of a control system for the article conveyor of FIG. 1 is illustrated in FIG. 3. The serial bit output line 46 of each reader station 42 transmits the serial binary address on the adjacent tote pan to a shift register 100 which serves as a serial to parallel converter. An output bus 101 from shift register 100 consists of parallel output lines, one corresponding to each bit position of the 10 bit position address. ln FIGS. 3 and 5, buses composed of a plurality of lines are generally indicated by a line surrounded by a circle, whereas a control line generally carrying a single bit or signal is indicated by a line without a circle.

Address bus lines 101 from the shift registers 100 are coupled to an address bus driver 103 which may amplify the signals and, under control of a station selection counter 105, gates only one address onto an address in bus 107 for a central addressable memory 110. Memory 110 is comprised ofa large number of storage locations, each location storing a word of data. Each data word may be composed of 8 bits, 16 bits, or any other conventional length. The address in bus 107 directly accesses the internal storage location identified by the 10 bit address on the lines forming bus 107. Each data word is transmitted to its storage location via a data in bus 112, and transmitted from its storage location via a data out bus 114, both buses 112 and 114 being composed of the same number of lines as the bit length of the data word (plus an additional line for parity if desired).

When data is to be stored in the memory storage locations, a read initiate line 116 is energized, causing the data word then on bus 112 to be stored in the memory location identified by the address word on bus 107. When data is to be transmitted out of the memory, a write initiate line 118 is energized, causing the data word stored in the memory location identified by the address word on bus 107 to be transmitted to data out bus 114. Memory 110, per se, may be formed of any conventional memory unit. For example, memory may be a coincident current core memory, such as manufactured by Fabri-Tek of Minneapolis, Minn., Model 420, having a storage capacity of 1,024 words each having a word length of eight bits.

The fon'nat for the data contents at each storage location in core memory 110 is illustrated in FIG. 4. For the particular memory specified above, only eight bit positions are available at each address, and hence only eight dispatch stations may be serviced in the present example. Of course, any number of stations may be serviced by increasing the bit length of the storage words, or by providing optional chaining, or by using combinations of bits to represent a binary code. Combinations of bits, however, require additional decoding to identify individual divert stations, and hence allocating a single bit position for each divert station is preferred if consistent with the capacity of the memory being utilized.

As seen in FIG. 4, the illustrated tote pan 22 carries a binary address 26 composed of 10 bits, namely, l00l00l 1 10. The format of the data word stored at this direct core address is illustrated in FIG. 4. Each selection ofa switch 55, FIG. 3, on the console keyboard 54 causes a corresponding bit position associated with that switch and that divert station to be set to a 1 bit. In the illustration in FIG. 4, a 1 bit is set for at least divert stations 2, 4 and N, but not for divert station 3. At the next core address 1001001 I l l, prior actuation of the console keyboard selected divert stations 2 and 3, but not divert stations 4 and N.

As indicated in FIG. 4, any amount of additional information may be associated with a given word address, either by increasing the word bit length or by using known chaining techniques. This allows additional information to be stored with data on selected divert stations, indicating for example product identification, the date or time at which the tote pan was dispatched, the weight of initial parts in the tote pan, or the like. For simplification, the remaining description will concern an eight bit length word which identifies only divert stations, it being understood that other data could similarly be stored in place thereof or in addition thereto.

Returning to FIG. 3, each data word in a given storage location in memory 110 is coupled via data out bus 114 to a station registers unit 125, which consists of an individual register or flip-flop for each bit in the data word. Thus, an output line I27 is enabled when the divert station 2 bit position has a I bit stored in core, and an output line 129 is enabled when the data word has a 1 bit stored at the divert station N bit position. The data word is also coupled over a data bus 130 to a core entry control unit 135. Unit 135 is effective to gate onto data bus in 112 the data word on bus 130, or to switch during dispatch operation from bus 130 to a bus 137 coming from the console keyboard 54. Individual bits of the data word can be deleted by actuation of corresponding delete lines, and thus effectively prevented from being written into the memory 110.

Memory 1 is of the destructive type in which a data word is destroyed when read out of core, and hence must be rewritten in core if the contents of the data word are to be saved. Generally, each reading of a data word initiated by energization of line 116 causes the word to be stored in register 125, and rewritten via control unit 135 into the same memory location unless the word contained a bit corresponding to a divert station which was actuated.

When reader station 2 is enabled, for example, and the gated address causes the memory to output a data word with a I bit on the 2 position line 127, a divert station 140 corresponding to reader station 2 is actuated. Each divert station 140 when enabled energizes the corresponding divert station 74 in FIG. 1, and also causes an output on a divert line 142 in FIG. 3 which deletes the corresponding bit from the data word. When the data word is subsequently rewritten back into core, the bit corresponding to the divert operation which just occurred is missing, indicating the programmed operation has occurred.

Memory 110 is time shared with each station in the control system. During the time period that counter 105 maintains enabled one reader station and associated apparatus, a core timing counter 145 steps through a complete cycle, generating timing pulses for all control functions necessary for time shared operation of each reader station. At the completion of the core timing cycle, the first output of core counter 145 steps station counter 105 to its next state, enabling the next reader station at which counter 145 again repeats the same control functions. By way of example, the station operation for the dispatch station and one divert station now will be described in detail.

After an operator has entered the desired divert stations on console keyboard 54, he actuates enter switch 57, causing a data word representing the actuated switches 55 to be stored in preparation for entry into the memory 110. The operator then actuates dispatch control 60, FIG. 1, causing the tote pan 22 to be transported by conveyor pass the dispatch station scanner which includes reader station 1. The resulting output on serial bit line 46 is immediately stored in shift register 100. The above operations can occur at any time, regardless of the state of station selection counter 105, since they do not require access to memory 110.

As core timing counter 145 completes its last count, the next count actuates the first stage output line 150, stepping station selection counter 105 to its next state. It will be assumed that output line N of counter 105 had previously been actuated, hence the pulse on line 150 enables the first output line 1 of counter 105. Output line 1 now enables driver 103 associated with station 1, gating the stored address onto bus 107. The gated address is maintained on bus 107 until the station selection counter 105 steps to another station after completion of a complete clock cycle.

Core timing counter 145 now counts and enables its next stage, actuating read initiate line 116. This causes the data word, if any, already stored in the memory storage location identified by the address on address in bus 107 to be accessed and transmitted via data out bus 114 to station registers 125. The data word has no meaning at this time, since a new data word is about to be entered from the keyboard 54. Nothing further occurs at this time in the core cycle because station selection counter is not enabling any divert station and hence no divert operation can occur.

As core counter 145 steps to a next state, write initiate line 118 is enabled. Because counter 105 is enabling station 1, control unit effectively disables bus 130 and couples data bus 137 to data in bus 112, causing the data word from keyboard 54 to be written and stored in the location identified by the address still held on address in bus 107. Thus, the new data word is written into the core location identified by the address originally read by reader station 1. As core counter 145 counts to its last state, a reset line 152 is enabled, reset ting to zero all of the station registers 125 and thus erasing the prior stored data word.

The next count of core counter 145 restarts the cycle by enabling line 150 and causing station selection counter 105 to energize the next output line, time shar ing a different reader station with memory 810. The cycle time for station selection counter 105 is chosen to complete a cycle for all stations in the control system faster than the minimum time elapse for the closest two tote pans to pass any reader station. The access time of typical memories allows a cycle time far in excess of most system requirements clue to the extremely slow speed, relatively considered, of a mechanical conveyor 20.

As a second example, it will now be assumed that station selection counter 105 has just been stepped to count 2, enabling line 2 which gates address bus driver 103 for station 2. It will also be assumed that the tote pan 22 of FIG. 2 has just been read by the associated reader station 42 for station 2. Shift register 100 of FIG. 3 now has stored therein the binary memory address word IOOIOOI I 10 (as seen from FIG. 2), which is gated onto bus 107.

Core timing counter 145 now energizes read initiate line 116, transmitting the contents of storage location IOOIOOI I 10 via data out bus 114 to registers 125. As seen in FIG. 4, the contents include a 1 bit at the station 2 location. Therefore, registers 125 have a I bit output on the 2 station output line 127. Divert station associated with station 2 now has all enabling inputs, that is, both register 125 and station counter 105 have 1 bits for station 2. The divert stage 140 is enabled and it energizes divert station 74, FIG. 1, associated with divert station 2. This causes the divert mechanism 75 to convey the tote pan which was read by the station 2 reader onto the station 2 side track 80. Returning to FIG. 3, enabling of divert stage 140 also energizes line 142, causing control unit 135 to effectively erase or delete the contents of the bit 2 position in station registers 125.

Core counter again steps and now enables the write initiate line 118. The data word from registers 125 is now rewritten back into the same memory location, absent a I bit at location which was erased by operation of the delete line 142. Core counter 145 now steps to its last count, enabling reset line 152 and thus erasing the contents previously stored in station registers 125. The control system is now ready to begin another time share operation with the next station.

Should divert station 2 have been full in the last example, the divert stage 140 would have been disabled, and thus the tote pan would have been transported past the station. Because divert stage 140 was disabled, delete line 142 would not have been energized and hence the divert station 2 bit would not have been erased. At the write cycle time, the identical data word originally read out of the core memory would be rewritten back into memory, allowing the tote pan to be removed at a later time when it again passes the divert station 2 and the divert station was not full. Thus, the loop conveyor serves as a recirculating storage system which fills order stations at a rate (and priority, as previously described) coordinated with the separate capacity of each station. Many other advantages will be apparent from subsequent sections.

DETAILED CONTROL SYSTEM CONVENTIONS In FIGS. A, 5B, 5C and SD, the control system shown in block form in FIG. 3 is illustrated in detail. Elements preforming a similar function at each conveyor station have been identified by the same reference numeral, sometimes followed with a dash and the number of the station associated therewith. The elements may operate with negative or positive going signals and levels (or a mix thereof) representing gating, enabling, and 1 bits, as desired. For clarity, conventional interfaces for changing signal level or drive requirements, NOT gates for providing inverted or complemented signals where necessary, and time delay elements for providing time delays apparent from this disclosure are generally not illustrated.

The general operation of the control system will not be repeated in the following detailed sections except insofar as necessary for an understanding of the additional elements shown in FIGS. 5A-D. The lines crossing between the sheets of drawings may be connected by placing side-by-side FIGS. 5A, 5B, 5C and 5D from left to right, respectively. Generally, all logic blocks (except registers) which have a plurality of inputs and one or more outputs generate an output signal at all outputs only when signals are present at all inputs. Thus each such logic block having plural inputs performs an AND gate function, unless noted otherwise.

READER STATION CIRCUIT Each reader station 42, address shift register 100, and address bus driver 103 operate in a generally similar manner and will be described with reference to the apparatus of FIG. 5D which illustrates station N. Turning to FIG. 5D, shift register 100 comprises an 1 1 stage register in which the first l0 stages, when the reigster is full, hold the read memory address and have parallel outputs which form bus 101. The last stage 200 of the register I00 indicates that the register has valid information when a I bit is present on an output line 201 of stage 200. Output line 201 does not form a part of the parallel bus 101.

As seen in FIG. 2, when a tote pan 22 first approaches reader station N, the same photodetector 40 detects the presence of the front wall of the tote pan 22 before photocells 36, 38 read address 26. Returning to FIG. 50, the sense RE. 40 has one output line 205 which forms an enabling input for divert unit l40-N. Sense RE. 40 also has an output line 207 which is coupled to a reset stage 209, a clocking stage 210, and an input of shift register 100. Clocking stage 210 also has an input from reader station output line 46 (which does not yet have an output).

Reset station 209 comprises a differentiator which generates an output pulse on line 212 which resets or clears all l l stages of shift register 100. However, since line 207 coupled via a line 215 to the input of the shift register has a continuing output from the sense RE. 40, a I bit is now set in the first stage of the shift register 100. This one bit will be shifted through the register and eventually appear in last stage 200, thus indicating that the remaining ten stages contain l0 bits of data, hence no parity error had occurred.

The output line 207 of sense PE. 40 is diagrammatically illustrated as connected to the input of shift register 100, to indicate that the first stage thereof is set when a bit is first present on line 207. Thereafter, the line 207 is no longer effective to control the input of the shift register 100. Any desired circuit (not illustrated) may be used to disable line 207 from further control of the input of the shift register I00 when data appears on line 46.

As the memory address begins to be read, line 46 has a series of bits thereon corresponding to the presence or absence of reflective chips. Desirably, the 0 and l levels are both different from the level when no signal is read, so as to provide clocking indications. Alternatively, a 1 bit at either detector 36 or 38, FIG. 2, could be coupled via an OR gate to clocking unit 210. As the first bit from line 46 appears at the input of shift regis ter I00, it is also coupled to clocking stage 210 which generates an output pulse on a clock output line 217. This clock pulse steps or shifts the register, thereby entering the 0 or I bit from line 46. The occurrence of the next bit from the reader station 42 again generates another clock pulse on line 217, shifting the register and entering the bit. This continues until the complete 10 bit address is entered into shift register 100.

Upon the completion of storage of the 10th bit, the initial one bit entered from sense PE. 40 will have been shifted to the last stage 200 of the shift register. This generates a one bit output on line 201 which causes a valid read stage 220 to have an output to a station on stage 222. As the tote pan passes the reader station, RE. 40 no longer has an output on line 207, disabling clocking stage 210. Meanwhile, the enabling bit from valid read stage 220 remains on until the control system cycles to station N and gates the address now stored in the shift register 100.

The last stage 200 circuit prevents an incorrectly read address from being gated through address bus driver 103 to the address in bus 107. Returning to FIG. 2, it will be recalled that the parity check stage 48 generated an error stop signal on line 49 if a parity error occurred in reading the address 26. This error stop signal causes output line 46 to have a series of binary bits less than 10. Returning to FIG. 5D, the occurrence of a parity error would thus cause less than 10 bits to be produced on line 46, and thus when sense P.E. 40 disabled clocking stage 210, the initial one bit entered via line 215 would not be contained in stage 200. As a result, the valid read stage 220 would not be enabled, and the tote pan would not be diverted.

After the tote pan recirculates and again passes reader station N, it will be diverted if the address is now read without a parity error. Additional apparatus can be provided. ifdesired, to indicate that a one bit did not occur on line 201 when sense PE. 40 returned to a zero state, in order to signal that an error has occurred. Such an error signal could be utilized to initiate corrective action, such as diverting the tote pan at a special error correction station where the cause of the error could be determined. Other such modifications will be apparent to those skilled in the art.

The storage of an address in shift register 100 occurs whenever a tote pan passes the reader station. When station selection counter 105, FIG. 5A, counts to station N, it generates an output on line 230 which forms a second input to station on stage 222. If the valid read stage 220 also has a one output at this time, lines 232 and 233 are activated. If shift register 100 were in the process of storing an address when line 230 was enabled, valid read stage 220 would not have an output (because stage 220 is not yet enabled), and hence an incomplete address cannot be gated onto the address in bus 107.

Assuming a complete address had already been stored in shift register 100 and valid read stage 220 had an output, then station on stage 222 would generate an output on lines 232 and 233 immediately upon receiving an input from line 230. The output on line 232 enables address bus driver 103, thereby transferring the stored address via address in bus 107 to an address bus interface driver 240, FIG. 5B, which directly drives the address in bus of memory core 110.

Returning to FIG. 50, the output on line 233 resets last stage 200. This removes the output on line 201 and thus prevents the same address from later being again gated when the station selection counter 105 cycles through all stations and again reaches station N.

Station on stage 222 also has a further output 250 which forms one enabling input of an operate inhibit stage 252 which controls enabling of the associated divert stage 140. If the other input of operate inhibit stage 252 has an enabling input at this time, and the stage 252 is not disabled by the full and emergency full indicators, then an output is generated on a line 254 which activates the divert stage 140 and causes the tote pan whose address is now being held on address in bus 107 to be diverted.

The other reader stations operate in generally the same manner as reader station N. It will be recalled that divert stations 2 and 3 produce exits to the left and right, respectively, at the same conveyor location. Therefore, only a single address scanner is necessary to service both divert stations 2 and 3. As seen in FIG. 5C, a single reader station 42 is used, and thus shift register I gates its stored address to bus 107 whenever station on stage 222 is enabled by valid read stage 220 and by an input line 260. Line 260 is coupled to an OR gate or combine stage 261, FIG. B, which has inputs from both the 2 and 3 station outputs of station selection counter 105, FIG. 5A. The operate inhibit stage 252 in FIG. 5C essentially is two independent units, each operating identical to stage 252 of FIG. 5D. Thus, an output is generated at line 254-2 when input line 250 has an enabling input and the input associated with station 2 is enabled, and an output is generated at line 254-3 when line 250 is enabled, and the other enabling input associated with station 3 is enabled. The operation of the disabling inputs will be described later.

DISPATCH READER STATION CIRCUIT Dispatch reader station I has additional elements not found in the other divert reader stations, due to the different nature of the dispatch operation. Also, some elements associated with the divert reader stations are eliminated. Turning to FIG. SA, sense RE. 40 generates an output on line 207 which sets the first stage in shift register 100, and inputs to a reset stage 209' which is similar to reset stages 209 but contains an additional enabling input. The line 207 also forms the set input to an invalid read stop driver 280 which has an output for enabling the stop solenoid 69.

In operation, the sensing of a tote pan causes driver 280 to be set, and upon complete storing of an address, the valid read stage 220 causes driver 280 to be reset, thereby causing no output when the invalid read reset P.E. 68 is subsequently enabled as the same tote pan passes the photoelectric scanner. If an error had occurred, and hence last stage 200 was not set, then driver 280 would not be reset and the gate signal from P.E. 68 would cause the stop solenoid 69 to be ener gized.

The dispatch station turn on and reset operations are also modified. When core timing counter 145 has an output on line 150 which causes station selection counter to step to output I, an enabling input is coupled to a dispatch station turn on stage 222. As core counter 145 steps to output 2, an enabling input via a line 300 causes stage 222' to turn on if an enabling input is also present from a station conditions met stage 302. Stage 302 has an output when the valid read stage 220 has an output, indicating a complete address is stored in shift register 100, and a line 304 has a one bit thereon indicating that data entered at console keyboard 54 is ready to be stored in the memory core.

Assuming both inputs are enabled to station conditions met stage 302, it has an output which combined with the other enabling inputs causes dispatch station turn on 222' to be energized. This produces outputs which are coupled to a reset delay stage 308, and are coupled via a line 312 to the core entry control and via line 232 to address bus driver 103. The enabled bus driver 103 gates the stored address from register I00 onto address in bus 107. The signal on line 312, as will appear, causes the stored information from the console keyboard to be gated to data in bus 112 in place of any data stored in the station registers 125.

Reset delay 308 has a time delay sufficient to allow core timing counter to step through output 5, enabling line 118 which causes the data originated from console keyboard 54 to be entered in memory core 110 in the storage location of the address held on the ad dress bus 107. After lapse of this time period, reset delay 308 has an output on a line 310, part of which fonns an enabling input to reset stage 209. Since reset 209' has an enabling input at this time from sense PE. 40, an output is generated on line 212 which resets all eleven stages of shift register 100. Line 310 from reset delay 308 also is coupled to clear the data at registers associated with the console keyboard 54.

MISCELLANEOUS CIRCUITS The clock and cycle control circuits are also shown in FIGS. 5A. A master clock 320 generates output pulses which are counter by core timing counter 145, illustratively a divide-by-six circuit with automatic reset upon completion of the sixth count in order that the next master clock pulse will again enable the first output. If desired, counter 145 could be a divide-by-seven circuit in which the seventh output was used to reset the counter. The fourth stage of counter 145 is connected to an output line 322 which enables a special handling circuit, to be described. The other outputs of counter 145 have already been described.

Station selection counter 105 may comprise a divideby-N counter having the same internal construction as counter 145, but modified if necessary to provide a count of N rather than a count of six.

The dispatch statin console keyboard 54 and associated apparatus are illustrated in FIG. B. Each selection of an individual station switch 55 is transmitted over a corresponding line in bus 137 to a corresponding flip-flop 325. The setting of each flip-flop 325 produces an output on a corresponding flip-flop output line 327. After an operator has made all desired selections, he actuates enter switch 57, which via a corresponding line in bus 137 sets an entry flag flip-flop 330. The output line 304 of flip-flop 330 forms one of the inputs which determine that the dispatch station should be turned on, as previously described. Data held on the output lines 327 will then be gated to data in bus 112. Thereafter, reset delay line 310 will be energized, resetting all keyboard associated registers, namely all flipflops 327 and 330.

STATION REGISTER AND CORE ENTRY CIRCUITS Station registers 125 and core entry control 135 are shown in detail in FIG. 58. Data output bus 114 has individual lines, corresponding to each storage bit location, which are coupled to the set inputs of corresponding registers or flip-flops for each divert station. For clarity, only station register 2, labeled 125-2, and station register N, labeled 125-N, are shown in FIG. 58. It is to be understood that similar registers 125 and associated apparatus are provided for each of the other individual output lines of data out bus 114.

Each individual register station 125 has an output coupled to an associated register output inhibit and console entry stage 340, and to a memory out stage 342. Thus, output line 127 from register station 125-2 enables memory out station 142-2, and similarly output line 129 from station register 125-N enables memory out station 142-N. Each memory out station 342 has an output line 344 which forms one input to the apparatus (including operate inhibit stage 252) which controls whether a particular divert station will be enabled. To clear each register station 125, a modify stage 350 has an output coupled to the reset input of each register station 125.

In operation, data out bus 114 has signals thereon when an address is being held on the address in bus 107 and the read initiate line 116 is enabled. This causes the core contents of a particular storage location to set or be transferred to the corresponding divert station registers 125. Each station register 125 which was set to a 1 bit due to the presence ofa 1 bit in the storage location has a I bit output which forms an enabling input to the stage 340, and via memory out station 342 forms an enabling bit for each of the divert stations.

Register output inhibit and console entry stages 340 are not like the other logic blocks shown in the diagrams. Each stage 340 normally connects the output from register station 125 directly to output line 350, allowing the data words read out of core to be rewritten in core during the write initiate portion of the core timing cycle. However, when line 312 is energized by the dispatch station turn on stage 222' (FIG. 5A), then each stage 340 is effective to switch from or block the input to the register stations 125, and connect the input line 327 directly to output line 350. This allows the data word stored in the keyboard registers 325 to be written into the memory core while the dispatch station is time shared with the memory core.

Assuming by way of example that station selection counter 105, FIG. 5A, is enabling its second stage and hence time sharing memory with the divert station 2 apparatus, the following operations will occur. If memory 110 had stored a data word with a I bit in the station 2 position, then register station -2 will be set during the read initiate mode and will cause an output on line 127 and hence on line 344-2 which forms an enabling input to operate inhibit stage 252, FIG. 5C. If station on stage 222 is also enabled, then an enabling signal will be present on output line 250. As a result of the enabling signals on lines 250 and 344-2, operate inhibit stage 252, FIG. 5C, will pass a signal to output line 254-2 and enable divert left stage -2 (assuming an enabling output is also present on line 205). Divert left station 74 for station 2, FIG. 1, is actuated by stage 140-2 and causes the adjacent tote cart to be diverted to the left onto the side track.

Divert left stage 140-2, FIG. 5C, also at this time generates an output on line 142 which forms an enabling input to modify stage 350-2, FIG. 58. Because stage 350-2 also has an enabling input from station selection counter 105, an output is generated which resets register station 125-2. Shortly after clearing register station 125-2, the core timing counter 145, FIG. 5A, will step from count 3 to count 5, enabling the write initiate line 118. Returning to FIG. 5B, the data in each register station 125 will now be rewritten back into core through stages 340. However, the 1 bit corresponding to station 2 is deleted because it has been erased.

SPECIAL HANDLING AND SAFETY CIRCUITS Special routing may be provided for by requiring, for example, that a tote pan be diverted at a particular divert station only after having previously been diverted at one or more prior divert stations. In the present example, divert station N is enabled to remove a tote pan only when a one bit is set in the storage location for station N and the tote pan has already been diverted at all other divert stations at which a one bit was originally set. Since each diverting operation resets the register station 125 to zero, a divert operation at station N occurs only when a 1 bit is present in location N, and all other bits of the stored data word are zero.

To detect for all zeros in the data word locations 2 through (N-l), an all zero comparator 400, FIG. 5C, has inputs connected to each line 344 from the memory out stations 342, FIG. 5B, for each bit position except station N. When all inputs to comparator 400 are zero, an output line 402 generates a 1 bit which is coupled to an input of an all station compare stage 405. During the count 4 mode of the core cycle, line 322 to stage 405 has an enabling input. If input 344-N also has an enabling I bit, then stage 405 generates an output on a line 407. Line 407 forms an input to operate inhibit stage 252 for station N, FIG. 50, and operates in the same manner as inputs 344 for the operate inhibit stages 252 of the other divert stations.

Each operate inhibit stage 252 has a plurality of disable inputs which block actuation of the associated divert stage 140 when the full indicators 85 and emergency full indicators 87 have outputs indicating that no more tote pans can be received. Each emergency full indicator 87 directly inputs to its associated operate inhibit stage 252 and prevents generation of an output on line 254 regardless of all other conditions occurring in the system. If a given divert station is not to handle emergency or special orders, then its full indictor 85 also can be directly connected to the disable input of its operate inhibit stage 252. Such a circuit is illustrated in FIG. 5C for reader stations 2 and 3. However, it is preferred that each full indicator be effective to disable the operate inhibit stage 252 only if no emergency order is present. Such a circuit is shown in FIG. 5D.

Turning to FIG. 5D, full indicator 85 has an output on a line 410 whenever the full indicator is actuated and no disable signal is received from the special P.E. 94. If the special PE. 94, H6. 2, detects a special handling tote pan, then full indicator 85, FIG. 5D, is disabled in order to remove any disabling output on line 410.

While certain special handling and safety overrides have been illustrated, it will be apparent that other combinations of safety circuits and overrides can be provided as desired. Also, while tote pans are illustrated for the material carriers, it will be appreciated that the invention is equally applicable in any material handling or conveying system utilizing separate material or work carriers which can be coded as previously described. Other modifications will be apparent to those skilled in the art.

I claim:

I. A control system for a material conveyor, comprismemory means having a plurality of separate data storage locations each identified by a unique memory address, address data output means, and input means for transmitting data from a storage location identified by a memory address to the data output means;

a plurality of material carriers each carrying a different one of said memory addresses;

input means for storing in each storage location data identifying a desired routing of the carrier having the same memory address as that storage location;

write initiating means for transmitting the memory address of a single carrier to said address input means; and

utilization means for routing said single carrier under control of the data at said data output means.

2. The control system of claim 1 wherein said memory means includes data input means for storing data in the storage location identified by a memory address at said address input means when said memory means is in a read initiate mode,

said input means includes reader means for reading the memory address carried by a selected carrier and for transmitting the read memory address to said address input means, entry means for generating data for routing said selected carrier, and read initiating means for coupling said entry means to said data input means and for establishing said read initiate mode.

3. The control system of claim 2 including stop means effective when enabled for stopping the passage of said selected carrier, and error means for enabling said stop means when an error occurs during said read initiating mode.

4. The control system of claim 3 wherein said error means includes safety means for generating a signal when said reader means does not correctly read the memory address carried by said selected carrier, said safety means being coupled to enable said stop means.

5. The control system of claim 2 wherein said utiliza tion means includes a plurality of divert stations for diverting an adjacent carrier when enabled, said entry means generates data words selectively identifying desired divert stations which are to be enabled when the selected carrier passes adjacent thereto, said write initiating means includes a separate scanner means associated with each of said divert stations for reading the memory address of the carrier routed adjacent thereto, and said utilization means further includes decoding means for decoding the data word at said data output means to enable the divert station associated with the scanner means which read the memory address transmitted to said address input means.

6. The control system of claim 5 including time share means for time sharing said memory means with each divert station and associated scanner means.

7. The control system of claim 6 wherein said entry means includes keyboard means having a plurality of separate switch means each associated with a different divert station, register means for storing a data word representing actuation of desired ones of said separate switch means, said time share means being effective to couple said register means and said reader means to said memory means to store said data word in the storage location identified by the memory address read by said reader means.

8. The control system of claim 1 wherein said utilization means includes a plurality of route stations individually actuable to control the routing of a carrier adja cent thereto, said write initiating means includes a plurality of scanner means each associated with a route station for reading the memory address carried by the material carrier adjacent the route station, and

selection means for coupling a selected route station to said data output means and the associated scanner means to said address input means.

9. The control system of claim 8 wherein each of said separate data storage locations stores a data word consisting of unique indicia representing selected route stations which are to be actuated when the carrier having the same memory address as the storage location is routed adjacent said selected route stations, and decoding means associated with each route station and effective when said selection means couples the associated route station to said data output means for decoding said data word to actuate said route station.

10. The control system of claim 9 wherein said data storage locations each comprise a plurality of separate bit storing areas each associated with a different one of said route stations, each area storing a bit indicating that the associated route station is to be actuated, and said decoder means includes separate register means for storing each bit from said areas, and means coupling each separate register means with a different route station to control actuation thereof.

11. The control system of claim 8 wherein each of said scanner means includes storage means effective independent of said selection means for storing the read memory address whenever a carrier passes adjacent the scanner means, and said selection means couples the storage means of the associated scanner means to said address input means when coupling the selected divert station to said data output means.

12. The control system of claim 11 wherein each scanner means further includes completion means for effectively generating a blocking signal when the associated storage means does not have a complete address stored therein, and safety means responsive to said blocking signal for preventing said selection means from coupling the storage means to said address input means.

13. The control system of claim 12 wherein said completion means includes carrier indicator means for generating a signal when a carrier is adjacent the associated scanner means, said storage means comprises a shift register having a plurality of stages, means responsive to said carrier indicator means for setting a bit in one of said stages of said shift register, clocking means for stepping said shift register to store the memory address read by the scanner means, valid read means coupled to a selected stage of said shift register for generating a valid read signal when the selected stage stores said bit, and safety means effective in the absence of said valid read signal for blocking the transmission of the address stored in said shift register.

14. The control system of claim 1 wherein each of said material carriers comprises container means having a plurality of walls for containing articles therein, and said memory address for each container means comprises a plurality of scannable elements mounted on an external one of said walls.

15. The control system of claim 14 wherein the write initiating means includes source means for emitting an energy beam along a path which intercepts the scannable elements on each container means conveyed thereby, and detector means responsive to a change in level of said energy beam for producing a signal indicating the presence or absence of a scannable element.

16. The control system of claim 14 wherein the scannable elements comprising said memory address are located within a first area on the external wall, a plurality of second scannable elements each comprising the complement of a corresponding one of the scannable elements in said first area and arranged within a second area on the external wall,

said write initiating means includes first area scanning means for developing an address signal representing the scannable elements within said first area, second area scanning means for developing signals representing the complemented address within said second area, output means for transmitting the address signal from said first area scanning means to said address input means, and error means responsive when the signal from said second area scanning means is not the complement of the signal from said first area scanning means for effectively disabling said output means.

17. The control system of claim 1 wherein said utilization means includes a plurality of divert stations indi vidually actuable to divert a carrier adjacent thereto, said input means includes memory alter means for changing the data stored in each memory location as the carrier having the same memory address is diverted at each of said divert stations, at least one of said divert stations including decoder means coupled to said data output means for actuating the associated divert station only when the data indicates that the carrier has previously been diverted at predetermined ones of said di vert stations.

18. The control system of claim 17 wherein said memory alter means erases data identifying a selected divert station after the carrier having the same memory address has been diverted at the selected divert station, and said decoder means is responsive when the data indicates no divert stations other than said at least one divert station remain to be actuated for actuating the associated divert station.

19. The control system of claim I wherein said utili zation means includes full indicator means for preventing the routing controlled by the data at said data output means, special means for indicating that a desired carrier is to receive special handling with respect to other carriers, and override means responsive to said special means for effectively disabling said full indicator means to allow routing of said desired carrier.

20. The control system of claim 19 wherein said ove rride means includes emergency full indicator means for indicating when carriers to receive special handling are to be prevented from being rounted by said utilization means, and emergency means responsive to said emergency full indicator means for effectively disabling said override means.

21. The control system of claim 19 wherein said spe cial means comprises a detectable element mounted on said desired carrier and separate from said memory address, and special handling means responsive to detection of said detectable element for enabling said override means.

22. The control system of claim 21 wherein said detectable element comprises a reflector with removable mounting means for attaching said reflector to any desired one of said material conveyors which are to receive special handling.

* t i i UNITEE) STATES EATENT OFFICE CERTIFEQATE OF (LORRECTI'GN Page-mt No. Dated April 9,

i fls) Terrence L. Duffy c is certified thac error appears in the above-identified patent and char said Letters Patent are hereby corrected as shown below:

IN THE SPECIFICATION:

Co .u--.n 2, line 4, "daigrarm'aatic" should be --diag"ramma'cic. Colman 5, line 15, "capacbility should be ---capability-. Coiamn 5, line 30, "rises" should be --raises----.

(3 3.11m. 8, line 25, "81.0" should be --'iiO-.

COLW'U.112, line 66, "counter" shouid be -counted--.

Column 13, line 13, "statin" should be --stationfl-IE CLAIMS Claim i, Line 5, after "address," delete --address and before "input" insert -address-.

Claim 20, line 4, "rounted" should be routed--.

Signed and sealed this 10th day of September 19 1 {S L) Attest:

uLcCOY M. GIBSON, JR. 0. MARSHALL DAN'N :JCLSSCLIQ: Officer Commissioner of Patents

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Classifications
U.S. Classification700/226, 700/230, 198/349
International ClassificationB65G47/50
Cooperative ClassificationB65G47/50
European ClassificationB65G47/50