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Publication numberUS3803589 A
Publication typeGrant
Publication dateApr 9, 1974
Filing dateDec 1, 1971
Priority dateDec 2, 1970
Also published asDE2159901A1, DE2159901B2, DE2159901C3
Publication numberUS 3803589 A, US 3803589A, US-A-3803589, US3803589 A, US3803589A
InventorsY Hatsukano, H Kawagoe, K Nomiya
Original AssigneeHitachi Ltd
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Display signal converting apparatus
US 3803589 A
Abstract
In a signal converting apparatus for converting a binary signal representing predetermined information into a drive signal for operating a display device having a plurality of luminous elements, there are provided a shift resistor for storing the binary signal, a first MOS matrix circuit connected to the shift resistor for converting the binary signal into a decimal signal, a second MOS matrix circuit connected to the first MOS matrix circuit for converting the decimal signal into a character signal to be displayed, and a drive circuit connected to the second MOS matrix circuit for and applying the character signal to and driving the luminous elements.
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United States Patent 11 1 Hatsukano et al'. Apr. 9, 1974 [54] DISPLAY SIGNAL CONVERTING 3,396,378 8/1968 Keith, Jr. 340/336 x APPARATUS 3,541,543 11/1970 Crawford et al 346/336 X [75] Inventors: g j i p f Primary Examiner-Charles D. Miller omlya o awagoe a C Attorney, Agent, or Firm-Craig and Antonelli Tokyo, Japan [73] Assignee: Hitachi, Ltd., Tokyo, Japan 57 ABSTRACT [22] Filed: Dec. 1, 1971 In a signal converting apparatus for converting a binary signal representing predetermined information [2]] Appl into a drive signal for operating a display device having a plurality of luminous elements, there are pro- [30] Foreign Application Priority Data vided a shift resistor for storing the binary signal, a Dec. 2, 1970 Japan 45-105831 first MOS matrix Circuit Connected to the Shift resistor for converting the binary signal into a decimal signal, [52] U.S. Cl 340/347 DD, 340/336 a Second MOS matrix circuit Connected to the first [511 in. C1. G06t 3/00 Mos matrix circuit fci ccnvciiiiig dccimai signal [58] Field of Search 340/347, 324.1, 336 into a Character signal to be p y and a drive cuit connected to the second MOS matrix circuit for 5 R f n i d and applying the character signal to and driving the UNITED STATES PATENTS Nakauchi 340/336 R1 DYNAMII) SHlFl H? READ lllll REGISTER ll SlGNAl ll'ltMllllV Q luminous elements.

3 Claims, 15 Drawing Figures VE BlIIlS 1; a 1. I5 is i: Bbllllllllli lilllllllfll ll: Sllillllll SIGN/ll BUNVERTER Silillll PATENTEBAPR 9:914

SHEET 3 [1F 7 INVENTORS YOSH l KAZU HATSUKANO KOSEI N 0M! YA ATTORN E Y5 PATENTEU'APR s 1974 SHEET m 0F 7 IN VENTORS Y05HIKAZU HATSUKANQ Ro a NOM YA HIROTO KA AGOE aMwwws 1-502 ATTORNEYS 1 DISPLAY SIGNAL CONVERTING APPARATUS BACKGROUND OF THE INVENTION This invention relates to a signal converting apparatus for converting a binary signal representing given information into a signal utilized for driving a display device.

Display signal converting apparatus utilized to display bit signals as visible letters or digits are now widely used in information processing apparatus such as table mounted electronic computers and electronic measuring apparatus such as a digital voltmeter. It is advantageous to fabricate such a signal converting apparatus on a single substrate by integrated circuit techniques for the purpose of miniaturizing the apparatus, decreasing the weight, improving the reliability and operating characteristics and decreasing the cost of manufacturing.

However, to fabricate such a signal converting apparatus as an integrated circuit it is necessary to take into consideration the signal processing system of the information processing device which is coupled to the input terminal of the signal converting device and the construction of the operation of the display device coupled to the output circuit of the signal converting device. Thus, for example, when fabricating the signal converting apparatus as an integrated circuit, it is necessary to select a suitable type which can satisfy the logic levels (positive logic and negative logic) processed by the information processing device as well as the construction and operation of the display device or display system. The method of processing the logic levels and the construction of the display device or display system are different for different makers of information processing devices, and there is no standard established in the art. For this reason, makers of component parts of the integrated circuits for use in the signal converting apparatus are required to supply various types of the integrated circuits which vary dependent upon the mode of operation of the information processing device so that it is impossible to reduce the manufacturing cost of the integrated circuits by mass production techniques. Factory installation for manufacturing integrated circuits requires a relatively large investment and the process steps for manufacturing the same also requires precise techniques.

In addition, large costs are necessary to develop new art. When considering the depreciation of these expenses, cost reduction is possible only when the integrated circuits are manufactured on a mass production scale.

SUMMARY OF THE INVENTION the signal converting apparatus as integrated circuits.-

Still another object of this invention is to provide an improved signal converting'apparatus including means for preventing some of the display devices from providing a visible display.

Another object of the invention is to provide an improved signal converting apparatus for use in digit display devices in which essential components of the signal converting apparatus can be comprised by insulated gate type field effect transistors and resistors which can be readily fabricated as an integrated circuit.

A further object of this invention is to provide a novel display signal converting apparatus which can be readily used for different types of display apparatus utilizing different combinations of luminous elements representing different letters or digits by mere change of the pattern of the mask used to form the insulated gates of the insulated gate type field effect transistors.

Still a further object of this invention is to provide a novel display signal converting apparatus applicable to information processing apparatus operating on positive or negative logic by merely changing the positions of the insulated gate type field effect transistors comprising the signal converter device. This can also be by merely changing the design of the mask pattern for the insulated gate type field effect transistors.

A further object of this invention is to provide a novel display signal converting apparatus applicable to display devices using luminous elements operated by ON or OFF levels by merely changing the positions of the insulated gate type field effect transistors. This can also be accomplished by changing the pattern design of the mask for forming such field effect transistors.

According to this invention there is provided a signal converting apparatus for converting a bit signal representing predetermined information into a drive signal for operating a display device having a plurality of luminous elements, said display signal converting apparatus comprising 1) signal memory means for storing the bit signal, (2) a first signal converting means including a plurality of bit input lines, a plurality of character output lines, the bit input lines and the character output lines being arranged in a matrix circuit, the first coupling means arranged between the bit input lines and the character output lines to respond to a binary signal impressed upon the bit input lines for producing a character output signal on a predetermined one of the character output lines, (3) means for applying the bitsignal to the bit input lines of the first signal converting means, (4) a second signal converting means including a plurality of character lines respectively connected to the character output lines, a plurality of display drive output lines corresponding to the luminous elements, and second coupling means arranged between the character input lines and the drive output lines to respond to the character output signals applied to the predetermined one of the character lines for producing a drive output signal on a predetermined one of the drive output lines, and (5) means for supplying the drive output signal on the predetermined one of the drive output lines of the second signal converting means to the luminous elements of the display device.

According to this invention there is also provided display signal converting apparatus for converting a bit signal representing predetermined information into av drive signal for operating a display device which operates to selectively display a plurality of different characters by selective combinations of plurality of luminous elements, said display signal converting apparatus comprising (l) a plurality of first drain semiconductor regions extending in parallel on the major surface of a first semiconductor substrate and of the number corresponding to the number of luminous elements of the display apparatus, (2) first source semiconductor regions on the major surface of the first semiconductor substrate in parallel with and in close proximity to the first drain semiconductor regions, (3) aplurality of first load resistors respectively connected to the first drain semiconductor regions, (4) a plurality of first gate metal regions of the number corresponding to the number of characters displayable by the plurality of luminous elements of the display device, the first gate metal regions being disposed at right angles with respect. to the first drain semiconductor regions and to the first source semiconductor regions and are isolated from these regions by an insulator layer for forming insulated gate type field effect transistor elements at the predetermined semiconductor regions between the first drain semiconductor regions and the first source semiconductor regions, (5) a plurality ofparallel second drain semiconductor regions, corresponding to the first metal regions, the second drain semiconductor regions being formed on the major surface of a second semiconductor substrate, one of the ends of the second drain semiconductor regions being connected to the first gate metal region, (6) a plurality of second semiconductor regions formed on the major surface of the second semiconductor substrate in parallel with and in proximity to the second drain semiconductor regions, (7) a plurality of second load resistors respectively connected to the drain semiconductor regions, and (8) a plurality of second gate metal regions for applying the bit signals, the second gate metal regions intersecting at right angles the second drain semiconductor regions and the second source semiconductor regions, and are insulated from these regions by means of an insulator layer for forming a plurality of insulated gate type field effect transistor elements in aplurality of predetermined semiconductor: regions between the second drain semiconductor regionsand the second source semiconductor regions.

BRIEF DESCRIPTION OF THE DRAWINGS Further objects and advantages of the invention will become apparent from the following detailed description taken-in conjunction with the accompanying drawings, in which: Y

1 FIG. 1 is a block connection diagram of one embodiment of the display signal converting apparatus constructed according to the teaching of this invention; FIG. 2v shows an equivalent circuit .of the circuit shown in FIG. 1; I I

FIGS. 3a and .4 are plan views of a portion of the novel display signal converting apparatus fabricated by integrated circuit technique; V

FIGS. 3b and 3c are sectional views of certain por tions of the converting apparatus shown in FIG. 3a;

FIGS. 5 and 6 are sectional views to show different steps of fabricating the integrated circuit;

FIG. 7 is a connection diagram, partly in block form, of the signal memory means and inverter means shown in FIG. 1;

FIGS is a connection diagram illustrating a modified embodiment of this invention;

FIGS. 9 and 10 show block diagrams showing different display circuit systems; a

FIG. 11 shows waveforms of electric signals helpful to explain the operation of the banking circuit;

FIG. 12 shows practical constructions of the load resistors shown-in FIG. 1, and

FIG. 13 shows an arrangement of the luminous segments of the display device adapted to display digits.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 of the accompanying drawing shows one embodiment of the novel converting apparatus for providing visual displays of bit signals of a shift register of a table type electronic computer on a display device of the digit type.

In the embodiment shown in FIG. 1, the result of the operation of an adder is written in a dynamic shift register R,. The information in the dynamic shift register R, is circulated through a feedback circuit 1 connected between the input and output of the dynamic shift register to be stored therein. The number of bits of the dynamic shift register is determined dependent upon the magnitude of the information to be stored therein. For example, when it is desired to store decimal numbers of I4 digits, at least 56 bits are required. The bit signal of the digit to be displayed is sent to a readout register R which comprises four bits and acts to convert a series signal into a parallel signal. The converted bit signals are memorized in signal memories M, to M.,. A

first signal converter D, comprises a group of bit input lines 1, to I a group of character output lines m, to m,,,, and coupling means a,, a a a, respectively responsive to bit signals applied to the group of input lines I, to 1,, for providing a character output signal to the selected one of the character output lines m, to m,,,. Each of the coupling means may comprise an insulated gate type field effect transistor (MOSFET) having a gate electrode connected to a bit input line and a drain electrode connected to a character output line, as shown in FIG. 2. More particularly, a MOSFET a, comprises a gate electrode g connected to a bit input line I, and a drain electrode (I connected to a character output line m,. Character output lines are connected to load resistors r, to r respectively. As schematically shown in FIG. 12, these load resistors may be comprised by MOSFETs. As shown in FIG. 1, bit input lines I, to 1,, of the signal converting device D, are connected to receive the output signals from memories M, to M.,, respectively.

Portions of these output signals are applied to the bit input lines through inverters I, to 1,, respectively.

FIG. 7 illustrates one example of a combination of memories M, to M, and inverters I, to I.,. As shown, pairs of memories and inverters may be formed of MOSFETs h, through h which can be fabricated as an integrated circuit. Register R can also be formed of three delay type flip-flop circuits DF,, DF, and DF, each comprising a MOSFET. Each flip-flop circuit is driven by two phase clock pulses cp, and cp, to shift a binary information signal by the clock pulses cp, and cp In FIG. 7, a signal from register R is stored in an input capacitor 2 of the MOSFET h through a gating MOSFET h, to produce an inverted output of the input signal at the drain electrode of MOSFET h. A signal of the same phase is derived out from the drain electrode of an inverter MOSFET h Returning to FIG. 1, a second signal converter D comprises a group of character input lines m, to m',,,, respectively, connected to corresponding ones of the character output lines m, to m,,,, a group of display drive output lines n to n, disposed at right angles with respect to lines m to m,,, and coupling means disposed to respond to the signals impressed upon input lines m to m' for producing a drive output on predetermined ones of the drive output lines n to ri Again,

as shown in FIG, 2, each of the coupling means comprises a MOSFET having a gate electrode 8 connected to a character input line and a driah electrode connected to a drive output line. For example, a MOSFET b, has a gate electrode g connected to the character input line m, and a gate electrode connected to the drive output line m. Drive output lines connected to the drain electrodes are connected to load resistors r to r respectively. Like the load resistors r, to r connected to character output lines these load resistors r and r can also be made of MOSFETs as shown in FIG. 12. The output signals from drive output lines it, to n of the second signal converter D are applied to drive circuits B to B respectively which are connected to apply operating voltage to the input terminals 9, to p, of a display device T.

The display device T includes eight luminous segments p, to p, which are arranged as shown. As is well known in the art, by selective energization of the luminous segments any one of a group of digits from 0 to 9 can be displayed. There are provided a plurality of such display devices of the number corresponding to the number of digits or of the order of magnitude to be stored in the shift register R Thus for example, where it is desired to display a numericalvalue of 14 digits there are provided 14 display devices. The switching operation of these display devices are effected by a control circuit C For the sake of simplicity, only one display device T is shown in FIG. 1. Actually, however, as diagrammatically shown in FIG. 9, a plurality of display devices T to T,, of the number corresponding to the number of digits to be displayed are provided which are controlled by control circuit C on a time division basis. Alternatively, as diagrammatically shown in FIG. 10, display devices T to T may be selectively operated without utilizing the time division control by providing a plurality of signal memories M, to M,,, first signal converters D to D,,,, second signal converters D to D and driving circuits B, to B',,, each of the number corresponding to the number of digits to be displayed. However, the display system shown in FIG. 9 is more advantageous because it requires a lesser number of component parts.

The display apparatus thus far described operates as follows. Upon receipt of a signal to be displayed by respective bits 1, 2, 4 and 8 of readout register R the signals of respective bits are stored concurrently in respective-signal memories. For the sake of understanding, it is now assumed that bit signals 1, 0, l and 0 representing a decimal digit 5 are stored in memories M M M and M.,, respectively. If level 1 is represented by a voltage-V and level 0 by a voltage of 0, respective memories will'store signal voltages of -V, 0, -V and 0, respectively. These signal voltages will supply V volts, to bit input lines 1,, l l and 1 whereas 0 volts will be supplied to bit input lines 1 l 1 and 1 The voltage of 0 volts applied to bit input lines l l l and 1 turns OFF MOSFETs a a 0 and (1 respectively coupled to these input lines, thereby maintaining the voltage of the output line m at a negative value. In other words, input lines 1 l l and I constitute a NOR input circuit for output line m and the voltage V impressed upon bit input lines l l l and I, will produce a 0 output voltage on all output lines exceptingoutput lines m In this manner, the first signal converter D, is constructed such that it produces an output voltage on only one of the character output lines m to m in accordance with input signal voltages impressed upon its bit input lines I, to 1, inclusive. In the case where bit signals 0, 0, 0 and 0 are applied to register R an output voltage will be provided for only output line m whereas when bit signals are l, 0, 0 and 1, the output voltage will be provided for only output line m Upon occurrence of a signal voltage -V on output line m this voltage turns ON MOSFETs b I2 b b and b connected in a matrix circuit in the second signal converter D whereby drive output voltages are produced on respective output terminals p' p' p,, p, and p',, of the drive circuits B, through B These output voltages cause segments 12,, p p p and p of the display device T to luminesce, thus displaying a digit 5.

Since it is possible to, constitute all components of the above described display signal converting apparatus with MOSFETS, the apparatus can be readily fabricated as an integrated circuit on a semiconductor substrate.

FIGS. 3a, 3b, and 3c illustrate one form of the integrated circuit. As shown in FIGS. 3a3b, the first signal converter D, comprises in pairs of p-type drain semiconductor regions (m d, m d M d) and p-type source semiconductor regions (M s, m s m s) which are formed on one major surface of a N-type silicon semiconductor substrate 10 and extend in parallel with each other, load resistors (r r r respectively connected to the drain semiconductor regions, a p-type semiconductor region 11 for fixing the potential of the source semiconductor regions (m s, m s, M s) to a reference potential E0, a layer of silicon oxide 12 overlying the major surface of the semiconductor substrate 10, and 1 aluminum layers l l .1, overlying the silicon oxide layer 12 at right angles with respect to the drain and source semiconductor regions. As shown in FIG. 3 b, each MOSFET constituting the NOR circuit can be readily formed by making thinner the thick ness of a portion 13 of the silicon oxide layer 12 extending between'drain semiconductor region m d and source semiconductor region m s underlying metal layer 1 than that of the layer 12. For example, the thickness of the portion 13 may be made to be l/ 10 to l/2O of that of layer 12, for example 1,000A. Consequently, portion 13 acts as the insulated gate of the MOSFET to enable channel control between the source and drain electrodes.

Like the first signal converter D the second signal converter D is also fabricated as an integrated circuit on the silicon semiconductor substrate. The second signal converter D comprises n pairs of p-type drain semiconductor regions (n d, n d. n d) and p-type source semiconductor regions (n s, n s. n s), a p-type semiconductor region 15 for connecting one end of the source semiconductor regions (n s, n s. n s) to the source of reference potential E0 and in aluminum layers (1 ,1 l overlying the silicon oxide layer 12, one of the ends of the aluminum layers being connected to the drain semiconductor regions of the first signal converter as shown in FIG. 30. Again, each MOSFET is formed by making a portion of the oxide layer 12 thin.

As shown in FIG. 4, the source semiconductor region may be provided in common for adjoining drain semiconductor regions. With this arrangement, the number of source semiconductor regions can be reduced to one half of that of the drain semiconductor region thereby increasing the density of the elements of the integrated circuit. As above described in connection with FIG. 12, since it is possible to form load resistors r, to r as MOS- FETs, respectively, they can also be formed as a part of the integrated circuit of the silicon semiconductor substrate 10.

Typical process steps of fabricating the signal converting apparatus include:

1. A step of diffusing a p-type impurity into the major surface of an N-type silicon semiconductor substrate for concurrently forming drain regions and source regions for the character output lines, drain regions and source regions for the drive output lines, and the drain and source regions for the load MOSFETS.

2. A step of forming a relatively thick silicon oxide film 17 on the major surface of the silicon semiconductor substrate, as shown in FIG. 5, or of forming a relatively thin silicon oxide film 18 of the thickness sufficient to act as an insulated gate electrode of a MOS- FET, as shown in FIG. 6.

g 3. A step of etching an exposed portion 20 of the silicon oxide film 17 by using an etching mask 19 as shown in FIG. to form the thin portion 13 acting as the insulated gate electrode of the MOSF ET or of depositing an oxide film 22 on the portion 13 of the oxide film 18 acting as the insulated gate by applying a deposition mask 22 on the film 18 as shown in FIG. 6, and

4. A step of'vapor-depositing aluminum on the oxide film 17 or 18 for forming metal layers or strips for the bit input lines and character input lines.

With the novel signal converting apparatus where the construction or mode of operation of the information processing device and the display device are changed, it is possible to simply change the design of the matrix circuit of the signal converting device by merely changing the positions of the MOSFETs without the necessity of changing the array of the diffused semiconductor regions. More particularly, it is only necessary to change the pattern of the mask utilized in the etching or deposition step described in the above described step 3 so that thin oxide films acting as the insulated gates are formed at the desired positions.

In a display signal converting apparatus utilizing MOSFETs, it is necessary to use an etching mask suitable for reducing the thickness of the oxide film at portions 16 in the second signal converter D shown in FIG. 3a.

It is to be noted that the design of the display signal converting apparatus should be changed in accordance with the construction of the display device. More particularly, although in the above description a converting apparatus utilizing luminescent elements combined to form a crisscross bounded by a rectangle has been shown, manufacturers may utilize a display device in which the luminescent elements are combined to form a figure 8 or another letter. For this reason, integrated circuit manufacturers are required to manufacture display signal converting apparatus having matrix circuits suitable for such different display devices. This invention can meet such a requirement by merely changing the pattern of the mask utilized to form the insulated gate of the second signal converting device D shown in FIG. 3. This is extremely advantageous for IC manufacturers because they can manufacture many types of products ordered by customers without the necessity of largely changing the manufacturing steps.

It is also necessary to change the design of the display signal converting apparatus dependent upon whether the logic level processed by the information processing device is positive logic or negative logic. The above embodiment has been described in terms of negative logic in which a potential of 0 volts was designated as a 0 level and -V volts as a I level.

On the contrary, where the information processing device operates on positive logic wherein 0 volts is designated as a 1 level and V volts as a 0 level, it is necessary to provide another type of signal converting apparatus suitable for this system. In accordance with this invention such a change of the matrix circuit can be readily carried out by merely changing the positions of the MOSFETs (the rectangular coordinate of the MOS- FETs) formed in the matrix circuit of the first signal converter D (see FIG. 1) or by changing the pattern of the mask.

Another factor that necessitates the change of the design of the signal converting apparatus for use in display devices involves whether the input level to the drive circuit means for the display devices is at an OFF LEVEL or an ON level. In the embodiment described above, the input level to the drive circuit required to operate the luminescent segments of the display device corresponds to the ON level (0 volts) of the output of the second signal converting device. If it is desired to use an OFF level (-V volts for the input level for operating the luminescent segments this can be readily accomplished by changing the positions of the MOS- FETS included in the second signal converter device. This can also be readily accomplished by changing the pattern design of the mask.

The invention can also provide a display signal converting apparatus including a character suppressor or a blanking circuit means adapted to control the time for applying drive signals to the display drive signals to the display device. Where the display device is of the type wherein its luminous segments are operated by the ON level output (0 volts) from the second signal converter D the blanking circuit is comprised by MOS- FETs e through e coupled to respective character output lines of the first signal converter D On the other hand, where the luminous segments of the second display device D are operated by the OFF level output (-V volts) from the second signal converter D the blanking circuit is comprised by MOS- FETs f, to f coupled to respective drive output lines of the second signal converter D Desired changes of the positions of the MOSFETs of the blanking circuit can be readily accomplished by changing the pattern design of the mask in the same manner as above described. Such a blanking circuit provides novel advantages when incorporated into the display signal converting apparatus of this invention. More particularly, where the signal converting apparatus is constituted by MOS- FETs, there is more or less a delay between the application of bit signals and the generation of the drive signals. This time delay results in a somewhat obscure display where a plurality of display devices are operated on the time division basis by utilizing the combination of a pair of signal converting circuit means and drive circuit means as shown in FIG. 9.

Although the degree of obscurity is different dependent upon the luminescent characteristics of the display device and the characteristics of the control circuit system for the time division system, utilization of the blanking circuit described above can obviate this difficulty.

The operation of one example of the blanking circuit will now be described with reference to FIG. 11. The luminous or operating voltages suppliedto various display devices through the control circuit C on a time division basis are distributed with the time phases as shown inFlG. l'la through 11d. Furthermore, the signals to drive the first, second, third. nth display devices are also supplied insuccession to the display devices through the driving circuit B in the periods of time t t t t respectively. Thus, in the time period of the first display device mainly displays a numeral corresponding to the signal to drive the first display device. However, due to the time delay in transmitting the signal in' the signal converters, the driving signals to drive thedisplay devices are supplied thereto with a delay time 25, whereby in the time period of t the display devices are forced to display numerals other than the numeral to be displayed therein with a result of obscurin'g the visible display. For example, the second display device displays, the numeral to be displayed therein in .a relatively long period and also display the numeral to be displayedin the first displaydevice in the very short period of i whereby the numerals displayed in the second display device become to flash and it makes difficult to read the display numeral. To prevent this, a blanking control'signal voltage Vtp shown in FIG. lle is applied to-a blanking input line q (see FIG. 1) to deenergize the display devices during a period t of the blanking control signal thereby preventing flashing or obscure luminescence of the display devices.

This kind of flashingor obscure luminescenceof the display devices is caused by the time delay or time difference between the voltage supplied to the respective display device through the control circuit device c and the signal voltage supplied in succession to the display devices from the driving circuit device B. Therefore, thevoltages supplied to the respectivedisplay device through the control circuit device are delayed even if the delay time of the signal voltages in the signal converters has been compensated by the provision of the following compensation circuit, so that phenomena such as flashing and obscure lightening of the display devices are caused. The above-mentioned blanking technique is also applicable to this case to overcome the above-mentioned defects.

FIG. 8 shows a compensation circuit for the delay,

time of the signal converters which may be constituted by gating MOSFETs h and signal storing MOSFETs h, included in the drive output circuit of the second signal converter D More particularly, when gating MOS- FETs h,, are rendered conductive by clock pulse cp cuit c is synchronized with the clock pulse cp, supplied to the gates of MOSFETs h If desired, blanking MOS- PET-s [1,, may be connected in series with memory MOSFETs h, for providing the blanking operation. The signal converting apparatus provided with such memory means is especially suitable for use in combination with a display device utilizing high speed digital display devices or semiconductor luminous diodes as the luminous elements.

The blanking circuit can also be used as the character suppress circuit. Where it is desired to prevent the display of a digit of a predetermined order of magnitude or where it is desired not to display'an unnecessary 0 which was displayed at digits of a higher order than the highest digit of integer of the displayed numeral, a blanking signal is applied during atleast the period in which the voltage is applied to the display device through the control circuit 0 for example, during at least the period of t to the MOSFETs constituting the blanking circuit to interrupt the drive input signals for the display devices.

Thus, the invention provides signal converting apparatus having different characteristics dependent upon the types of the display device, logic levels of the information processing device and the input levels of the display drive circuit.'The invention can also provide a signal converting apparatus provided with blanking circuit.

. While the novel signal converting apparatus has been shown and described for use in display devices displaying decimal digits it will be clear that the invention can equally be applied to other display devices for displaying characters such as alphabets, and that many changes and modifications are obvious to one skilled in the art within the true spirit and scope of the invention as defined in the appended claims.

What we claim is:

1. A display signal converting apparatus for converting a bit signal representing predetermined information into a drive signalfor operating a display device having a plurality of luminous elements, said display signal converting apparatus comprising:

1. signal memory means for storing said bit signal,

comprised of a plurality of pairs of field effect transistors connected in series, at the output of each pair of which is provided a corresponding one of a plurality of memory bit output lines;

2. a first signal converting means including a plurality of bit input lines, a plurality of character output lines, said bit input lines and said character output lines being arranged in a matrix circuit, and first coupling means arranged between said bit input lines and said character output lines to respond to a binary signal impressed upon said bit input lines,

I termined one of said character output lines;

. 3. means for applying said bit signal to the bit input lines of said first signal converting means; 4. a second signal converting means including a plurality of character input lines respectively connected to said character output lines, a plurality of display drive output lines corresponding to said luminous elements, and second coupling means. ar-

ranged between said chara'cter input lines and said drive output lines to respond to the character output signal applied to said predetermined one of said character input lines for producing a drive output for producing a character output signal on a predeclaim 1, wherein said blanking means includes a first signal supply line coupled'to said character output lines of said first signal converting means through third coupling means.

3. A display signal converting apparatus according to claim 1, wherein said blanking means includes a second signal supply line coupled to said drive output lines of said second signal converting means through fourth coupling means.

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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3947721 *Jun 20, 1974Mar 30, 1976Matsushita Electric Industrial Company, Ltd.Liquid crystal device
US3947976 *Mar 10, 1975Apr 6, 1976Eric F. BurtisMathematical problem and number generating systems
US4149151 *May 20, 1977Apr 10, 1979Hitachi, Ltd.Display data synthesizer circuit
US4603495 *Sep 19, 1984Aug 5, 1986Stevens John KAlphanumeric display modules
US5373291 *Jan 15, 1992Dec 13, 1994Texas Instruments IncorporatedDecoder circuits
US6005537 *Sep 17, 1997Dec 21, 1999Hitachi, Ltd.Liquid-crystal display control apparatus
US6259421Aug 5, 1999Jul 10, 2001Hitachi, Ltd.Liquid-crystal display control apparatus
US6396464Jun 29, 2001May 28, 2002Hitachi, Ltd.Liquid-crystal display control apparatus
Classifications
U.S. Classification341/99, 257/E27.102, 341/104, 345/33
International ClassificationG09G3/22, G09G3/04, H01L27/112, H03K21/08, H03M7/00
Cooperative ClassificationH03M7/00, H01L27/112, H03K21/08
European ClassificationH03M7/00, H01L27/112, H03K21/08