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Publication numberUS3803594 A
Publication typeGrant
Publication dateApr 9, 1974
Filing dateJul 17, 1972
Priority dateJul 17, 1972
Publication numberUS 3803594 A, US 3803594A, US-A-3803594, US3803594 A, US3803594A
InventorsKlein C, Korta L, Mc Lean M
Original AssigneeJohnson Service Co
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Programmed time division multiplexed coded tone transmission system
US 3803594 A
Abstract
An alarm transmission system for transmitting alarm information provided by a plurality of alarm sources to a central monitor over a common transmission line includes zone monitoring circuits having a code generator for generating a monitor code comprised of a continuous sequence of bits for transmission over the transmission line to the central monitor, alarm multiplexing circuits including alarm storage circuits which provide separate storage locations for storing alarm outputs provided by each alarm source and a sequencing circuit controlled by the alarm data storage circuits in response to the receipt of an alarm output provided by an alarm sensor to generate a plurality of control signals in a predetermined time sequence, including a control signal for enabling an inhibit circuit to inhibit the transmission of the monitor code to the central monitor and a further control signal for enabling an alarm source identification code generator to effect readout of the alarm storage circuits to generate an alarm source identification code comprised of a sequence of coded bits, each bit of which represents the condition of a different alarm sensor, for transmission over the transmission line to the central monitor to enable identification of the source of the alarm.
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K i 9 H ra I Klein et al. A 233 S /erg; 1451 Apr. 9, 1974 m 9 X L/ 57; l v z [54] PROGRAMMED TIME DIVISION [57] riBSTRACT MULTIPLEXED CODED TONE TRANSMISSION SYSTEM [75] Inventors: Carl F. Klein; Lawrence B. Korta;

Michael B. McLean, all of Milwaukee, Wis.

[73] Assignee: Johnson Service Company,

Milwaukee, Wis.

[22] Filed: July 17, 1972 [21] Appl. No.: 272,575

9/1972 LaFalce 340/413 X Primary Examiner-Harold Pitts Attorney, Agent, or Firm-Johnson, Dienner, Emrich,

Verbeck & 'Wagner REMQTE TEJT 0 meme RIVLR s 5/, s50 ALARM E (90: sauna. r GEN. at/v f/ 2 3? LINE An alarm transmission system for transmitting alarm information provided by a plurality-of alarm sources to a central monitor over a common transmission line includes zone monitoring circuits having a code generator for generating a monitor code comprised of a continuous sequence of bits for transmission over the transmission line to the central monitor, alarm multiplexing circuits including alarm storage circuits which provide separate storage locations for storing alarm outputs provided by each alarm source and a sequencing circuit controlled by the alarm data storage circuits in responseto the receipt of an alarm output provided by an alarm sensor to generate a plurality of control signals in a predetermined time sequence, including a control signal for enabling an inhibit circuit to inhibit the transmission of the monitor code to the central monitor and a further control signal for enabling an alarm source identification code generator to effect readout of the alarm storage circuits to gen,- erate an alarm source identification code comprised of a sequence of coded bits, each bit of which represents the condition of a diflerent alarm sensor, for transmission over the transmission line to the central monitor to enable identification of the source of the alarm.

43 Claims,-l3 Drawing Figures A L 30 T SEQUENCE/P m: GEN. I L 50 0:54am: I

New insta l PATENTEDAPR 91w 3.803594 FIG] ALARM 9U TPU T GATE 86 OUTPUT 10/ ALA5RM MONO 98 Fl; 25? I I L 6 ALARM FF 99 v F- OUTPUT I03 "l g FUUU'UUULFL n sm c TIMER n4 puLlos Lmsue r0 TONE 051v Euz a oF SCAN 124x L RE S ET ALL FLIP FLOPS 105 REZET 0005 saw INHIBIT 10f; I

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to remote alarm monitoring systems, and, more particularly, to a multiplexed alarm transmission system wherein alarm information from a plurality of alarm sensors is transmitted to a central monitor over a single transmission line.

2. Description of the Prior Art In security systems, it is frequently necessary to interconnect a multiplicity of alarm sensors to one central monitor. Typically, the alarm sensors are separated by relatively short distances as, for example, when the alarm sensors are employed for detecting unauthorized entry of classrooms in a school, while the central monitor could be a relatively large distance away from any of the sensors as, for example, when located in the school administration building.

.When the distance over which alarm information must be transmitted is great, some form of line supervision is required for the transmission lines which carry such alarm data, the degree of supervision being a function of the level of system security required, To minimize alarm data transmission costs and to enhance the securityof the alarm transmission system when alarm data must be transmitted over long distances, it is desirable to minimize the number of transmission lines which must be connected between the central monitor and the locations of the alarm sensors. Thereforefthere exists a need for a supervised alarm data transmission system which couples multiple alarm sensors to a centr'al monitor over a single secured transmission line while transmission line complexity and costs of associated supervision and alarm transmission circuits are minimized.

'Such system may employ a multiplexing arrangement using either frequency division multiplexing or time division multiplexing techniques to transmit data from a plurality of sources to they central monitor.

Frequency division multiplexing systems require a plurality of tone generators including an individual tone generator for each alarm data source. Alarm data provided by different alarm sources is coded by tones of different frequencies, and the coded tones, representing the data from all of the alarm sources, transmitted simultaneously to the central monitor over a common transmission line. Filter circuits are required at the central monitor to separate the coded tones provided by the different alarm sources in separate signal channels and a separate tone detector in each channel detects the tones transmitted from an associated alarm source.

In time division multiplexing systems, information from a plurality of alarm data sources is transmitted over a common transmission line on a shared time basis. Accordingly, only one tone generator and tone detector are required, and thus, the cost of the data transmission circuits is less than those required in systems employing frequency division multiplexing.

However, the use of time division multiplexing has not found much acceptance in the security area. There is a prevailing feeling that a necessary condition for maximum security requires continuous monitoring of all protected areas.'Thus, any time division multiplexing system which inherently results in a brief interruption between an alarm sensor and the central monitor to provide a time interval for interleaving of the signals from a plurality of alarm sensors has not been well accepted. Part of this disfavor results from the fear that a momentary alarm indication provided by a given sensor may occur between the two instants at which the output of such alarm sensor is sampled and that such alarm indication may not be detected.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a secured intrusion alarm. data transmission system wherein alarm data provided by a plurality of intrusion sensors is transmitted to a central monitor over a common alarm transmission line in order to minimize complexity and both installation and operating costs of the system.

A further object of the invention is to provide a secured data transmission system which utilizes coded tone transmission wherein information provided by a plurality of alarm sensors is transmitted to a central monitor in a programmed time sequence.

Another object is to provide a secured data transmission system which transmits at least two fundamentally different types of alarm information, namely an indication of an alarm and the identification of the source of such alarm.

A further object is to provide an intrusion alarm data transmission system in which the alarm sensors are se-.

lectively operable in either an active or standby mode and wherein data representing the active or standby status of each alarm sensor is periodically transmitted to the central monitor over the alarm transmission line.

Another object is to provide a time multiplexed alarm transmission system which, by virtue of an alarm storage means, maintains essentially continuous surveillance over all alarm sensors.

Another object is to provide an extremely flexible, secured data transmission system which can easily be expanded in terms of both the number of alarm sensors monitored and the amount in types of information transmitted for each alarm sensor.

Yet another object is to provide a secured multiplex alarm data transmission system in which the operation of each alarm sensor can be tested upon command from the central monitor.

in accordance with an exemplary embodiment, the secured intrusion alarm data transmission system provided by the present invention includes zone monitoring means for monitoring the status of a plurality of alarm sensors, each located in a different area to be protected and for effecting the transmission of alarm information provided by the sensors to a central monitor over an alarm line. The zone monitoring means includes alarm multiplexing means having alarm storage means for providing separate storagelocations for storing alarm outputs provided by each sensor and alarm data readout means responsive to alarm outputs provided by one or more of the alarm sensors to effect the transmission of alarm information into the central mon- The zone monitoring means further includes code generator means for generating a monitor code comprised of a known sequence of code bits for transmis- Kiwis e. at.

sion over the transmission line to the central monitor to normally indicate that the transmission line is secure and that all protected areas are secure.

Whenever an alarm indication isprovided by one or more of the alarm sensors, the alarm multiplexing means is operable to substitute the alarm code for the monitor code to indicate the presence of the alarm and permit identification of the source of the alarm at the central monitor. The alarm code includes an alarm indication followed by an alarm source identification code sequence which is comprised of a plurality of bits,

ceived code with the corresponding bit of the reference code generated by the reference code generator means. Under normal conditions, that is, whenever the transmission line and all of the protected areas are secure, the sequence of bits received from the zone monitoring means is identical with the sequence of bits provided by the reference code generator means.

However, whenever an alarm code is being transmitted from the alarm multiplexing means, the alarm code will fail to compare with the corresponding bits of reference code sequence, and accordingly an alarmtindication willbe provided at the central monitor. Thereafter, alarmsource identification decoding means of the central monitor is enabled to be responsive to the bits of the alarm source identification code which represent the conditions ofthe alarm sensors for determining the source of the alarm.

Thus, the alarm transmission system of the present invention provides an alarm indication at the central monitor whenever an alarm is provided by any one or more of the alarm sensors. Thereafter, the origin of the alarm is determined through readout of the alarm storage means to effect the generation of an alarm source identification word comprised of a plurality of bits, each bit of which represents the status of a different alarm sensor.

In a described embodiment of the invention, the code generator means and the reference code generator means are each operable to provide code bits in a known yet pseudo-random sequence. Since the line monitor code thus provided cannot easily be anticipated, the system provides protection from tampering with the' alarm transmission line. Severing of the transmission line or the injection of signals onto the line will cause the system to indicate an alarm.

In accordance with a feature of the invention, the alarm multiplexing means is operable in a programmed sequence during a plurality of time slots. The alarm multiplexing means includes sequencing means which is enabled whenever an alarm output is provided by one or more of the alarm sensors to generate signals during different time slots for controlling the sequencing of operations of the alarm multiplexing means.

The alarm multiplexing means further includes means responsive to a first control output provided by the sequencing means to inhibit the transmission of the monitor code to the central monitor so as to indicate that-an alarm has been provided by one or more of the alarm sensors. Thereafter, an alarm source identification means of the alarm multiplexing means is enabled by a further output of the sequencing means to generate the alarm source identification code.

The sequencing means further provides a delay in the sequencing of operations of the alarm multiplexing means to enable the transmission of the alarm indication to the central monitor and a further delay for enabling the transmission of the alarm source identification code to the central monitor.

After the alarm code has been transmitted to the central monitor, the sequencing means provides control outputs for restoring the zone monitoring means to the idle condition.

In accordance with a further feature of the invention,

the alarm source identification means may include point sequence code generator means which enables preselection of the sequence in which the bits representing the status of the alarm sensors are provided such that the alarm source identification code bits cannot be attributed to a given alarm sensor. A similar point sequence code generator provided at the central monitor allows proper decoding of the point sequence code representing the identification of the alarm sensor providing an alarm output.

The zone monitoring means further includes accesssecure means for permitting the alarm sensors to be selectively operable in either an active or a standby mode and for providing information for transmission to the central monitor to indicate the access-secure status of each alarm sensor.

In a described embodiment of the invention, the

alarm transmission system includes remote test genera-- BRIEF DESCRIPTION OF TI IE DRAWINGS FIGS. 1 and 2, when arranged in a sideby-side relationship, show a block diagram of the multiplexed coded tone transmission system provided by the present invention;

. FIGS. 3-6, when assembled as shown in FIG. 12, show a schematic representation of the zone monitoring circuits and the alarm sensors associated therewith of the system shown in FIGS. 1 and 2;

FIG. 7 is a timing diagram showing the relationships for signals provided by circuits of the zone monitoring circuits shown in FIGS. 3-6;

FIGS. 8-10, when assembled as shown in FIG. 13,

show a schematic representation of the line monitoring circuits of the system shown in FIGS. 1 and 2;v

FIG. 11 is a schematic representation of one of the alarm sensors of the system shown in FIGS. 1 and 2;

FIG. 12 shows how FIGS. 3-6 are to be assembled; and

FIG. 13 shows how FIGS. 810 are to be assembled.

DESCRIPTION OF A PREFERRED EMBODIMENT General Description FIGS. 1 and 2 when arranged in a side-by-side relationship show a block diagram of an exemplary embodiment for a secured intrusion alarm transmission The alarm sources 10 include a plurality of alarm sensors, such as sensors 11-14 shown in FIG. 1, each located in a different area to be protected. Typically the protected areas may be rooms of a building. Each of the alarm sensors 11-14 may, for example, be an intrusion detector which provides an alarm output in response to the detection of an unauthorized entry of an' area protected by such intrusion detector.

The zone "mast fatiguin 2U rscmaearammuifi plexing circuits 21 having alarm data storage circuits 22 and associated output gating circuits 23, and programmed alarm data readout circuits 24. The alarm data storage circuits 22 comprise a plurality of bistable storage circuits, such as storage circuits 25-28 each associated with a different one of the alarm sensors such as alarm sensors 11-14, respectively for storage circuits 25-28. The bistable storage circuits 22, such as storage circuit 25, is set by each alarm output provided by the associated alarm sensor, sensor 11 for storage circuit 25, and will remain set until alarm data indicating that an alarm has been provided by such alarm sensor has been transmitted to the central monitor.

The alarm sensors 1' awaraasmaasaxa an 'asso ciated alarm storage circuits 25-28 via DC supervised lines 31-34, respectively. Such supervision provides for an alarm responsive to a change of more than 5 percent in a DC current which continuously flows in the lines 31-34. Thus, opening or shorting of any one of the lines 31-34 will immediately result in an alarm. Alarm information may be provided in the form of contact closures, as is customary in security systems.

i I The zone max-mag circuits ZG fUEtIierincIutie a monitor code generator 35 which is driven by a clock 36 at a predetermined rate to generate a line supervisory or monitor code, comprised of a known pseudorandom sequence of logic I and logic 0 bits. The monitor code bit sequence provided at the output of the code generator 35 is extended to a tone generator 37 which converts the logic level bits of the line monitor code into tone signals of first and second frequencies coded to represent the monitor code. The sequence of coded tones thus provided is normally continuously transmitted over the transmission line 30 to the transmission line monitoring circuits 40, shown in FIG. 2, and the reception of the monitor code by the line mon- 'itoring circuits 40 indicates that the transmission line is secure.

Referring to FIG. 2, the transmission line monitoring circuits 40 include a tone converter circuit 41, a reference code generator 42 and a code comparator circuit 43. The tone sequence transmitted from the zone monitoring circuits 20 is received by the tone converter cir- I cuit 41 and converted into logic 1 and logic 0 level bits representing the line monitor code generated by code generator 35.

The reference code generator 42 is driven by clock pulses provided by a clock 44 to generate a reference code which is comprised of a known sequence of bits in which each bit is normally identical with corresponding bits of the line monitor code at any given time. The bits of the line monitor code received from the zone monitoring circuits 20 are compared with corresponding bits of the referencecode by the code comparator circuit 43 and' under normal conditions, the bits of the monitor and reference codes which are compared will be the same, indicating that the transmission line is secure and that all protected areas are secure.

Due to the pseudo-random nature of the monitor code, it is highly improbable that the monitor code areas, such as the area protected by alarm sensor 11,

for example, the alarm sensor 11 will provide an alarm output over the DC line 31 which is connected between alarm sensor 11 and alarm storage circuit 25 which is associated with alarm sensor 11. The bistable circuit 25 is normally in a reset condition, providing a first logic level output indicating that the corresponding protected area is secure. The bistable'circuit 25 is responsive to each alarm output provided by alarn sensor 11 to be switched to a set condition, thereby providing a second logic level output indicating an alarm condition for the corresponding protected area.

The outputs of all of the alarm data storage circuits 22, including storage circuit 25, are extended over alarm gates 23a of the output gating circuits 23 to the alarm data readout circuits 24 and whenever an alarm output is provided by one or more of the alarm sensors 10, the logic level-output of the alarm data storage circuit associated with such alarm sensor will enable the alarm data readout circuits 24 to effect transmission of The alarm multiplexing circuits 21 are operable in aprogrammed sequence during seven time slots as summarized in Table I.

4 TABLE I g I A TIME SLOT OPERATION T0 Monitor alarm sensors Tl Inhibit monitor code transmission T2 Transmit alarm indication T3 Initiate alarm source identification T4 Transmit alarm source identification data T5 Reset alarm data storage circuits T6 Reinitiate monitor code transmission During the first time slot T which represents the idle condition for the alarm multiplexing circuits 21, the alarm sensors 10, including alarm sensor 11,, are continuously monitored, and the monitor code generated by monitor code generator 35 is transmitted to the central monitor.

The alarm output provided by any of the alarm sensors, such as alarm sensor 1 1, responsive to an intrusion of the area protected by such alarm sensor is provided during time T0. Such alarm output effects the setting of the corresponding alarm data storage circuit, storage circuit 25 for alarm sensor 11, to provide an enabling output for the alarm data readout circuits 24. The alarm data readout circuits 24, under the control of a sequencing circuit 50, effect the generation of an alarm code which includes an output indicating that an alarm has been provided by one or more of the alarm sensors and an alarm source identification bit sequence for indicating the source of the alarm. The alarm code is substituted for the monitor code during times T1-T6, to permit transmission of the alarm information to the central monitor.

The sequencing circuit 50 is responsive to an alarm output extended thereto over the output gating circuits 23a to provide a series of control signals during time slots Tl-T6, for controlling a tone generator disable circuit 51 and an alarm source identification code generator circuit 52 of the alarm data readout circuits 24.

Thus, for example, assuming alarm sensor 11 provides an alarm output indicating an unauthorized intrusion of the area protected by alarm sensor 11, the corresponding alarm data storage circuit 25 will be set, providing an alarm indicating output during time slot T0. The alarm indicating output of storage circuit 25 is extended over the alarm gates 23a of the output gating circuits 23 to the sequencing circuit 50 of the alarm data readout circuits 24. The sequencing circuit 50 is responsive to such output to generate a control signal at time T1 for the tone generator disable circuit 51 which is operable to disconnect the output of the code generator 35 from the input of the tone generator 37 during times TL-T6, thereby interrupting the transmission of the monitor code to the central monitor and to inhibit the tone generator for a predetermined time interrupting the transmission of tone signals to the central monitor during time slot T2.

At time T3, the sequencing circuit 50 provides an output for enabling the alarm source identification code generating circuit 52 to generate an alarm source identification code for transmission to the central monitor during time T4. The alarm source identification circuit 52 may comprise a parallel-to-serial converter which scans the alarm data storage circuits, including circuits 25-26 to provide a logic level output as each alarm data storage circuit is scanned, with each output provided representing the condition of the alarm storage circuit being scanned.

The alarm data storage circuits 22 may be scanned in sequence such that successive bits of the point identification code represent the data stored in consecutive storage circuits 25, 26, 27, 28, or, alternatively, a point sequence generator circuit 57 may be employed for controlling the alarm source identification circuit 52 to scan the data storage circuits 22 in a nonmore difficult to a person attempting to compromise thealarm transmission system.

The bits of the alarm source identification code provided by the identification code generator 52 are extended to the tone generator 37 to effect the generation of tone signals of first and second frequencies in a sequence coded to represent the alarm source identification code. The tone sequence provided by the tone generator is transmitted to the central monitor over the transmission line 30.

Referring to FIG. 2, whenever the transmission of tone signals is interrupted as the result of an alarm output provided by one or more of the alarm sensors 10, the loss of tone, when detected at the central monitor, will cause the code comparator circuit 43 of the line monitoring circuits 40 to provide an output for enabling an alarm circuit 46 of an alarm module 45 to indicate an alarm condition for one or more of the protected areas. Thereafter, the tone sequence representing the alarm source identification code is received by the tone converter 41, converted to a logic level sequence and passed to' an alarm source identification decoder 47 to enable decoding of the alarm source identification bit code sequence transmitted to the central monitor from the zone monitoring circuits 20 and the identification of the source of the alarm.

The alarm source identification decoder circuit 47 may comprise a serial-to-parallel converter which is operable to gate successive bits of the alarm source identification code to different alarm circuits, including alarm circuits 48a-48d, of the alarm module 45. A separate alarm circuit, such as circuits 48a48d is provided for each ofv the alarm sensors, such as alarm sensors 11-14 respectively. The bits of the alarm source identification code which represent the status of an alarm sensor, such as alarm sensor 11, which is providing an alarm output, will enable the alarm circuit associated with such alarm sensor to provide an alarm indication at the central monitor to thereby indicate the source of the alarm. It is pointed out that if a point sequence code generator 57 is used at the zone monitoring circuits 20 to modify the sequence in which the alarm data storage circuits 22 are scanned, the alarm source identification decoder circuit 47 would have associated therewith a further point sequence generator 49, which is identical with point sequence generator 57, for enabling proper decoding of the alarm source identification code.

Referring again to FIG. 1, after all of the point identification code bits have been transmitted to the central monitor, the sequencer circuit 50 provides an output during time slot T5 for effecting the reset of all of the alarm storage circuits 22 and thereafter at T6, reset of the code generator disable circuit 51, thereby returning the alarm multiplexing circuits 21 to the idle condition and reinitiating the transmission of the monitor code to the central monitor.

In the foregoing general description of the alarm transmission system, the alarm sensors l0 and associated zone monitoring circutis 20 were described as being operable in a secure mode, and as such, were responsive to the detection of any human movement within the corresponding protected area to provide an alarm output for effecting the registration of an alarm at the central monitor. During certain periods of time, however, it may be necessary to permit movement of an authorized person within a given protected area while the alarm system is energized. For example, when i 9 t a the alarm transmission system is used in an application for monitoring the conditon of rooms in a school, an authorized person, such as a janitor or a repairman, should be allowed access'to the protected area at night.

switch, which is located at the site of the alarm sensor i 11, as for-example, on a wall outside of a room protected by alarm sensor 11. The access-secure-switch 61 controls the associated alarm sensor 11 to be operable in either a secure mode of an access mode. Whenever the switch 61 is set in the secure position, the alarm sensor 11 will be responsive to any human movement within the area protected by the alarm sensor 1 1 to provide an alarm output indicative of the detection of an unauthorized intruder within the protected area, and

the movements of such intruder will cause the registration of an alarm at the central monitor in the manner described in the foregoing.

However, when the access-secure switch 61 is set to the access position, the alarm sensor 11 associated with access-secure switch 61 will be disabled and will not respond-to movements detected with the protected area.

In order to enable the access-secure status of the alarm sensors, including alarm sensors 11-14;10 be made known atthe central monitor, the'zone monitoring circuits 20 include access-secure conditionmonitoring circuits 65 which periodically scan the access-secure switches 60 and generate a sequence of tone signals coded to represent the status of all of the access-secure switches 60 and hence of the alarm sensors 10.

The access-secure condition monitoring circuits 65 include a scanner circuit 66 controlled by clock pulses provided over a pulse divider circuit 67 from the clock 36 which controls the code generator 35. Since the access-secure information does not have the same degree of importance as the alarm information provided by the alarm multiplexer 21, the conditions of the accesssecure switches 60, including switches 61-64, are scanned at a slower rate than the rate at which the bits of the monitor code are generated. The slower rate is provided through the use of the clock pulse divider circuit 67. The access-secure switches 60, including access-secure switches 61-64, are connected to the scanner 66 over a cable 68 which provides separate paths for each switch to the scanner 66. Each access secure switch is adapted to provide a first output over cable 68 when such switch is set in the access mode position and a second output when such switch is set in the secure mode position.

As each access-secure switch is scanned, the scanner 66 extends the output representative of the condition of the switch being scanned to an access-secure tone generator 69 which provides a tone output ofa first frequency for each output representing an access mode position for a switch being scanned, a tone output of a second frequency for each output representing a secure mode for a switch being scanned. The tone sequence thus provided represents the access-secure status of all of the switches 60 being scanned. The access-secure switches 60 may be scanned sequentially, i.e., switch 61, then switch 62, 63, 64, or alternatively, through the use of a point sequence code generator 70, the switches 60 may be scanned in a non-consecutive yet known sequence and accordingly, the access-secure information as transmitted from the zone monitoring circuits 20 could not be attributed to a specific alarm sensor location.

In order to enable simultaneous transmission of the tone sequence representing access-secure data provided by the access-secure condition monitoring circuits 65 to the central. monitor over a common transmission line, the frequencies of the tone signals provided by the tone generator 69 of the access-secure monitoring circuits 65 are chosen to be different from the frequencies of the tone signals provided by the tone generator 37 of the alarm multiplexer circuits.

The tone sequence representing the access-secure code generated by the access-secure monitoring cir-- cuits 65 is transmitted over transmission line 30 to the central monitor and is received by the tone converter circuit 41 of the transmission line monitoring circuits 40. The tone converter circuit 41 converts the received tone sequence to a sequence of logic. level signals and extends the sequence of logic level bits to an accesssecure decoder circuit 71 which routes each bit of the access-secure code to a different alarm circuit of the alarm module 45. The access secure decoder 71 is controlled by clock pulses supplied thereto over pulse divider 72 from clock pulse generator 44 and is operable at the same rate as the scanner 66 at the zone monitoring circuits 20. I

The alarm module 45 includes a separate accesssecure indicator for each alarm sensor. The accesssecure indicators are enabled as a function of the bits of the access-secure code received from the zone monitoring circuits 20. Thus, as the sequence of bits representing the status of the access-secure switches 60, and correspondingly alarm sensors 10, is received, the access-secure decoder 71 (under the control of the point sequence code generator 73, if point sequence code generator is used at the zone monitoring circuits 20) will provide a separate output for each alarm circuit of the alarm module 45, including alarm circuits 48a-48d corresponding to alarm sensors 11-19, respectively, such that the alarm circuit associated with a given alarm sensor will provide a first indication whenever the corresponding alarms sensor is operating in the secure mode and a second indication whenever the corresponding alarm sensor is operating in the access mode.

The alarm transmission system also includes provision for remote testing of the alarm sensors 10 to determine if all of the alarm sensors are operating properly. Accordingly, a remote test signal generator 74 at the central monitor is operable, when enabled, to transmit a test command signal over the transmission line 30 to the alarm multiplexing circuit 21 at the locations of the alarm sensors 10. The frequency of the test signal is different from the frequencies of the signals provided by the tone generator 37 of the alarm multiplexing circuits 21 and the tone generator 69 of the access-secure condition monitoring circuits 65.

The alarm multiplexing circuits 21 include a test signal detecting circuit 75 which receives the test signals and is responsive to each test signal extended thereto to extend enabling signals to each of the alarm sensors to simulate intrusions-in the areas protected by the alarm sensors 10.

Each of the alarm sensors 10, including sensors 11-14, is responsive to the enabling signals extended thereto to provide an alarm output. The alarm outputs thus provided effect the generation of an alarm code by the alarm multiplexing circuits 21 for transmission to the control monitor to register appropriate alarm indications at the central monitor in the manner set forth in the foregoing.

DETAILED DESCRIPTION A schematic representation of the zone monitoring circuits and the alarm sensors 10 associated therewith is shown in FIGS. 3-6 when arranged in a side-byside relationship as shown in FIG. 14. For'purposes of illustration of the operation of the zone monitoring circuits 20, including the slarm multiplexing circuits 21 and the access-secure condition monitoring circuits 65 itis assumed that the zone monitoring circuits 20 monitor twenty alarm sensors, including sensors 11-14 shown in FIG. 3.

The nature of many commercially available alarm sensors is such that separate alarm indications (as represented, for example, by changes in relay contact states) are available for intruder detection and for supervisory indication of sensor component malfunctions. The alarm multiplexing circuits 21 include alarm storage circuits 22 which provide separate storage for both types of sensor information.

Accordingly, the alarm storage circuits 22 include flip flops 25a-28a which store intrusion alarm outputs provided by sensors 11-14, respectively in response to the detection of an unauthorized entry of the areas protected by sensors 11-14, and flip flops 25b-28b, which store supervisory alarm outputs provided by sensors 11-14 as the result of component malfunctions of sensors 11-14.

' The intrusion alarm output of sensor 11 is connected over a DC supervised line 31a and a NOR gate 81 to the set input of the alarm flip-flop 25a associated with sensor 11. The supervisory output ofthe sensor 11 is connected over a DC supervised line 31b and a NOR gate 82 to the set input of the supervisory flip flop 25b associated with sensor 11.

Similarly, the alarm outputs of sensors 12-14 ar connected over respective D.C. supervised lines 32a-34a and NOR gates 81a-81c to the set inputs of alarm flip flops 26a-28a, and the supervisory outputs of sensors 12-14 are connected over respective D.C. lines 32b-34b and NOR gates 82a-82c to the set inputs of supervisory flip flops 26b-28b, respectively.

A logic I level signal on lines 31a-34a or 31b-34b represents a normal condition, and a logic 0 level on one or more of the lines 310-340 or 31b-34b indicates that an intrusion or supervisory alarm indication is being provided by the sensor connected to such line.

An enabling signal at a logic 0 level is normally extended over conductor 83 from the alarm data readout circuits 24 to each of the NOR gates including gates 81, 81a-81c, 82a-82c, 82. Accordingly, whenever one or more of the alarm sensors, such as alarm sensor 11,

' provides an intrusion alarm output over conductor 31a 12' ever NOR gate 81 is enabled, the alarm flip flop 25a will be set and whenever NOR gate 82 is enabled the supervisory flip flop 25b will be set. The alarm flip flop 25a and the supervisory flip flop 25b, when set in response to an alarm indication by the associated sensor 1 1, will remain set, storing such alarm indications until reset. by the alarm data readout circuits 24. Thus, an alarm indication provided by any of the alarm sensors 10, such as sensor 11, will be stored in the alarm storage circuits 22 until the alarm indication has been transmitted to the central monitor.

Each of the alarm storage flip flops, including flip flops 25a-28a, and each of the supervisory flip flops,

including flip flops 25b-28b, normally provide a logic 0 output whenever associated alarm sensors 11-14 are not providing an alarm output. j

The outputs provided by the alarm storage flip flops 25a-28a and the supervisory flip flops 25b-28b are combined by alarm gates 23a, including gates-84-86, of the output gating circuits 23. For example, the outputs of the alarm flip flops, such as flip flops 25a-28a, are extended via cable 87 to separate inputs -of a NOR gate 84. The outputs of the supervisory flip flops, such as flip flops 25b-28b, are extended via cable 88 to separate inputs of a NOR gate 85. The outputs of NOR gates 84 and are individually connected to inputs of a NAND gate 86. Whenever all of the alarm storage flip flops, including flip flops 25a-28a, and all of the supervisory flip flops, including flip flops 25b-28b, are in a reset condition, representing an idle condition for the alarms multiplexing circuits 21, NOR gates 84 and 85 will be enabled to thereby enable alarm gate 86. NOR gate 84 will be disabled to thereby disable alarm gate 86 whenever an alarm output is stored in one or more of the alarm flip flops, and NOR gate 85 will be disabled to thereby disable alarm gate 86 whenever an alarm output is stored in one or more of the supervisory flip flops. The alarm multiplexing circuits 21 are operable in the alarm mode whenever alarm gate 86 is disabled.

Whenever alarm gate 86 is disabled, gate 86 provides an output which enables the alarm data readout control circuits 24 (FIG. 6) to generate an output indicating that an alarm has been provided andto thereafter effect readout of the alarm data stored in the alarm data storage circuits 22 and the transmission of such data to the central monitor to permit identification of the source of the alarm.

CODE GENERATOR Whenever all of the protected areas are secure and all of the alarm sensors, such as alarm sensors 11-14, are operating properly, the alarm multiplexing circuits 21 are operable in the idle mode during time slot TO, and accordingly, the monitor code generated by the monitor code generator 35 shown in FIG. 6, is transmitted over the transmission line 30 to the central monitor.

One code generator suitable for this purpose is described in the copending application U.S. Ser. No. 193,450 of John C. Donovan, Ramesh Krishnaiyer and Frank J. Esser, which was filed on Oct. 28, l97l.

In an exemplary embodiment, the code generator 35 includes a four stage shift register 90 having feedback connections over conductors 91 and 92 from the first and fourth stages, respectively, connected through an Exclusive OR circuit 93 to the input of the first stage. The Exclusive OR circuif 93 provides a logic output whenever the two inputs to the Exclusive OR circuit are at the same logic level, and provides a logic 1 output whenever the inputs are at different logic levels. Code generator 35 preferably includes at least a sixteen stage register and may be as much as a thirty-two stage register capable of generating a pseudo-random sequence of bits, the length of the sequence being given by the relationship 2"l, where N is the number of lo stages which comprise the shift register 90 of the code generator circuit 35. In thepresent example, for convenience only, a four stage register 90 is shown, and bits are provided.

To illustrate the operation of the code generator 35, it is assumed that initially all stages of the register 90 store logic 1 level bits and that the register 90 is there'- after cycled under the control of clock pulses provided by a clock pulse generator 36. The sequence of words given in Table 11 will appear in the stages of the shift register 90 as successive clock pulses are provided.

Since initially the first and fourth stages both contain binary ones, the Exclusive OR circuit 93 provides a logic 0 output which is gated into the first stage of the shift register 90 with receipt of the first clock pulse as can be seen in Table II. The clock pulse also shifts the logic ls from the first to third stages to the second to fourth stages, respectively. When the second clock pulse is receivcd,'the outputs of the first and fourth stages are different, and accordingly the Exclusive Or" circuit 93 will provide a logic 1 output which will be gated into first stage of the shift register 90.

The random bit sequence generated by the code generator 35 is extended to an input of an AND gate 94 which has a second input connected to the output of an alarm flip flop 99 of the tone generator disabling circuit 51.

Under normal conditions, that is, whenever no alarm indications are being provided by the alarm sources 10, the alarm flip flop 99 is set, providing an enabling input for AND gate 94 whereby AND gate 94 follows the bits ofthe monitor code provided by code generator 35 and provides a logic l level output for each logic 1 level bit of the monitor code sequence and a logic 0 level output for each logic 0 level bit of the monitor code sequence.

The sequence of logic 1 and logic 0 level bits provided at the output of the AND gate 94 is extended over an OR gate 95 to the input of the tone generator 37.

The tone generator 37 may comprise a conventional frequency shift keyed oscillator (FSK) which normally provides a tone output of a first frequency Fa, whenever a control signal at a logic 0 level is supplied to the input of the oscillator circuit. The oscillator circuit is responsive to a control signal at a logic 1 level to provide a tone output which is shifted in frequency by a predetermined amount Fa F0 providing a signal of a second frequency Fb. Thus, the FSK oscillator is responsive to coded sequence of logic 1 and logic 0 level bits supplied thereto by the code generator 35 to. provide tones of frequencies Faand Fb in a sequence coded to represent the bits of the monitor code for transmission to the central monitor over the transmission line 30.

The transmission line 30 may, for example, comprise a pair of standard 4 KHz bandwidth telepone lines.

Since such lines have a transmission frequency range of 500 Hz to 3K1-1z, the base frequency Fa of the oscillator and the second frequency Fb are selected to be within the range of 500 Hz to 3KHz. v

The output of the tone generator 37 is connected to an input of a summing amplifier 96, the output of which is connected to the transmission line 30 to pass the tone sequence to the line 30 for transmission to the central monitor. The monitor code tone sequence will be transmitted to the central monitor as long as all the protected areas are secure.

On the other hand, whenever an alarm output is provided by one of the alarm sensors 10, such as alarm sensor 11, the associatedalarm flip flop 25a for sensor 11 will be set, providing a logic 1 output which is extended via conductor 87a of cable 87 to NOR gate 84, enabling gate 84. Whenever gate 84 is enabled, the gate 84 provides a logic 0 output which disables alarm gate 86. The logic 1 output provided whenever NAND gate 86 is disabled, is extended to the sequencing circuit 50 of the alarm data readout circuits 24.

Sequencing Circuit ing time slots T1-T6 for controlling the operation of the alarm data readout circuits 24 while the alarm multiplexing circuits 21 are operable in the alarm mode. The logic timing elements 101-106 may, for example, be monostable multivibrators of the type SN74l2l commercially available from Texas Instruments.

Referring to the timing diagram given in FIG. 7, in response to an alarm output provided by alarm sensor 11 over line 31a during time slot TO, NOR gate 81 will be enabled, providing a logic I level output (shown in line 1 of FIG. 7). The logic 1 level output provided by gate 81 sets the alarm storage flip flop 250 which then provides a logic 1 level output (line 2, FIG. 7) to effect enabling of alarm gate 86. The output I of gate 86 (shown in line 3 of FIG. 7) is extended to a monostable circuit 101 of the sequencing circuits 50 which after a short transition delay provides an output (FIG. 7, line 4) over conductor 107 defining time slot T1, forenabling the alarm monostable circuit 98 and the alarm flip-flop 99. t

The alarm monostable circuit 98 when enabled, provides an output (line 5, FIG. 7) of a predetermined duration over conductor 108 which output disables the tone generator 37 and inhibits the generation of a tone output by the tone generator 37 for the duration of the monostable circuit 98 as indicated in line 14 of FIG. 7. Such absence is indicative of an alarm condition at the zone monitoring. circuits 20 as will become apparent hereinafter.

The enabling signal provided by monostable 101 over conductor 107 is also extended over conductor 107a to alarm flip flop 99, resetting flip flop 99 providing a logic output over conductor 109 as shown in line 6 of FIG. 7. The logic 0 outputprovided by the alarm flip flop 99 over conductor 109 disables AND gate 94 to thereby preclude the passage of code bits provided by the code generator 35 to the tone generator 37. The output on conductor 107 is also extended to a monostable 102 which provides a delay during time slot T2, for the duration of the output of the monostable circuit 98, to permit transmission of the alarm condition, as indicated by a loss of tone, to the central monitor.

The output of monostable 102 is extended to a first input of an AND gate 110 which has a second input provided by the output of monostable circuit 98 over conductors 108 and 108a and an inverter 1081;. Gate 1.10 will be enabled when the monostable 98 times out. At such time, the output 111 of gate 110 will be extended to a monostable 108 which provides an output (line -7, FIG. 7) over conductor 112, defining tinre slot T3, for enabling the alarm source identification-code generating circuit 52. The output of monostable 103 is also extended to an input of monostable circuit 104 enabling monostable 104 to provide a logic I level output which is extended to an input of an AND gate 133.

Alarm Source Identification Circuit The alarm source identification code generating circuit 52 is operable to effect readout of the contents of the alarm flip flops, such as flip flops 25a-28a, and the supervisory flip flops, such as flip flops 25h-28h which comprise the alarm storage data circuits 22. The outputs of all the alarm data flip-flops 22 are extended over output identification gates 23b to the alarm source identification generator circuit 52.

The output identification gates 23b comprise a plurality of OR gates, including OR gates 120-123 shown in FIG. 3. The output identification gates 23b provide a separate OR gate for each pair of alarm data storage flip flops, the output of each OR gate providing a scan point for the data stored in an associated pair of flip flops. Thus, for example, the outputs of the alarm storage flip flop 25a and the corresponding supervisory storage flip flop 25]) associated with alarm sensor 11 are connected to separate inputs of OR gate 120. Similarly, the outputs of alarm flip flop 26a and supervisory storage flip flop 26b, associated with alarm sensor 12, are connected to inputs of OR gate 121, etc.

Each output identification gate, such as gates 120-123, provides a logic 0 output whenever both inputs are at logic 0 level (representing an idle condition for the corresponding alarm sensor) and a logic l output whenever either output is at a logic I level (representing an alarm condition for the corresponding alarm sensor).

I The alarm source identification code generating circuit 52 comprises a paralIel=to-serial converter, which is comprised of a multi-stage shift register 124 and a plurality of gate circuits 129, including AND gates 125-128 shown in FIG. 4 and an OR gate 130. In the present example, wherein the data stored in 20 pairs of flip flops, such as flip flops 25a and 25b, is to be readout, the alarm source identification code generating circuit 52 includes 20 AND gates 129, four of which are shown in FIG. 4, each AND gate being individually associated with one of the output OR gates 23b.

The output of each of the OR gates 23b is individually extended to an input of a different one of the AND gates 129 of the alarm source identification code gencrating circuit 52. For example, the outputsof OR gates -123 are individually connected to first inputs of AND gates -128, respectively. The outputs of the AND gates 129 are individually connected to a separate input of OR gate 130.

In an exemplary embodiment, the shift register 124 comprises a 24 stage shift registerconnected as a ring counter having the output stage 124x fed back to the input stage 124a. Each of the stages of the register 124, including stages 124a-1242 and 124v-124x, shown in FIG. 4, have clock inputs connected to an output of an oscillator circuit 117 to receive clock pulses provided by the oscillator 117 whenever the oscillator 117 is enabled. The oscillator is enabled at time T3 by an output extended to an input of the oscillator 117 over conducv tor 112 from monostable'circuit 103.

An output 114a of the first stage 124a of the register 124 is connected to an input of a sync pulse generator circuit 114. The sync pulse generator circuit 114 may, for example, be a monostable circuit operable when enabled to provide a pulse (shown on line 9 of FIG. 7) of a predetermined duration, the duration of three clock pulses in the present example. The sync pulse, provided by sync pulse generating circuit 114, is extended over OR gate 130, a pulse line 116 and or gate 95 to the input of the tone generator 37. The sync pulse enables the tone generator 37 to generate an output tone at frequency Fb, for example, (as indicated in line 14 of FIG.

'7), the duration of the tone being determined by the width of the sync pulse provided by the sync pulse generating circuit 114. v

The sync tone is transmitted to the central monitor over the transmission line 30 to enable the alarm source identification decoder circuit 47 of the line monitoring circuits 40 to be responsive to the bits of the alarm source identification code provided by the alarm source identification code generating circuit 52.

Intermediate stages of the register including stages 124d, 124e, 124v and 124w shown in FIG. 4, have outputs individually connected over a point sequence code generator 57 to second inputs of a different one of the twenty AND gates, gates 125-129, respectively. An output 133a of the last stage 124x of the register 124 is connected to an input of AND gate 133 which has a second input connected to the output of monostable circuit 104. i I

In operation, one of the stages of the ring counter 124 normally contains a logic 1 level bit, and the remaining stages normally contain logic 0 level bits. The logic I level bit, which is assumed to be initially stored in the last stage 124): of the register 124 is shifted to the first stage 124xa of the register 124 when the first clock

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Classifications
U.S. Classification340/518, 340/554, 340/534, 340/512, 340/535, 340/515, 340/524, 340/533
International ClassificationG08B25/00, G08B25/04, G08B25/01
Cooperative ClassificationG08B25/00, G08B25/04
European ClassificationG08B25/04, G08B25/00
Legal Events
DateCodeEventDescription
Mar 8, 1982ASAssignment
Owner name: JOHNSON CONTROLS INTERNATIONAL, INC., 229 SOUTH ST
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:JOHNSON SERVICE COMPANY, A CORP. OF DE.;REEL/FRAME:003962/0639
Effective date: 19820302