|Publication number||US3809952 A|
|Publication date||May 7, 1974|
|Filing date||Jun 21, 1971|
|Priority date||Jun 21, 1971|
|Also published as||CA957748A1, DE2229053A1, DE2229053C2|
|Publication number||US 3809952 A, US 3809952A, US-A-3809952, US3809952 A, US3809952A|
|Inventors||M Eisenberg, W Harmon|
|Original Assignee||Burroughs Corp|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Referenced by (4), Classifications (11), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
United States Patent 1191 1111 3,809,952 Eisenberg et a1. I May 7, 1974 1 APPARATUS REDUCING THE POWER 3,614,526 10/1971 Lanning 315/169 R REQUIRED FOR SCANNED DISPLAY DEVICES Assignee:
Burroughs Corporation, Detroit,
June 21, 1971 Appl. No.: 154,731
............ 315/169.TV, 315/169 T H05b 39/00 Field of Search 315/169 C, 168 C, 170 C,
315/169 T, 169 TV References Cited UNITED STATES PATENTS Display Device Primary Examiner--Nathan Kaufman Attorney, Agent, or FirmRobert A. Green; Edward G. Fiorito; Paul W. Fish  ABSTRACT Apparatus is disclosed reducing the power dissipated internally and externally during the scanning of display devices having a plurality of gas-filled cells and including gas communication channels extending between adjacent columns of cells. In the illustrated display device, internal scanning of the display cells is accomplished by causing a preferential transfer of gaseous discharges from column to column in the device. The operating apparatus includes a sequential threephase cathode driving circuit having a pre-biasing circuit which dissipates less power in its operation and is not interfered with during resetting of the panel. A pulse-operated control circuit is provided for controlling the current in scan anodes in'the device in synchronism-with the cathode control signals. The current and power applied to the cells each cycle is reduced after initial activation of the cells to a lower sustaining level.
4 Claims, 6 Drawing Figures 3.809.952 SHEET 3 0F 4 h @250 @520 m? mm om- 5 a v NR 5 mm PATENTEUMY 7 1914 w fig @AQ WI? 09 @Q L maxi Bi @Q a:
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WHhcm J HQrmor Jr;
W ATTORNEY 1 APPARATUS REDUCING THE POWER REQUIRED FOR SCANNED DISPLAY DEVICES BACKGROUND OF THE INVENTION This invention relates to low power scan control apparatus for operating multiple element display devices. More particularly, the invention relates to pulseoperated current source means for the scan anodes and low power prebias circuitry for the cathodes of gas discharge display panels.
Display panels having a plurality of gas-filled cells within the body of the panel have been available commerically for some time. One such device is known as the SELF-SCAN panel display, described in Ogle and Holz, Ser. No. 850,984, filed Aug. 18, 1969.
In the SELF-SCAN panel display there is a layer of scan cells having associated scan anodes and cathodes, and a layer of display cells having an array of display anodes which cooperate with the same cathodes. Gas communication channels extend between selected ones of the scanning cells to provide a selected flow of ex cited gas particles from activated cells to adjacent cells for preferential transfer of glow discharge between them. This glow transfer permits internal scanning of the columns of scan cells in the panel which greatly reduces the amount of drive and selection'circuitry necessary for operating the device. Both the cost of the dis play and the amount of power required for the display is thus reduced by this reduction in external drive and selection circuitry.
These gas discharge devices, however, still require a considerable amount of power for operation, particularly when they are enlarged to increase the number of rows and columns of cells. It would be desirable to re duce the power dissipated in such display panels and in the attendant circuitry in order to make battery operation more feasible in portable equipment where a limited amount of energy is usually available.
A suitable drive apparatus for such a panel display has previously been illustrated and described in Eisenberg et al., Ser. No. 21,756, filed Mar. 23, I970.
The cathodes of the device were driven in groups by a driver of three or more phases and each group was independently pre-biased. Each of the rear scan anodes was coupled by a series load resistor to a common ref erence potential terminal which, together with the cathode drivers, determined the amount of current and power applied to the cells during scanning.
Under some circumstances, the amount of power dissipated in the pre-bias circuitry and in the display device itself is undesirable. The power dissipated within the body of the display device, however, is usually determined by the amount of voltage applied for initially establishing the gas discharge in the cells. Also, prebiasing of the cathodes at a point between the cathode and the anode ON potentials is desirable, even though it consumes a considerable amount of power outside the actual display device.-
SUMMARY OF THE INVENTION Accordingly, an object of the subject invention is to reduce the amount of power required for operating scanned display devices having a plurality of lightproducing cells.
Another object of the invention is to reduce the amount of power dissipated both internally and externally during the scanning of display devices having a plurality of gas-filled cells.
In accordance with the invention, there is provided scan control apparatus for multiple: element display devices, which includes a low power pre-biasing circuit common to the cathodes of the device and coupled for pre-biasing a reset cathode in the device. but functionally independent of it. The cathodes of the display are pre-biased independent of the reset cathode bias connection and is not disturbed during resetting of the device. Also included is a pulse-operated circuit for controlling the current in the scan anodes in the device during scanning. The pulsed control circuitfor the scan anodes is synchronized with the cathode control circuitry and reduces both the current and the power applied to the cells after initial activation of them. This lowers the operating temperature of the display device and also increases the contrast ratio between the fully energized display cells and the rear scanning cells when energized at the low power level.
DESCRIPTION OF THE DRAWINGS Other features and advantages of the invention are made clear inthe following detailed description and in the accompanying drawings wherein:
FIG. 1 is a perspective view ofa multiple-element display panel with which the invention may be utilized;
FIG. 2 is an exploded view and FIG. 3 is a sectional view of such a display panel;
FIG. 4 is a schematic representation of a display panel with its attendant control electrodes and matrix array of display cells;
FIG. 5 is an electrical schematic circuit diagram of an exemplary low power apparatus. for operating a scanned display panel according to the invention; and
FIG. 6 is a timing diagram which illustrates operating signal waveforms at selected points in the apparatus.
DESCRIPTION OF THE PREFERRED EMBODIMENTS The illustrated apparatus is provided for operating display cells in a display device having an array of similar light-producing cells which are successively scanned in groups. It is particularly useful for operating display panels such as those described in the patent application Ser. No. 850,984.0f Ogle and Holz and in the patent application Ser. No. 855,448 of J. A. Ogle, both filed Aug. 18, I969. The display device is shown and described herein as panel 10. The panel may have, substantially any desired size and shape, and'it may include substantially any number of gas-filled display cells of the like. It also contains any suitable ionizable gas such as neon, argon, xenon, etc., singly or in combination, and usually a vapor of a metal suchas mercury to reduce cathode sputtering.
Display panels having different numbers of cells appear in the various figures for illustrating the display device and the invention. The panel shown in FIG. 1 has six cathode columns 111-1 to 113-2 of five cells each and the structure of FIGS. 2 and 3 has five cathode columns 50 of four cells each. A greater number of cells are included in the schematic representation of the panel and the external connectionsfor scanning its cells in FIGS. 4 and 5. The display cells may be of any desired shape such as round (FIGS. 2, 3 and 5) or rectangular (FIG. 4).
Referring to FIGS. 1 and 4 a display panel 10, operable in accordance with the invention, includes an insulating housing of glass, ceramic, or the like having a plurality of display control electrodes 11, 12, formed in an upper layer thereof and scan electrodes 21, 22, formed near the base. They are preferably wires used as display control anodes and scan supporting anodes, respectively, in the operation of the device.
' The cathode electrodes 111-1, 112-1, 113-1, 113-2 are preferably flat strips, each having a series of holes or apertures for a column of display cells. The cathodes are parallel to each other and are oriented at an angle, preferably 90, to the scan anodes 21-25. Each crossing of them defines a scan cell. A cathode aperture is located at each crossing for priming an associated display cell 90. Each cathode 111-1, 113-2 lies along a column of cells, and each anodelies along a row of cells. Therefore, each column of cathode apertures is associated with a column of cells and each row of cathode apertures, defined by adjacent cathodes, lies along a row of cells. Each scan cell includes a portion of one of the scan control anodes 21-25, the associated portion ofa cathode 111-1, 113-2 above it, and the volume of gas between these electrode portions. The scanning cells are identified by the anode and cathode which cross them.
The system of the invention is especially suited for use with a display panel 10 of the type known as a SELF-SCAN panel and shown in FIGS. 2 and 3. This type of panel includes a bottom plate 20 of insulating material, such as glass or ceramic, having a plurality of parallel slots formed in the top surface thereof.
Electrodes 40, which are used as scanning anodes in one mode of operation of the panel, are seated in each of the slots 30, and electrodes 50, used as cathodes for scanning and display, are seated on or in the top surface of plate 20.'Each cathode electrode 50 crosses each anode electrode 40, and each crossing defines a scan cell 60. The cathodes include rows of tiny apertures '85, each of which is located at a scan cell. The scanning cells 60 are arrayed in rows and columns, and each cathode 50 is oriented along a vertical column of scanning cells in the panel as illustrated.
The panel 10 includes an insulating plate 95 disposed over the cathodes 50 and having apertures or display cells 90 arrayed in rows and columns, with each cell 90 being positioned over and in operative relation with a cathode aperture 85 and a scan cell 60. Display anode wires 100 are disposed on or in the top surface of the insulating plate 95, and each is aligned with a row of display cells 90. A glass cover plate 105 completes the panel. The panel is filled with a suitable ionizable gas such as neon, argon, xenon or the like, or mixtures of such gases and a vapor of mercury is usually included to minimize cathode sputtering.
The operation of a SELF-SCAN panel and the structural features thereof are described and claimed in copending application Ser. No. 850,984, filed Aug. 18, 1969. Briefly, the operation comprises applying operating potential to all of the scanning anodes 40 and applying operating potential sequentially and in turn to each of the scanning cathode electrodes 50, beginning, for example, at the left and proceeding to the right as seen in FIGS. 2 and 3. As each scanning cathode is energi'zed, the associated column of scanning cells 60 is fired, and the operation is carried out sequentially throughout the panel. Simultaneously with the energization of each cathode 50, information signals are applied to selected display anodes 100. The display cells 90, associated with the energized anodes and the energized scanning cells 60, are thus fired. The inforreset cathode 100, a keep-alive anode 18 and cathode 101, and a covering view plate of glass or the like as in FIGS. 4 and 5. In the completed panel 10, the plates and the various electrodes are hermetically sealed along their adjacent edges by a glass frit such as Pyroceram, or other suitable material. Reset cathode may have a separate group of gas cells associated with it, if desired. The gas used in panel 10 isintroduced in any suitable manner, for example, by means of a tubulation (not shown), secured to the bottom plate.
The cells usually are actuated beginning with the first column of scan cells and proceeding from column to column to the last column of cells in the device. A signal is generated to fire the cells associated with reset cathode 110 having terminal 102 to initiate the scanning cycle. The cathodes of the panel are connected in three groups, which may be described as phases, to terminals 111, 112 and 113, as shown in FIG. 4. The display cathode -111-1 associated with the first column of cells at the left-hand edge of the panel is designated a phase 1 cathode and every fourth cathode is connected in this group. The other cathodes are connected in the other groups as shown, including the last cathodes lll-n, 112-n and l13-n. A- matrix array of display cells 90 is illustrated, associated with the cathodes 111, 112, 113. Any number of cells may be included in the array, of course, including cells in association with reset cathode 102, if desired. The keep-alive anode 18 and the keep-alive cathode '101, if included, are usually energized independent of the other electrodes.
Referring now to FIG. Sin detail, a display system according to the invention includes a display panel 10 having a plurality of display cells 90.DispIay anodes 11-15 and scan anodes 21-25 in the panel are asso-- ciated with the corresponding rows of display cells and scan cells, respectively. Cathodes 111-1, 112-1 and 113-1 are associated with the first three display columns at one end of the panel. The panel also includes a reset cathode 110 and cathodes 111-2 Ill-n, 112-2 112-n, 113-2 113-n, coupled in groups with cathodes 111-1, 112-1 and 113-1, respectively. The cathodes of the panel are driven by cathode drivers 123 in successive order. Reset cathode 110 is driven by reset driver 120 through an RC energy storage network including capacitor 104 and resistors 106 and 108, as described in the Eisenberg, et a1 application, Ser. No. 21,756.'Phase 1 (01) cathodes 111-1,
111-2, etc. are driven by phase 1 driver transistor 121.
Likewise, phase 2 (02) cathodes 112-1, 112-2, etc. are driven by cathode driver 122 and phase 3 (03) cathodes 113-1, 113-2, etc. are driven by phase 3 cathode driver 123.
Reset driver 120 is controlled by a logic or timing gate through a RC coupling network including resistor 170 and capacitor 180. Likewise, cathode drivers 121-123 are controlled from logic gates 191-193 through RCcoupling networks including resistor 171 and capacitor 181, resistor 172 and capacitor 182, and resistor 173 and capacitor 183, respectively. Diodes 160-163 are connected across the base-emitter junctions of cathode drivers 120-123 to limit reverse biasingof them. Diodes 196-199 clamp the voltage on the outputs of logic gates 190-193 near ground in the negative direction.
The sequential driving of the cathodes are referenced to a clock signal applied to point A in the circuit as illustrated by waveform 210- in FIG. 6. Reset gate 190 is enabled concurrent with the first pulse of clock waveform 210 for turning on reset driver 120, as indicated by the reset drive waveform 220. The reset drive extends until the beginning of the next clock pulse as shown and discharges energy from capacitor 104 into the reset cathode. Logic gate 191 is enabled at the beginning of the second clock pulse for turning ON cathode driver 121, which is driven until the beginning of the third clock pulse as shown in waveform 230. Like wise, phase 2 cathode driver 122 and phase 3 cathode driver 123 are enabled by logic gates 192 and 193, respectively, concurrent with the leading edges of the third and fourth clock pulse signals as shown by drive waveforms 240 and 250 of FIG. 6.
In the operation of display panel 10, each of the scan cells at the junctions of the cathodes and of the scan supporting anodes 21-25 must be pre-biased at an OFF level. This is ordinarily accomplished by connecting the scan anodes 21-25 through-suitable resistors to one bias level and by coupling each of the cathodes of the panel through suitable resistor and diode networks to a pre-bias voltage level which will maintain them in the OFF state. The customary networks for applying voltage to the cathodes of these devices from a voltage reference device such as a Zener diode 135 have often wasted a considerable amount of current. As much as a half watt or more of power can be dissipated in such circuits.
According to one aspect of the present invention, the use of a. separate current-source network or circuit for Zener diode 135 is eliminated and sustaining current for it is provided through the resistors of the individual cathode pre-bias networks. The reset cathode 110 is pre-biased through resistors 106 and 108 connected between ground and Zener diode 135 in addition to storing energy in capacitor 104 preparatory to the driving of it. In this apparatus the phase lcathodes 111-1, 111-2, etc., are pre-biased through the series connection of resistor 131 and diode 141 also connected between ground and the Zener diode. This phase 1 prebias network is effectively in parallel to the pre-bias network of the reset cathode including resistors 106 and 108 and diode 140.
It is necessary to provide separate pre-biasing paths to the reset cathode and to one of the groups of display cathodes in order to maintain pre-bias on the unenergized cathodes while any one of them is activated. Par allel pre-biasing is provided for the reset cathode and the phase 1 cathodes in this system since the first phase 1 cathode 111-1 is capacitively coupled within the device itself to the reset cathode 110 to a significant degree. The phase 1 cathodes would be pulled negatively with the reset'cathode if they were not pre-biased independently by-a parallel bias network as in this apparatus.
The phase 2 cathodes 112-1, 112-2, etc. and the phase 3 cathodes 113-1, 1 13-2, etc. on the other hand, can be pre-biased through resistor 132 and diode 142 and resistor 133 and diode 143, respectively, directly to Zener diode 135, as shown. It has been found that sufficient sustaining current for the Zener diode is conducted either by phase 1 pre-bias resistor 131 or by pre-bias resistors 106 and 108 of the reset cathode circuit to adequately bias the remaining cathodes. Prebias for the remaining cathodes is. thus continuously available since the pre-bias circuits of either the reset circuit or of the phase 1 cathode circuit is operating at all times. The power loss in the pre-bias Zener diode 135 is, therefore, limited by the current conductedby these two cathode pre-bias resistor networks. The power wasted in cathode pre-biasing is thus considera-' bly less than that experienced when all the cathodes are pre-biased separately and when a separate currentbleeding resistor is provided for the pre-biasing Zener diode.
According to another feature of the invention, a pulse-operated current source is provided for the scan supporting anodes 21-25, rather than their being resistor-coupled directly toa fixed bias level. A control transistor 91 is coupled across a reverse-biased Zener diode 98 and in series with resistors 31-35 which are connected. at their other ends to the scan anodes. The clock signals applied to input A of inverter 88 appear inverter at circuit junction B as shown by waveforms 210 and 260 of FIG. 4. This inverted clock waveform is applied concurrently to control transistor for blanking display anode drivers 41-45 in each cycle,
and to control transistor 91 for scan anodes 21-25,.
through resistor 94. Control transistor 91 is normally held off by a positive voltage level from inverter 88 and is turned ON by base bias resistor 96 during each inverted clock signal. A diode 92 is provided to limit neg ative voltage excursions upon the output terminal of inverter 88. 4
The total bias voltage available across the selected scan cells of the device during'the clock pulses is, therefore, the difference in potential between an approximate ground potential at point D and the potential on Zener diode 135,-on the order of 170 volts, nominally. After a column of scan cellsin the device has been ionized, however, scan resistors 31-35 drop the initial voltage on the scan anodes to approximately -80 volts, as appears in waveform 290 of FIG. 4. At the end of each clock pulse signal, control transistor 91 turns OFF and the bias for scan anodes 21-25 is provided through Zener diode 98, a 50 volt unit in the preferred embodiment. The waveform at circuit junction D, therefore, varies between approximately ground and 50 volts as shown by waveform 280 in FIG. 4. The result is that the voltage waveform atpoint E on the scan anodes themselves varies between approximately 80 volts and volts, as shown by waveform 290.
The total voltage applied to the scan cells of the device after initial ionization may be less than the breakdown voltage, and of the order of approximately 80 volts, if desired. The pulsed current drive to the scan supporting anodes by control transistor 90, therefore, 1 reduces the current in the energized scan cells of the device after glow transfer between columns and glow priming of the display cells are completed. An initial high current level is' provided to a selected column or group of scan cells during each clock pulse through transistor 91. During the rest of the column ON time, the current to the energized scan cells is reduced to a lower level through Zener diode 98.
This reduces the power dissipation in the'device considerably since it has been found to be possible to reduce the scan current levels in the latter portion of each clock period by a factor of 2 or more. This reduces the amount of power necessary to drive the rear anodes of the display device or panel. Since the length of time at the high current level is independent of the column ON time, the amount of power reduction is greater for shorter panels (those having fewer columns),
The display anode drivers 41-45 are held off by control transistor 80 by negative voltage pulses at circuit junction C during the clock pulses, indicated by waveform 270 of FIG. 4. Control transistor 91 for the scan anodes, on the other hand, is turned on during each clock pulse. This results in the high current level in the scan anodes being maintained during each clock pulse signal, while the display anode drivers 4145 are blanked" or disabled.
The display anodes themselves are driven by current drivers 4l-45 under the control of transistor 80. The current level in the display anodes 11-15 and,'conscquently, the brightness of the display cells is controlled by different bias levels provided on the arm of potentiometer 86. The individual current levels for the display anodes is determined by current-limiting resistor 61-65, respectively, and the display drivers 41-45 are protected from destructive current levels resulting from possible arcing in the display device, by resistors 51-55, respectively. Display anode drivers 41-45 are normally held off by base resistors 71-75 and are delayed from turning on during each clock pulse by the controltransistor 80. The input signals for the data to be displayed are applied to the base electrodes of transistors 4l 45.
Although the preferred embodiments of the invention have been described in detail, it should be understood that the present disclosure has been made by way of example only. Many modifications and variations of the invention are possible in light of the above teachings. It is, therefore, to be understood that, within the scope of the appended claims, the invention may be practiced otherwise than as specifically disclosed.
What is claimed is:
1. A display system including a gas-filled display panel comprising an array of first scanning cells disposed in rows and columns, including a first column, a last column, and intermediate columns,
a scan anode electrode aligned with each row of scanning cells,
a scanning cathode electrode aligned with each column of scanning cells,
a column of reset cells disposed adjacent to and ahead .of said first column of scanning cells, and in operative relation with said scan anode electrodes,
a reset cathode electrode aligned with said column of reset cells,
an array of display cells disposed in rows and columns and each aligned with one of said scanning a source of information signals coupled to each of said display anodes and adapted to apply informa- -tion signals thereto,
said scanning cathode electrodes being connected in a plurality of groups so that there is a first group, a second group, and an nth group, the scanning cathodes being arrayed so that two adjacent cathodes of one group are separated by one cathode of each of the other groups, a cathode of said first group being positioned immediately adjacent to said reset cathode,
a separate cathode driver coupled to each of sai groups of cathode electrodes for applying operating potential to eachgroup of cathode electrodes separately,
drive means coupled to said cathode drivers and adapted to turn on each cathode driver separately and in turn whereby the cathode electrodes are energized separately-and in turn whereby each column of scanning cells is energized separately and in turn,
a reset cathode driver connected to said reset cathode electrode,
drive means coupled to said reset cathode driver for operating said reset cathode driver, and
a voltage pre-bias circuit coupled to all of said cathodes including circuit means for biasing said reset cathode at a first level, biasing said first scanning cathodes at a second level, and biasing all of the other scanning cathodes at a third level,
wherein said pre-bias circuit for said cathode electrodes and said reset cathode electrode includes a connection from a potential source through a Zener diode to a bus, said bus being connected through a diode, a parallel first resistor-capacitor combination, and a second resistor to ground, said parallel resistor-capacitor combination being connected to said reset cathode to provide pre-bias po- .tential thereto, a connection from said bus through a diode and a third resistor to ground, with a connection to said first group of cathodes from the junction point of said diode and said third resistor to provide pre-bias potential for said first group of cathodes, said third resistor being in parallel with said second resistor, and other connections from all of the other groups of cathodes through a parallel combination of resistor and diode to said bus to provide pre-bias potential therefor.
2. The system defined in claim 1 and including a source of voltage pulses coupled to all of said scan anode electrodes.
3. The system defined in claim 2 wherein said source of voltage pulses includes a source of generally rectangular clock pulses coupled through an inverter to a semiconductor switching device, the output of which is coupled to said scan anodes, the output of said semiconductor switching devices comprising voltage pulses corresponding in time to said clock pulses.
, 4. The system defined in claim 3 wherein said semiconductor switching device is a transistor having its collector-emitter circuit coupled across a reversebiased Zener diode, having its collector connected to said scan anodes, and having its base connected to said inverter.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
|US3891983 *||Jun 20, 1974||Jun 24, 1975||Burroughs Corp||Multi-position character display panel having display cathodes and auxiliary cathodes and circuits for operating the same|
|US3893101 *||Jun 20, 1974||Jul 1, 1975||Burroughs Corp||Display apparatus having segmented integral regulator|
|US3942071 *||Nov 1, 1974||Mar 2, 1976||Ferranti, Limited||Gas-discharge display device driving circuits|
|WO1982000066A1 *||Jun 11, 1981||Jan 7, 1982||Inc Lucitron||Flat panel display system|
|U.S. Classification||345/61, 348/E03.14|
|International Classification||H01J17/49, G09G3/29, H04N3/12|
|Cooperative Classification||G09G3/29, H04N3/125, H01J17/494|
|European Classification||H04N3/12G, G09G3/29, H01J17/49D2|
|Nov 22, 1988||AS||Assignment|
Owner name: UNISYS CORPORATION, PENNSYLVANIA
Free format text: MERGER;ASSIGNOR:BURROUGHS CORPORATION;REEL/FRAME:005012/0501
Effective date: 19880509
|Jul 13, 1984||AS||Assignment|
Owner name: BURROUGHS CORPORATION
Free format text: MERGER;ASSIGNORS:BURROUGHS CORPORATION A CORP OF MI (MERGED INTO);BURROUGHS DELAWARE INCORPORATEDA DE CORP. (CHANGED TO);REEL/FRAME:004312/0324
Effective date: 19840530