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Publication numberUS3812475 A
Publication typeGrant
Publication dateMay 21, 1974
Filing dateDec 26, 1957
Priority dateDec 26, 1957
Publication numberUS 3812475 A, US 3812475A, US-A-3812475, US3812475 A, US3812475A
InventorsC Christiansen, L Kanter, G Monroe
Original AssigneeIbm
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Data synchronizer
US 3812475 A
Abstract  available in
Images(409)
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Claims  available in
Description  (OCR text may contain errors)

United States Patent Christiansen et a1.

1 May 21, 1974 1 1 DATA SYNCHRONIZER [75] Inventors: Carl L. Christiansen; Lawrence E.

Kanter, both of Poughkeepsie; George R. Monroe, Wappingers Falls. all of NY.

[73] Assignee: International Business Machines Corporation, New York. NY.

[22] Filed: Dec. 26. 1957 [21] Appl. No: 705.447

[52] 0.8. CI. 340/1725 [51] Int. Cl. 60619/18 [58] Field of Search 235/61 PB. 61 MS, 157. 235/165, 166. 167

[56] References Cited UNITED STATES PATENTS 3.029.414 4/1962 Schrimpl 340/1725 3.142.043 7/1964 Schrimpf 340/1725 3.231.865 1/1966 Wilenitz 340/1725 3.234.517 2/1966 Herold et a1 340/1725 3.283.308 11/1966 Klein et a1. 340/1725 3.334.333 8/1967 Gunderson et a1. 2.604.262 7/1952 Phelps et all. 2.636.672 4/1953 Hamilton et a1. 340/1725 X 2.679.638 5/1954 Bensky et a1. 340/1725 2.767.908 10/1956 Thomas 340/1725 2.796.218 6/1957 Toolill et a1. 340/1725 2.805.283 9/1957 Stiles 178/2 2.960.683 11/1960 Gregory et a1 340/1725 FOREIGN PATENTS 0R APPLICATIONS 1.099.467 3/1955 France 340/1725 749.836 6/1956 Great Britain 340/1725 OTHER PU BLlCATlONS E.R.A. 24-Digit Parallel Computer with Magnetic Drum Memory (PX29136)." Eng. Research Assoc.

Inc. St. Paul. Minn.. 1949. pp. 4. 5. 7-22. 27-36.

Primary liraminerRaulfe B. Zache Attorney. Agent. or Firm-Hanifin & Jancin ABSTRACT A data processing system in which a plurality of data channels control the simultaneous exchange of data between many input/output devices. and a common shared storage. The channels automatically extract control instructions from storage and interpret them to independently carry out data transfers.

Each data channel is initialized by the central processing unit (CPU) which causes a control word to be transferred from storage to the data channel where it is stored. The data channel utilizes the control word to start an input/output operation. The input/output operation is continued automatically by the channel which has means for retrieving subsequent control words from storage independent of the CPU. Data transfers between a data channel and the storage over a common storage bus are performed by a cycle stealing" capability wherein execution of the CPU program may be delayed for one storage cycle. which cycle is utilized by the channel to store a word of data in the storage. Competing requests among data channels and the CPU are resolved by a priority circuit which grants storage access to the highest priority channel demanding access. The CPU is given the lowest priority.

Since the channels direct the flow of information between [/0 devices and main storage, they relieve the CPU of the task of communicating directly with the devices and permit data processing to proceed concurrently with 1/0 operations.

91 Claims. 506 Drawing Figures 10 1C is tat it time PATENTEBIAX 21 mm 38 121475 sum 01 or 409 FPUNCHED CARD CARD PRINTER READER PUNCH TAPE CHANNEL CONTROL A 4.20-1

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SYNCHRONIZER a ATTORNEY PAIENTEDRAYZWM 3,812,475

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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4571674 *Sep 27, 1982Feb 18, 1986International Business Machines CorporationPeripheral storage system having multiple data transfer rates
US4771378 *Jun 19, 1984Sep 13, 1988Cray Research, Inc.Electrical interface system
US4807121 *Jun 10, 1988Feb 21, 1989Cray Research, Inc.Peripheral interface system
US4817037 *Feb 13, 1987Mar 28, 1989International Business Machines CorporationData processing system with overlap bus cycle operations
US5448699 *Aug 16, 1993Sep 5, 1995Compaq Computer Corp.Apparatus with leading edge delay circuit for selectively sending a delayed substitute version of a signal transmitted between an expansion card and a system bus
US5796979 *Oct 16, 1996Aug 18, 1998International Business Machines CorporationData processing system having demand based write through cache with enforced ordering
US7076578Dec 22, 2003Jul 11, 2006Intel CorporationRace free data transfer algorithm using hardware based polling
US7412608 *Nov 22, 2002Aug 12, 2008Infineon Technologies AgSecure data processing unit, and an associated method
US7710681 *Jun 6, 2007May 4, 2010International Business Machines CorporationOptimizing tape speed for a sync operation
US7808905 *Sep 25, 2002Oct 5, 2010Panasonic CorporationTransmission method, sending device and receiving device
US8706262 *Feb 17, 2012Apr 22, 2014Omron CorporationCPU unit of PLC, system program for PLC, and recording medium storing system program for PLC
US8745346 *Mar 18, 2008Jun 3, 2014Microsoft CorporationTime managed read and write access to a data storage device
US20120239172 *Feb 17, 2012Sep 20, 2012Omron CorporationCpu unit of plc, system program for plc, and recording medium storing system program for plc
EP0706134A2Sep 22, 1995Apr 10, 1996International Business Machines CorporationData processing system having demand based write through cache with enforced ordering
Classifications
U.S. Classification710/7, 710/20
International ClassificationG06F15/78
Cooperative ClassificationG06F15/78
European ClassificationG06F15/78