|Publication number||US3815354 A|
|Publication date||Jun 11, 1974|
|Filing date||Jan 2, 1973|
|Priority date||Jan 2, 1973|
|Also published as||CA995470A, CA995470A1, CA1001712A, CA1001712A1, DE2365143A1, DE2365143B2, DE2365143C3|
|Publication number||US 3815354 A, US 3815354A, US-A-3815354, US3815354 A, US3815354A|
|Inventors||R Strocka, D Broxterman|
|Original Assignee||Cal Tex Semiconductor|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (2), Referenced by (11), Classifications (18)|
|External Links: USPTO, USPTO Assignment, Espacenet|
United States Patent 1191 Strocka et al.
[ ELECTRONIC WATCH 75 Inventors: Richard L. Strocka; David F.
Broxterman, both of Sunnyvale,
 Assignee: Cal-Tex Semiconductor, Santa Clara, Calif.
 Filed: 2, 1973 21 Appl. No.: 320,223
 US. Cl 58/50 R, 307/38, 340/336 [5 1] Int. Cl. G04b 3/12, G04c 3/00  Field of Search... 58/23 R, 23 A, 23 BA, 85.5;
Primary Examiner--Edith Simmons .lackmon Attorney, Agent, or Firm-Townsend and Townsend;
Warren P. Kujawa RESET 1111 3,815,354 1 June 11, 1974  ABSTRACT A low cost electronic time keeping and display system comprising a regulated voltage converter for converting a low voltage from a source to a relatively high voltage, an electronic time keeping system powered by the low voltage source for providing low voltage time signals, and a plurality of level converters powered by the high voltage for converting each of the low voltage time signals to a relatively high voltage of sufficient magnitude to operate an associated relatively high voltage display. The regulated voltage converter periodically samples the relatively high voltage with a short duty cycle to minimize current consumption. Each level converter has a complementary configuration which consumes current only during an extremely short switching cycle. A single chip CMOS design, low voltage and current requirements and compatibility with liquid crystal display make the invention ideal for use in a watch environment.
19 Claims, 8 Drawing Figures RIQULATED VOLTAGE PATENTEDJUH H @1 3815354 SHEET '4 BF 4 ELECTRONIC WATCH BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to electronic time keeping devices for providing a correct indication of time. More particularly, this invention relates to systems employing electronic circuitry for generating correct time signals which can be fabricated in a single integrated circuit source .must of necessity have a correspondingly small dimensions. In addition, such a source must be economical to replace. Although energy sources which I meet the required constraints on physical dimensions chip and housed in a typical watch case. In a further aspect, this invention relates to circuitry for providing a regulated high level supply voltage from a relatively low voltage source for supplying power to electronic time display circuitry. In a still further aspect, this invention relates to level converter circuitry for converting'time indicating signals from a relatively low voltage to a relatively high voltage for driving a time indicator display. v
2. Description of the Prior Art Time keeping devices are known which employ electronic circuitry for providing electrical signals serving to indicate the correct time. In a typical device, an extremely stable high frequency oscillator supplies high frequency time base signals. These signals are divided down by known circuitry which supplies a signal train .of pulses having a frequencyof 1 Hz. This signal train is coupled to a time keeping unit-comprising a number of counters which are incremented by the 1 Hz pulses. A scale of 60 counter provides a count representative of the correct second of the minute. Another scale of 60 counter provides a count representative of the cor rect minute of the hour. A scale of 12 counter provides a count representative of the correct hour of the day. In some devices, the hours counter is a scale of 24 counter.
The outputs of the time keeping unit counters are decoded and typically coupled to a multi-digit seven segment or dot matrix display. As the counters are clocked to different states by the 1 Hz clock pulses, various ones of the segments or dots are energized by the. decoded-counter outputs, thereby providing a visual output indicatingthe time.
Time keeping systems of the above type provide a degree of accuracy which surpasses conventional mechanical movements, primarily due to the high frequency time base employed and the excellent frequency stability of electronic digital circuitry. Also, fully electronic systems are less expensive to manufacture than mechanical systems, and exhibit a much longer lifetime since there are no moving mechanical parts.
With the advent of large scale integrated circuits, attempts have been made to produce electronic time keeping systems for packaging in wrist, pocket, pendant and ring watch cases. Efforts at successful development of electronic watches have been impeded, however, by the problem of power consumption. Since all known electronic time keeping systems and display devices consume electrical energy, an electronic watch must be provided with a suitable portable energy source which is capable of supplying electrical energy at the requisite voltage and current level for a reasonably long period of time before replacement is required, the minimum desirable period being approximately 1 year. Because of the relatively small amount of volume available in a typical watch case, such a and cost are currently available, their voltage, current and power ratings are extremely low.
' Given the desirability of using such available sources, however, recent developmental effortsin the field of electronic watches have focused on designing electronic time keeping systems and associated displays which consume a minimal amount of current at the minimum voltage required for error free operation of the device. Some efforts have concentrated on combining an electronic time keeping system with a standard mechanical watch display utilizing motor driven sweep type hour, minute and second hands. Other efforts have been directed to a fully electronic system using an electronic time keeping system in' combination with an electrically actuated digital display utilizing light emitting diodes. While the electronic time keeping portion of such electronic watches has been found to consume modest amounts of electrical'ene rgy, the power requirements of the display portion of both types have been found to be less than satisfactory for the abovenoted available energy sources.
Still other efi'orts to produce an electronic watch compatible with available low power, minimal size energy sources have been directedto utilizing a liquid crystal display with an electronic time keeping system. While liquid crystal displays are available which meet the minimal size requirements for packaging purposes and which require only modest amounts of energy for proper operation, such displays require a relatively high voltage for proper actuation. Thus, known electronic watches using a liquid crystal display have employed an electronic time keeping system having two portions: one operated at a relatively low voltage, eg. 3 volts DC, for generating the 1 Hz reference pulses; the other operated at a relatively high voltage, eg. 15 volts DC, for providing time indicating signals having a sufficiently great magnitude for controlling the actuation of the liquid crystal display characters. This latter portion has heretofore employed a single discreet level SUMMARY OF THE INVENTION The invention disclosed herein comprises a low cost electronic time keeping and display system which operates from a low voltage energy source and consumes energy at a greatly decreased rate than that of known systems. Because of the low operating voltage and low current consumption characteristics, systems constructed according to the-invention can be powered by commercially available, low cost energy sources for prolonged periods in excess of one year without deterioration of the time keeping accuracy thereof. In addition, since virtually all of the electrical components are housed in a single integrated circuit chip, the fabrication and assembly costs are extremely low.
as a liquid crystal display. The time keeping system includes a crystal-controlled high frequency oscillator, a divider circuit, a time keeping unit, and a decoder section. The regulated voltage converter comprises a constant current source, a voltage threshold detector, a sense and enable circuit, and a sample circuit voltage converter including a ringing circuit. To minimize power consumption, the regulated voltage converter is arranged to periodically sample the relatively high voltage output, with each sample period having an extremely short duty cycle. Each level converter is arranged to draw current only during an extremely short switching period. The preferred embodiment of theinvention is implemented with CMOS circuitry arranged for minimal power consumption.
For further understanding of the nature and advantages of the invention,-reference should be had to the following description taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a system diagram of the preferred embodiment of the invention;'
FIG. 2 illustrates a seven segment display character;
FIG. 3 is a block diagram of the time keeping unit of the preferred embodiment;
FIG. 4 is a diagram of a portion of the time keeping unit of FIG. 3;-
FIG. 5 is a block diagram of the regulated voltage converter of the preferred embodiment;
FIG. 6 is a circuit diagram of the regulated voltage converter of FIG. 5;
FIG. 7 is a circuit diagram of a pair of level converters, a transfer gate and the shaper of the preferred embodiment; and FIG. 8 is a wave form diagram illustrating the operation of the preferred embodiment.
. DESCRIPTION OF THE PREFERRED EMBODIMENT Turning now to the drawings, FIG. 1 illustrates the preferred embodiment of the invention suitable for use as an electronic watch. An oscillator 10 having a control crystal 12 provides a train of high frequency reference'pulses preferably at a frequency of 32,768 Hz to the input of a frequency divider circuit 14. Frequency divider circuit 14 divides the high frequency reference signal down to 64 Hz, 32 Hz and 1 Hz reference signals. The 64 Hz and 1 Hz reference signals are coupled to the input of a time keeping unit 16, shown in detail in FIGS. 3 and 4, which provides output signals representative of minutes and hours to a decoder unit 18.
Decoder unit 18 is provided with a plurality of output leads 19 -19,- each coupled to a low voltage control input terminal of a different level converter 20 -20,. It is noted that the 1 Hz output signal from divider 14 is also coupled directly to a level converter 20,.
The output of each level converter 20 -20,- is coupled to the control input of a different transfer gate 20 -20,. The output of each transfer gate 22 -22,- is a high level signal for enabling a different one of a plurality of display segment control electrodes 24 -24,- of a liquid crystal display 25.
In the preferred embodiment, liquidcrystal display 25 is arranged as a plurality of -7 segment digital display characters, each similar to the seven segment character illustrated in FIG. 2. Each character comprises seven individual segments a-g, each of which is actuatable in response to the application thereto of an enabling or striking potential. By selectively actuating different combinations of the individual segments a-g, the decimal digits 09 may be displayed. In the preferred embodiment two such characters are used for indicating minutes and two characters for indicating hours. A special segment 24 is pulsed at a I second rate by the I Hz signal on lead 19 to provide a visual indication to the wearer that the electronic watch is functioning properly. The structure and operation of liquid crystal displays are well known and further structural details of display 25 are accordingly omitted to avoid prolixity. Such displays are characterized by relatively low current consumption compared to light emitting diode displays or other known types of displays suitable for use as time indicators. However, for proper operation a liquid crystal display requires the application of a relatively high enabling potential between a given segment 24 and the common electrode 30. Moreover, this relatively high enabling potential is preferably applied in an A.C. mode as described below in order to prolong the life of the display.
As will be apparent, the number of level converters 20 40,, transfer gates 22 -22, and display segment control electrodes 24 -24,- is determined by the number of desired reference characters and the number of segments per characterrTo avoid needless repetition, the majority of such elements have been indicated in the FIG. 1 diagram by broken lines.
A low voltage source 26 providing a source voltage V of approximately 1.5 volts DC in the preferred embodiment is coupled to the supply voltage input of oscillator l0, divider unit 14, time keeping unit 16 and decoder. unit 18. Low voltage source 26 is also coupled to a regulated voltage converter 27 which converts the relatively low voltage from source 26 to a relatively high voltage of the order of approximately 15 volts DC in the preferred embodiment. The output from regulated voltage converter 27 is coupled to the supply voltage input of level converters 20 -20,, a level converter 20, and a shaper 29. The high leveloutput of the shaper 29 is coupled to the transfer inputs of transfer gates 22 -22, and to common electrode 30 of liquid crystal display 25.
As will now be apparent, oscillator 10, divider 14, time keeping unit 16 and decoder 18 are all powered by the relatively low voltage V from source 26. Since these units are all well known to those skilled in the art their details have been omitted to avoid prolixity. These units are preferably implemented by CMOS circuitry. As will be evident to those skilled in the art, cirsuch circuits require extremely small amounts of current for proper operation. In addition, such circuits can readily be designed to function properly from 'extremely low supply voltage. Thus, low voltage source 26 may comprise any one of a number of commercially available 1.5 volt DC batteries.
In operation, the train of high frequency reference pulses from oscillator) is divided down by divider 14 to the 64 Hz, 32 Hz and 1 Hz time reference signals. The 1 Hz reference signals are applied to timekeeping unit 16 which provides a minutes and hours count in response thereto. The minutes and hours signals from time keeping unit 16 are decoded by decoder unit 18 into low level signals on leads 19 -19 for specifying the individual segments 24,-24, of liquid crystal display which are to be actuated in order to provide a visual time indication. The low level 1 Hz reference signals on lead 19 are also utilized to specify the actuation of seconds segment 24 of liquid crystal display 25.
' Level converters 20 -20,- and 20,-, transfer gates 22 -22,- and shaper 29 are all operated at a relatively high potential V provided by regulated voltage converter 27. Level converters 20 40, convert the low level control signals at their respective inputs 119 -49,- to high level control signals for operating transfer gates 22 -22,-. Level converter 20,- converts the low level 32 Hz control signal present on input lead 19,-to high level 32 Hz signals. These high level signals from level converter 20,- are shaped by shaper 29 to provide high level 32 Hz segment actuation signals with sharply defined leading and trailing edges. The segment actuation signals are'coupled through transfer gates 22 -22, to segments 24 -24, and directly to common electrode of liquid crystal display 25. As more fully described below in connection with FIGS. 7 and 8, transfer gates 22 22, control the phase of the segment actuation signals coupled therethrough with reference to the phase of the segment actuation signal coupled directly to common electrode 30. When the segment actuation signals on a given segment 24,- and common electrode 30 are in phase, that segment is not displayed; when segment actuation signals are out of phase that segment is actuated. Thus, various segments of the minutes and hours digit characters are displayed or not depending on the low level output signals on leads 19 -19. from decoderunit 18. In this manner, the various digits indicating minutes and hours are displayed.
An important feature of the invention shown in FIG. 1 resides in the operation of the time keeping system comprising oscillator 10, divider unit 14, time keeping unit 16 and decoder unit 18 at the low voltage level V provided by source 26 and the operation of the level converters 20 -20,, 20 transfer gates 22 -22, and shaper 29 at the high voltage levelV provided by regulatedvoltage converter 27. Because of the low voltage operation of the time keeping system and the use of complementary semiconductor circuitry, the power consumption of the continuously operating time keeping system is held to a minimum. Because of the complementary semiconductor circuit configuration of the high level operated level converters 20 -20,, 20;, gates 22 -22,- and shaper 29, power consumption of this relatively high voltage portion of the preferred embodiment is also held to a minimum.
Time keeping unit l6, as shown in FIG. 3 comprises a divide-byunit 31, a minutes counter 32, an hours counter 33 and a time adjust unit 34. The divide-by-6O unit 31 produces an output pulse at 60 second intervals from the 1 Hz input signal. Each output pulse from unit 3]. increments minutes counter 32 which may comprise a scale of 60 counter or a scale of 10 counter followed by a scale of 6 counter. The last stage of minutes counter 32 produces an output pulse at 1 hour intervals. Each such output pulse increments hours counter 33, which may comprise a scale of 12 counter or a scale of 24 counter, the latter being utilized when a 24 hour time system is desired. Such counters are well known in the art and accordingly are not described in detail.
Time adjust unit 34 is arranged to gate 64 Hz signals to divide-by-60 unit 31 along with a DISABLE signal for preventing the 1 Hz input signal from operating unit 31, and 1 Hz signals to minutes counter 32 or hours counter 33, all in response to'time adjust signals from an operator control device. The operator control device comprises any operator adjustable device for providing minute and hour advance signals. One such arrangement comprises a pair of switches: one signifying minutes adjust; the other hours adjust; each operable by a different button protruding from the watch case. Other equivalent arrangements will occur to those skilled in the art. The 64 Hz input to divide-by-60 unit 31 clocks this unit to a predetermined initial state whenever minutes counter 32 is being adjusted. Once unit 31 reaches this initial state, application of the 64 'Hz signal to unit 31 is terminated. Thereafter, the DIS- MINUTES ADJUST signal inverted by an Inverter 38 disables an AND gate 39 from transmitting 1 Hz pulses to OR gate 37. When the last stage of divide-by60 unit 31 is set, a reset signal is applied to the reset input of flip-flop 35. When flip-flop 35 resets, AND gate 36 is disabled. AND gate 39 continues disabled until the MINUTES ADJUST signal is removed.
The minutes time adjust is effected by applying 1 Hz pulses to minutes counter 32 until the proper count has been attained. During this time the minutes section of liquid crystal display 25 provides a visual indication of the setting in minutes counter 32. The hours adjust is accomplished in a similar manner.
The various stages of minutes counter 32 and hours counter 33 are coupled to decoder unit 18. Decoder unit 18 comprises known logic circuitry for decoding various counter settings into control signals for specifying the proper character segments for actuation in accordance with the counter settings to form the corre sponding digit characters. Since circuitry for performing this function is well known to those skilled in the art, further details thereof have been omitted to avoid prolixity.
An important feature of the invention comprises the regulated voltage converter 27 shown in block diagram form in FIG. 5. A constant current source 41 supplies a small constant current to a voltage dropping resistor 42. In the preferred embodiment the approximate value of this current is l microamp. The opposite end of resistor 42 is coupled to the relatively high voltage output V of a voltage converter 44. Since the current through resistor 42 is substantially constant, the voltage drop thereacross is also constant. ThuS, any variation in the magnitude of V results in a linear variation of the voltage V, at junction 45, Le. V,V =K a constant. The voltage V, at junction 45 is sensed by a threshold detector 46 which provides an output signal whenever the magnitude of voltage V, falls below a first predetermined value, indicating that the magnitude of voltage V,, has fallen below a second predetermined value linearly related to the first predetermined value by the constant K. A sense and enable circuit 47 enables voltage converter 44 whenever the output of threshold detector 46 indicates that the magnitude of voltage V has fallen below the predetermined value. When enabled, voltage converter 44 converts the relatively low voltage V from low voltage source 26 to a relatively high voltage V A samplecircuit 48 controls constant current source 41, threshold detector 46 and sense and enable circuit 47 to provide periodic, interrupted operation of these elements. In the preferred embodiment, a sampling rate of 4 Hz is employed, the actual sample period being I millisecond. Other sampling rates and periods may be employed as desired. As noted above, in the preferred embodiment the relative magnitudes of V and V,, are approximately 1.5 volts DC and 15 volts DC respectively.
4 Voltage converter 44 also converts relatively low voltage V to' a biasing voltage V having a magnitude of approximately 1.5 volts DC below the magnitude of V,,'. In the preferred embodiment bias voltage V is derived from voltage V,, and thus is not separately sampled and replenished. If desired, however, separate sensing and replenishing circuitry may be employed for voltage V As discussed more fully below, voltage V provides a bias voltage for the operation of level coni verters 20 -20,, 20,.
' the elements comprising the various blocks shown in FIG. are enclosed in broken rectangles bearing the same reference numeral.
Voltage converter 44 may be considered as comprising a first portion depicted at the right of the Fig. for generating voltage V,,' and a second portion depicted at the. left of the Fig. for generating voltage V The first portion comprises a pair of complementary MOS transistors 50, 51 connected in a push-pull buffer configuration for providing a high driving current to a discreet transistor 52. Transistor 52 together with an inductance 53, a rectifying diode 54 and a capacitor 55 comprise a voltage ringing circuit for converting the relatively low'voltage V at terminal 56 to a relatively high voltage V,, at terminal 57. Transistor 50 is normally biased on and transistor 51 is normally biased off by the quiescent low level input signal to their commonly connected gates. A ground potential is thus applied through transistor 50 to the base of discreet transistor 52, maintaining this element non-conductive. When the level of the signal coupled to the gates of transistors 50,51 changes, the states of these two elements reverse. Thus, relatively low potential V from terminal 56 is applied through transistor 51 to the base of the remaining data input of discreet transistor 52 turning this element on, thereby permitting current to flow through inductor 53. When the level of the gate input signal to transistors 50, 51 reverts to the quiescent level, these elements again reverse states. turning off discreet transistor 52. The change of current through inductor 53 causes the development of a high voltage thereacross, which is rectified by diode 54 and stored by capacitor 55. After several initial cycles, the voltage at terminal 57 builds up to the desired magnitude V,,. In this manner, this first portion of voltage converter 44 converts the relatively low supply voltage V,, from low ,voltage source 26 to the relatively high voltage-V present on terminal 5.7.
The second portion of voltage converter 44 comprises a p-type MOS transistor 60 which is permanently biased on by voltage V,,'to supply current to a pair of N-type MOS transistors 61,62 configured as shown. The source terminal of lower transistor 62 is coupled to voltage V,,'. Transistors 61,62 provide a constant voltage drop to voltage V to establish bias voltage at terminal 63.
Constant current source 41 includes an N-type MOS transistor 65 and a pair of P-type MOS transistors 66,67 configured as shown as the mirror image of transistors 60,61, 62 to provide a constant voltage to the gate of a P-type MOS transistor 68. Transistor 68 provides a constant current to a first terminal of resistor 42 whenever a first P-type MOS switching transistor 70 is turned on in the manner described below. As noted above, the opposite terminal'of resistor 42 is coupled to voltage V Sense and Enable circuit 47 includes a pair of P-type MOS transistors 72,72 which are permanently biased on by voltage V applied to their respective gates whenever a second P-type MOS switching transistor 71 is switched on in the manner described below. Transistor 72 serves as a load for a P-type MOS transistor connected as a source follower, while transistor 73 serves as a load for an N-type MOS sensing transistor 76. Transistor 75 provides a voltage drop to voltage V, at junction 45 so that the voltage variations on the gate of sensing transistor 76 fall within an operative range. In addition, the voltage drop provided by source follower transistor 75 ensures that the voltage on junction 45 remains within a range that maintains the operation of transistor 68 in the constant current mode. So long as the magnitude of voltage V is not below the predetermined threshold value, sensing transistor 76 is biased off by the voltage present at the gate thereof. However, when the magnitude'of voltage V drops below this threshold value, sensing transistor 76 is biased on and the normally high signal at the output thereof drops to a low level.
The output from sensing transistor 76 is coupled directly to a first data input of a flip-flop 77 and through an inverter 78 to the remaining data input thereof. The
clock input signal to flip-flop 77 is a train of 4 Hz pulses each approximately 1 millisecond in duration obtained from sample circuit 48, described more fully below. Flip-flop 77 provides a control input signal to an inverting OR gate 80 which provides enabling control signals to the first portion of voltage converter 44.
The other input to inverting OR gate 80 is obtained from the output of an inverting AND gate 82. The inputs to inverting AND gate 82 are a 256 Hz and a 32K l-Iz pulse train, obtained from appropriate stages of divider circuit 14 of FIG. 1, and the O output of a flipflop 83, which is a J-K flip-flop in the preferred embodiment. The 256 Hz pulse train is applied directly to a first data input of flip-flop 83 and through an inverter 84 to thereof. As will be apparent to those skilled in the art, inverter 84, flipflop 83 and inverting AND gate 82 comprise a leading edge detector which develops negative-going pulse signals of approximately 15 microseconds duration each at a rate of 256 Hz from the 256 Hz and the 32K [-12 pulse trains. Thus, when flip-flop 77 is in the reset state, inverting OR gate 80 transmits these pulse signals to the commonly-connected gates of transistors 50,51 of voltage converter 44. Conversely, when flip-flop 77 is set, inverting OR gate 80 blocks the transmission of these pulse signals to voltage converter 44.
Sample circuit 48 comprises a sample pulse generator, an inverter 86 and the aforementioned first and second switching transistors 70,71. The sample pulse generator comprises a flip-flop 87, which is a .l-K flipflop in the preferred embodiment, an inverter 88 and an inverting OR gate 89. A 4 Hz pulse train is coupled directly to a first data input of flip-flop 87 and through inverter 88 to the remaining data input of flip-flop 87.
A 1,024 Hz pulse train is applied to the clock input of flipflop 87. Both pulse trains are obtained from appropriate stages of divider circuit 14 of FIG. 1. The Q output of flip-flop 87 is coupled to the input of inverting OR gate 89 along with the inverted 4 Hz pulse train. As will be apparent to those skilled in the art, inverter 88, flip-flop 87 and inverting OR gate 89 comprise a leading edge detector which develops positive-going pulse signals of approximately 1 millisecond duration each at a rate of 4 Hz from the 4 Hz and 1,024 Hz pulse trains. As noted above, these'pulse signals are applied directly to the clock input of flip-flop 77. Thus, the input to flipflop 77 is sampled 4 times per second. These pulse signals are also inverted by inverter 86 and applied to the gates of switching transistors 70,71. Since switching transistors 70,71 enable constant current source 41 and threshold detector 46, respectively, these circuits are each enabled concurrently for l millisecond at the rate of 4 times per second in synchronism with the sampling of flip-flop 77.
In operation, when power from voltage source 26 of FIG. 1 is first applied to the various V terminals of regulated voltage converter 27, the voltage at terminal 57 lies below the predetermined threshold value. Sensing transistor 76 is biased on and flip-flop 77 is reset by the first clock pulse, thereby enabling inverting OR gate is set by the succeeding clock pulse, blocking inverting OR gate 80. Thereafter, inverting OR gate 80 remains blocked until the magnitude of voltage V drops below the predetermined threshold value, causing sensing transistor 76 to be biased on, which in turn enables flip- 10 flop 77 to be reset by a succeeding clock pulse. During this operation, the magnitude of the voltage V,, at terminal 63 follows the variations in the magnitude of the voltage on terminal 57.
As will now be apparent to those skilled in the art, regulated voltage converter 27 provides an extremely well regulated high voltage V and a related bias voltage V required for the operation of level converters 20 -20,, 20, and liquid crystal display 25. The intermittant operation of constant current source 41 and threshold detector 46, the small duty cycle provided by sample circuit 48 and the complementary transistor drive configuration of voltage converter 44 all serve to reduce the power consumption of regulated voltage converter 27 well below that required for prior art voltage converter circuits providing conversion of a relatively low voltage to a relatively high voltage. The power consumption of regulatedvoltage converter 27 is further reduced by the use of CMOS circuitry for implementing flip-flops 77,83 and 87, and the use of MOS devices for the elements as shown and for the inverters and gates symbolically illustrated.
FIG. 7 illustrates the actual circuitry employed in the preferred embodiment for implementing level converter 20,, shaper 29 and level converter 20,- and transfer gate 22}, the latter circuitry being typical of level converters 20 40,- and transfer gates 22 -22,. In this Fig. the elements comprising the various blocks shown in FIG. 1 are enclosed inbroken rectangles bearing the same reference numeral.
Level converter 20,- includes a first and second pair of P-type MOS transistors 100, 101 and 102, 103, respectively, each pair being connected source-to-source and drain-to-drain as shown. The commonly-connected sources of each pair are coupled to ground potential. The gate of each inner transistor of each pair is coupled to the common drain terminal of the other pair. The
gate inputs to outertransistors 100,103 are the 32 Hz reference signals on lead 19, from'divider 14 of FIG. 1 and the output of an inverter 105, respectively. The common drain terminal of each pair is coupled to the drain terminal of a different N-type MOS transistor 106,107 respectively. The gate of each transistor 106,107 is coupled to the gate of the associated inner transistor 101,102 respectively. A constant current source comprising an N-type MOS transistor 108 having relatively high voltage V coupled to the source terminal thereof and biasing voltage V coupled to the gate thereof in order to permanently bias transistor 108 on is provided in the left main branch of level converter 20 An identically configured constant current source comprising N-type MOS transistor 109 is provided in the right branch of level converter 20;.
In operation, with enabling voltages V and V applied to transistors 108,109 and the low level input signal on terminal 19, at the true level, transistor .100 is biased off. The inverted input signal from inverter 105 is false and transistor 103 is thus biased on. U; is thus at ground potential and biases transistor 101 off and transistor 106 on. Since transistor 106 is biased on by Q, and transistor 108 is biased on by voltage V,,, O,
on and transistor 107 off.
When the low level input signal on terminal 19, transitions false, transistor 100 is biased on and transistor 103 is biased off. Since transistor 100 is now on, the voltage at Q, rises to ground potential, turning transistor 102 off and transistor 107 on. As transistor 102 is biased off, the voltage at Q, falls to V,,', biasing transistor 101 on and transistor 106 off. The circuit remains latched in this state until the inputv signal on lead 19,- transitions true. I
When the low level input signal on lead 19," transitions true, transistor 100 is biased off and transis tor 103 is biased on. As transistor 103 is biased on, the voltage at Q,- rises to ground potential, biasing transistor101 off and transistor 106 on. As transistor 106 is biased on, the voltage at Q, falls to V biasing transistor 102 on and transistor 107 off. The circuit remains latched in this state until the input signal on lead 19, again transitions false. Further operation of level converter 20, proceeds as already described.
As will now be apparent, level converter 20, provides a pair of oppositely phased output signals on terminals Q,, O, which range in magnitude between a negative voltage V having a relatively high magnitude and ground potential in response to an input signal on lead 19 ,which ranges in magnitude between a negative voltage V having a rlatively low magnitude and ground potential. As noted above, in the preferred embodiment the range on the magnitude of the input signal is approximately l.5 volts DC while the range on the magnitude of the output signal is approximately O-l5.0 volts DC. Thus, level converter 20 as well as level converters 20,20,-, permit the low voltage portion of the electronic time keeping system to control the relativelyhigh voltage display. It is important to note that level converter 20, draws current only during the extremely short transitional periods when the circuit is being switched between opposite latched states, due to the complementary configuration of the circuit. Thus, the current consumption of level converter 20, is extremely small and discontinuous, being of the order of 1 micro- The ogtput signals from level converter 20, on leads Q, and Q, are coupled to the control gate of complementary MOS transistors 110, 111, 112, 113, respecis coupled directly to common electrode of liquid crystal display 25. The output signals on Q and 629 ased on and the signal on Q29 is transmitted to'display seg n ient 24,-. Conversely, whenever the output signal on Q, is high and the output signal of Q, is low, tra nsistors 122 and 123 are biased on and the signal of 0 is transmitted to display segment 24,.
Level converter 20, is substantially identical in configuration to above-described level converter 20,. The input signal to level converter 20,, however, is a relatively low frequency time control signal from decoder unit 18, it being remembered that the control signals change at the maximum rate of l per minute for segments representing the 'units minutes'characters and the minimum rate of l per 12 hours for segments representing the tens hours character. Due to the relatively low frequency of the control signals applied to-level converter 20,-, it is not necessary to shape the output signals from this element present on terminals Q5, Q1.
The output signals from level converter 20, control the phase of the commutated square wave signal applied to display segment 24, relative to the phase of the commutated square wave signal applied to common are coupled to transmission gates 22 -22,, only one of I which is shown in FIG. 7.
Transmission gate 22,- comprises two pair of parallel connected CMOS transistors 120, 121 and 122, 123 respectively. The gates of CMQS transistors 121,122 are commonly connected to theQi Output terminal of level converter 20,. Similarly, the gates of CMOS transistors 120,123 are commonly connected to the 0, output terminal of level converter 20,. Whenever the output signal on Q, is high (ground potential) and the output signal on Q, is low (V,,') transistors and 121 are bielectrode 30. This is best illustrated with reference to FIG. 8. Wave form A represents the relatively low level 32 Hz square wave input signal to level converter 20,
present on lead 19,-. Wave forms B and C illustrate the- 32 Hz relatively high level output signals from shaper 29 present on output terminals Q Q respectively.
Wave form D illustrates the relatively low level control terminals Q, and Q, respectively. Wave form G illustrates the output signal from transfer gate 22, coupled to display segment 24,. Wave form H illustrates the signal from terminal Q coupled to common electrode 30 of liquid crystal display 25. For economy of space all of the above wave forms are represented in abbreviated form indicated by thebroken'central portion.
When wave forms G and H are in phase, the potential difference between display segment 24, and common electrode 30 is zero and the segment 24, is off. Conversely, when wave lforms G and H are out of phase a striking potential is established between segment 24, and common electrode 30 and segment 24, is on. The relative phase of wave forms G and H is determined by control waveform D. When this control signal is true, wave forms E and F are false and true respectively, and wave form G follows wave form H. When wave form D is false wave forms E and Fare true and false, respectively, andwave form G is oppositely phased from wave form H. Thus, with segment 24, initially off, indicated by the hatched area, when wave form D transitions false segment 24, is turned on as indicated by the unhatched area. When wave form D again transitions true, segment 24, is again turned off. 1
In the preferred embodiment, each segment 24, is operated in an AC. mode by reversing the direction of the potential between the segment and common electrode 30 at the arbitrary rate of 32 Hz. This mode of operation of all character segments is utilized in order to prolong the life of liquid crystal display 25. When the preferred embodiment is used to drive other types of relatively high voltage display devices, A.C. operation 20 -20, and level converter 20,, transmission gates 22 22,-, and shaper 29 may be omitted.
The entire electronic time keeping and display system disclosed herein can be virtually fabricated from a single integrated circuit chip, the outline of which is outlined in FIG. 1, by the phantom-lined border indicated by reference character C. As indicated by this Fig, the only components which are not included in the single integrated circuit chip are oscillator crystal 12, low voltage source 26, which must be removable when exhausted, and a portion of regulated voltage converter 27. With reference to FIG. 6, those elements ofregulated voltage converter 26 which are not housed in the single integrated circuit chip, also outlined in phantom in this Fig, are resistor 42 and the discreet elements of voltage converter 44: viz, transistor 52, inductor 53,
diode 54 and capacitor 55. Thus, only seven circuit elements one of which must be readily replacable are carried externally of the single integrated circuit chip. As will be evident to those skilled in the art, this enables the electronic time keeping system of the invention to be fabricated and assembled at an extremely low cost. I
Referring again to FIG. 1, liquid crystal display 25 comprises a separate physical package, indicated by the phantom-lined border D, from the integrated circuit chip, and may be arranged relative thereto in any convenient manner. In one suitable packaging arrangement employed in the preferred embodiment, the liquid crystal display package D is mounted above the integrated circuit chip, and this assembly is placed in a watch case with the liquid crystal display characters visible through the watch case crystal. Other equally suitable mounting arrangements will occur to those skilled in the art.
As will now be evident to those skilled in the art, the electronic time keeping and display system disclosed herein provides a highly accurate, readily visible time display and is sufficiently small to be easily accommodated by the various types of watch cases known in the art. Further, the disclosed system is powered by a single, readily available low cost battery which is easily replacable when exhausted. Moreover, due to the low voltage and current requirements, the latter amounting to an average drain for the entire circuitry of only approximately microamperes, and the resulting low power consumption of the electronic circuitry, electronic watches constructed according to the invention can operate on the same low voltage source in excess of one year before replacement of the source becomes necessary.
As will be further evident to those skilled in the art, the level converters utilized in the electronic time keeping system enable the low voltage time control signals to control the operation of the high voltage display without consuminggreat quantities of current, thereby contributing to the efficient low power operation of the entire system. In addition, the regulated voltage converter utilized in the electronic time keeping system provides a well-regulated source of relatively high voltage for operating the level converters and the display also without consuming substantial amounts of current, which further contributes to the efficient low power operation of this system.
While the above provides a full and complete disclosure of the preferred embodiment of the invention, various modifications, alternate constructions and equivalents may be employed without departing from the true spirit and scope of the invention. Therefore, the above description and illustrations should not be construed as limiting the scope of the invention which is solely defined by the appended claims.
What is claimed is:
L'An electronic timekeeping system characterized by low power consumption, said system comprising a source of relatively low DC. voltage;
means for converting the output from said source of relatively low voltage to a relatively high D.C. voltage;
a source of relatively low voltage clock pulses;
a time signal generator coupled to said source of clock pulses forproviding a plurality of time signals having a magnitude of the order of said low voltage, said clock pulse source and said time-signal generator being-coupled to and powered by said source of relatively low DC. voltage; and
level converting means coupled to said time signal generator and said voltage converting means for converting individual ones of said plurality of low voltage time signals to display actuation signals having a magnitude of the order of said relatively high DC. voltage. i
2. The apparatus of claim 1 further including display means coupled to said level converter means and operable by said relatively'high voltage display actuation signals for generating visible time indicia in response to said time signals. I v
3. The apparatus of claim 2 wherein said display means comprising a liquid crystal display having a plurality of seven-segment digit characters.
4. The apparatus of claim 1 wherein said voltage converting means includes means for maintaining the magnitude of said relatively high voltage above a predetermined threshold value.
5. The apparatus of claim 4, wherein said maintaining means includes a threshold detector for generating an enabling signal when the magnitude of said high voltage decreases to said predetermined threshold value.
6. The apparatus of claim 5, wherein said maintaining means further includes sample means for periodically sampling the output of said threshold detector, and sense and enable means for generating a control signal adapted to actuate said voltage converting means in response to the generation of said enabling signal.
7. The apparatus of claim 6, wherein said sample means includes means for limiting the duration of each sampling period to a small value relative to the period therebetween.
8. The apparatus of claim 7, wherein the duration of each of said sampling periods is approximately 1 millisecond and the period therebetween is approximately 250 milliseconds.
9. The apparatus of claim 1 wherein said time signal generator includes a minutes counter and an hours counter.
10. The apparatus of claim 9 wherein said time signal generator further includes a time adjust circuit for individually adjusting said minutes counter and said hours counter.
11. The apparatus of claim 1 wherein said level converting means includes means coupled directly to said source of clock pulses for converting said relatively low voltage pulses to relatively high voltage display actuation signals for indicating that said electronic timekeeping system is operational.
'12. The apparatus of claim 1 wherein said level con- I verting means comprises a plurality of level converters 13. The apparatus of claim 12 further including an additional level converter coupled to said time signal generator for providing a relatively high voltage reference signal, and a plurality of transfer gates each coupled to a different one of said level converters and said additional level converter for generating said display actuation signals in response to said relatively high voltage control signals.
14. The apparatus of claim 13 further including means coupled to said additional level converters for shaping said high voltage reference signal.
15. The apparatus of claim l3 wherein said additional level converter provides a periodic high voltage reference signal having a frequency substantially higher than the frequency of said control signals.
16. In an electronic watch having a means for providing a relatively low D.C. supply voltage, a source of reference clock pulses, a timekeeping unit for providing a plurality of time indicating signals in response to said clock pulses, said clock pulse source and said timekeeping unit being powered by said low voltage supply means, a display operable at a relatively high voltage for providing a visible time indication, and means for converting said relatively low voltage to said relatively high voltage the improvement comprising a plurality of level converting means coupled-to said timekeeping unit and said voltage converting means for converting each of said time indicating signals to a level having a magnitude of the order of said relatively high D.C. voltage, said improvement enabling said watch to operate with low power consumption.
'17. The apparatus of claim 16 wherein each of said level converting means comprises a level converter for converting the associated time indicating signal to a relatively high voltage control signal, and transfer means for generating a display actuation signal in response to said relatively high voltage control signal.'
18. The apparatus of claim 17 further including an 7 additional level converter coupled to said source for providing a relatively high voltage supply signal for said transfer means.
19. The apparatus of claim 17 wherein said level con- UNITED sTATEs PATENT OFFICE CERTIFICATE OF CORRECTION Patent NO. 3!8l5!354 Dated June 1974 Richard L. Sirocka et al It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:
On the title page correct the designation of the first inventor by cancelling "Strocka" and inserting "Sirocka.
Signed and Scaled this I Twenty-sixth Day of October 1976 [SEAL] A nest:
RUTH C. MASON Arresting Officer C. MARSHALL DANN Commissioner oflarents and Trademarks UNITED sTATEs PATENT OFFICE CERTIFICATE OF CORRECTION Patent NQ. 15,354 Dated June 11, 1974 Inventor) Richard L. Sirocka et al It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:
On the title page correct the designation of the first inventor by cancelling "Strocka" and inserting "Sirocka.
Signed and Sealed this Twenty-sixth Day'of October 1976 [SEAL] Arrest:
RUTH C. MA'SON C. MARSHALL DANN AHPSII'IS ff Commissioner nfPatenls and Trademarks
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|U.S. Classification||368/84, 968/962, 345/38, 368/85, 307/38, 968/889|
|International Classification||G04G99/00, G04G9/00, G04C10/00, H03K5/02, G04G9/12, G04G19/02|
|Cooperative Classification||G04G9/12, G04G19/02, H03K5/023|
|European Classification||G04G9/12, G04G19/02, H03K5/02B|