|Publication number||US3820108 A|
|Publication date||Jun 25, 1974|
|Filing date||Mar 10, 1972|
|Priority date||Mar 10, 1972|
|Publication number||US 3820108 A, US 3820108A, US-A-3820108, US3820108 A, US3820108A|
|Original Assignee||Optel Corp|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (26), Classifications (15), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
7 1 f? United States 3,820,108 Luce June 25, 1974 DECODER AND DRIVER CIRCUITS 3,485,033 12/1969 Langley 340/334 PARTICULARLY ADAPTED O USE WITH 3,540,209 11/1970 Zatsky et a1. 340/324 R 3,541,543 11/1970 Crawford et a1. 340/324 R LIQUID CRYSTAL DISPLAYS 3,581,308 5/1971 McNaney 340/336  Inventor: Nunzio A. Luce, Trenton, NJ.
73 A I 0 t I Primary Examiner-John W. Caldwell 1 sslgnee p e Corporation Xddlesex N J Assistant Examirzei-Marshall M Curtis Fllcdi fl 1972 Attorney, Agent, or Firm-.l0el F. Spivak, Esq.  Appl. No.: 233,669
4  ABSTRACT  U.S. Cl 340/336, 350/160 LC A d r-dri r network for energizing a liquid crys- 51 Int. Cl. G09f 9/30 tal p y used in a timepiece to cause the same to  Field of Search... 340/324 R, 336, 334, 324 M; provide y one of a plurality of presentations accord- 350/160 LC ing to any one of a number of coded formats. The decoder-driver circuit uses bidirectional devices ar-  References Cit d ranged in series paths to minimize components and in- UNITED STATES PATENTS crease 3,204,234 8/1965 Nakauchi 340/336 10 Claims, 5 Drawing Figures (WM/J10 j [mu/0 [kw/71x amt/4y l i 125 irr1 /Z I v 1 I Z/P/I K/P l A 11 1 Z/ l f I l I 1 1 0mm.- q Jim); 4' 4 4 647/449 41/4/0755 7 a --n #00,? W
4 rat/Mix rm m M: L v
- sin/Ma 106/6 xm 01:. L gut/mm 1 l l (327684692) firm/a .SW/ffl/ PATENTEDJUNZS I974 SHEET 1 0f 3 1 DECODER AND DRIVER CIRCUITS PARTICULARLY ADAPTED FOR USE WITH LIQUID CRYSTAL DISPLAYS This invention relates to decoding and driving circuitry and more particularly to such circuitry for utilization with liquid crystal displays.
BACKGROUND OF INVENTION Recently, liquid crystal displays in conjunction with integrated'circuits have been widely utilized as a valuable combination in digital equipment. Such combined devices especially offer great advantages in the field of timepieces. For example, the digital electronic wrist watch is now a reality. As is well known certain watches which are electronic in nature are available to the consumer. The design and fabrication of a wrist watch using a liquid crystal display and suitable integrated circuitry has been discussed in various articles and other prior art. In any event, in any consumer product there is a desire to build as a reliable device as possible, while maintaining an economical product.
In regard to any electronic product a portion of the cost is directed towards the amount of circuitry utilized and the complexity of the circuitry. Basically, it is safe to say that as the complexity of the circuitry decreases and as the number of components decreases so does the cost. A decreasing component number is further evidenced by an overall increase in the reliability of the product. 1
Due to the nature of operation of an electronic timepiece one desires a relatively stable oscillator. Such an oscillator may utilize a crystal device which can provide a frequency stability within a few parts per million per year. In general, the higher the frequency of the oscillator the more accurate the timekeeping of the watch will be.
Naturally there is a trade-off in regard to cost in determining the frequency. In any event, the frequency of the oscillator is much higher than the normal repetition rates which are utilized in present timepieces. The output frequency of the oscillator must be divided down in order to produce a pulse train of a 1 Hz. rate to provide the timekeeping function. Again for economical reasons, one must utilize cascaded counters. These counters of course operate according to binaryformats. The outputs eventually have to be decoded in order to drive a-suitable display. Due to such considerations an integral part of such a timepiece must be a decoding matrix whose function is to convert the counter outputs into suitable signals for driving a display. Usually such a decoder has to be isolated from the display elements, or additional power is necessary to drive the display elements. This therefore requires driver circuitry, which circuitry exists separate and apart from the decoding circuitry. As indicated above, it is desirable to reduce the amount of circuitry in order to reduce cost and increase reliability.
It is therefore an object of the present invention to provide novel decoder and driver circuits which can be used to directly operate a display, and particularly adapted as a decoder-driver for a liquid crystal display utilizing common circuit components.
DESCRIPTION OF PREFERRED EMBODIMENT A decoder driving apparatus to be used in conjunction with a display, said display being of the type including a first common electrode and a plurality of display electrodes, the electrodes being adapted to be activated by a source of bidirectional potential having first and second terminals for being connected across a display with said first terminal connected to said common electrode of said display and said second terminal connected to any desired one of said plurality of display electrodes, said display capable of indicating a different one of a plurality of presentations according to which of said display electrodes are connected to said second terminal of said source, the decoder driver apparatus comprising a plurality of bidirectional active devices each having an input, output and common electrode, means for coupling a first plurality of said devices in a series path between one of said display electrodes and a circuitterminal adapted to be coupled to said second terminal of said source of energizing potential, and means coupled to said input electrodes of said first plurality of devices to cause a low impedance path to appear between said output and common electrodes of said active devices, to cause said series path to provide a low impedance return path to said second terminal thereby activating said display electrode.
BRIEF DESCRIPTION OFDRAWINGS FIG. 1 is a block diagram of an electronic timepiece useful in explaining the operation of this invention.
FIG. 2 is a circuit schematic of a decoder driver network according to this invention using bidirectional field effect devices.
FIG. 3 is a front plan presentation of a seven segment display useful in explaining the operation of this invention. i
FIG. 4a is a detailed schematic diagram of an alternate embodiment of a decoder driver circuit according to this invention employing complimentary symmetry devices.
FIG. 4b is a table showing outputs states of the counter for application to the decoder.
DETAILED DESCRIPTION OF FIGURES Referring to FIG. 1 there is shown a block diagram of a digital timepiece. Numeral 10 references a crystal oscillator and divider module. For purposes of explaining the operation of the system let us assume that the crystal oscillator operates at a frequency of 32,768 Hz. Therefore, in order to obtain an output frequency of, for example, 64 Hz. one would have to divide the above noted frequency by 512. It is also noted that 512 is a binary number and therefore the dividing chain incorporated in module 10 can consist of a conventional binary counter comprising a plurality of cascaded bistable multivibrators. Such counting stages exist either in the form of monolithic integrated circuits or as MOS devices and are easily obtainable and readily available.
The output of the counter is a signal having a repetition rate of 64 Hz. This is applied to another divider 11 which divides the 64 Hz. signal by a factor of 64 to obtain at an output thereof a 1 Hz. signal. This of course is indicative of seconds and can be utilized in conjunction with additional circuitry to perform timekeeping. A 32 Hz. signal is also provided in counter 11 and is applied via inverters l2 and 13 to a common terminal of a segmented liquid crystal display 15. Basically, the liquid crystal and the principles of operation of the same have been discussed in detail in various papers. However, a brief description will be given.
Nematic liquid crystals are organic materials made up of rod-like molecules. The term liquid is utilized because of the physical characteristics of the material. These materials are capable of being poured while further possessing the optical properties of a crystalline solid. The nematic materials are temperature sensitive. Accordingly, at low temperatures the material is a solid and at high temperatures it is an isotropic liquid. The transititions to the isotropic state are sharp, reversable and reproduceable. Liquid crystal display 15 can be fabricated to operate according to the principles of dy namic scattering. A basic liquid crystal cell consists of a liquid crystal material sandwiched between two pieces of transparent conductive coated glass. The liquid crystal molecules are highly birefringent and are in an ordered structure. The operation is relatively simple. With no voltage applied across the glass plates the cell is transparent. When a voltage is applied a resultant current causes turbulence which is a disruption of the ordered structure. This disruption causes the cell to appear milky white, and hence light reflective. The change in appearance is due to light scattering caused by changes in the index of refraction in the material about the region of disruption. In order to utilize a liquid crystal display in a timepiece the following characteristics are desirable:
1. Must be capable of operating at relatively low power;
2. Have a relatively long life;
3. Have an attractive physical appearance;
4. Be capable of operating for wide temperature ranges.
Liquid crystals in general are sensitive to both moisture and oxygen and in order to accomplish long life the liquid crystal material is preferably packaged in a hermetically sealed unit. Such materials have been developed and are presently available. The liquid crystal display 15 as indicated is segmented. The display has one common terminal and a plurality of segmented terminals in order to provide the requisite number of digits for displaying time. For example, the display may be a seven segment 3 /2 digit unit with a colon. The digits should be relatively small and still present good overall appearance. To achieve this a display which is approximately .123 inch by .184 inch is available with an active display length of .8 inch. The display can operate at 15 volts and has a nominal power dissipation of 15 microwatts with a contrast ratio that is greater than to one. Such displays are available from Optel Corporation, Princeton, New Jersey, the assignee herein.
As will be described subsequently the common terminal of the liquid crystal display is driven via a flipflop stage in divider 64 via inverters 12 and 13 at a frequency of 32 Hz. The one cycle output from divider 11 is applied to a divider 16 which performs a division by 60 to obtain at the output of divider 16 a pulse train having a repetition rate of 1/60 a second. The 1 Hz. signal is applied to a gating circuit 17 which receives the 1 Hz. signal and the l/60th Hz. signal to provide at an output a signal indicative of minutes. This signal is applied to a minutes counter 18 which advances its count by one for each pulse applied via a gating circuit 17. The output of the minutes counter is applied to a gating circuit 19 which also receives the 1 Hz. signal. The gating circuit 19 produces a pulse for every 60 pulses accumulated by the minutes counter 18. This output pulse is of course synchronous to the 1 Hz. signal. Therefore, the output of the gating circuit 19 consists of one pulse per hour and this pulse is applied to an hours counter 20. As previously indicated both the minute counter and the hour counter are digital devices and operate according to a binary or binary coded decimal format. Hence, these binary formats have to be dccoded to provide compatability with normal time indications.
There is shown a decoder 21 and a decoder 22 each respectively associated with the minutes counter 18 and the hours counter 20. The outputs of these decoders 21 and 22 are applied to respective driver circuits 23 and 24 which are in turn coupled to the segment electrodes of the liquid crystal display 15 in order to provide a proper digital display. As seen from FIG. 1 a conventional approach would be to use a separate decoder module such as 21 and 22 to drive a separate driver circuit such as 23 and 24. The dashed lines surrounding the two modules are included to indicate the structure to be covered by this invention. This structure namely is a combined decoder-driver assembly useful to reduce the number of components and circuit complexity, therefore achieving an increased reliability of the final timepiece.
Numeral 30 represents setting logic circuitry which basically is used to set the timepiece for different times or for initial adjustment. The function of the setting logic 30 is to apply higher frequency pulses to the minute and hour counters 18 and 20 in order to provide easy setability without using excessive time.
Referring to FIG. 2 there is shown a decoder driver circuit according to this invention utilizing P channel MOS devices. Reference numerals 32 and 33 represent two inverting circuits which may be ordinary amplifiers or operational devices which in essence serve to invert the polarity of the liquid crystal drive signal which, as indicated in FIG. 1, is 32 Hz. The output of inverter 32 is coupled to the liquid crystal common electrode 34, while the output of inverter 33 is applied to the MOS decoding and driver circuitry. The MOS devices shown are P channel devices. The liquid crystal display 15 requires an alternating current driving source and hence the P channel devices are bidirectional switches. The outputs of the circuits as will be explained are connected to the appropriate segments of the display each separately indicated as (1,, b 0 d e f and g These circuits serve to swtich between the common electrode 34 and the various segments in a bidirectional manner. When a P channel switch device is turned on the current flows through the liquid crystal in one direction for one half cycle and the reverse direction for the other half cycle. Since the P channel device is symmetrical there is relatively little DC offset on the display. In any of these bidirectional switching circuits one desires to have the leakage current of the switch in the off state as small as possible because of the relatively high impedance associated with the display segments. Such P channel devices can be designed to have leakage currents of 10 nanoamps or less for relatively large temperature variations and hence more than adequately serve to perform the necessary switching. If the leakage current of the P channel device becomes a problem, one can further assure reliable operation by shunting the device with another device by applying approximately phased signals from a driving source to assure adequate on-off display operation.
The circuit operates as follows: The outputs from a binary or other coded gaunte are zgplied to the terminals designated as A, A, B, B, C, and D. Segments as a, to g, are represented by their own binary code. Assume that the a, segment of the liquid crystal display is to be activated. As can be seen this segment terminal a, is coupled to the MOS devices 40, 41 and 42. These devices have their output terminals connection in shunt. Since each device 40, 41 and 42 is symmetrical The tabulation below indicates the segments which are activated according to the states of t he counter respectively designated as A, A, B, B, C, C, and D.
LlQUlD CRYSTAL DISPLAY SI-IGMliNI' ACl'lYAllON R SEGMENTS D B A i. t. m. f. 0 0 o o I I l b c 0 O l) l l l U 0,, b 11,. XI 0 0 l 0 (l l 1 1, g, 0 l l l 0 0 lu lvjivgl O l 0 0 U l l t. hfi. g, 0 l 0 l 0 l 0 n h n fi-gt 0 l l U U 0 l t. 1. i 0 l 1 1 0 o 0 n hvh h hfhg. l 0 0 0 l I l li lr ly lr K1 l '0 U l l l 0 This State Not Permitted by Counter I 0 l 0 l 0 I do. I O l l l O 0 do. I O U 0 l I do. I l 0 l 0 l 0 do. I l l U 0 O I do. I l I I 0 0 (J 3 the conventional dram and source electrodes can be interchanged. As indicated the gate electrodes of devices 40, 41 and 42 are respectively connected to the inputs A, B, and C from the binary type counter. The upper common electrode of the three devices is coupled directly to the segmented electrode a, while the bottom common electrode is coupled to the common electrode connection of the P channel devices 43, 44, 45 and 46. The other common electrode of these devices being coupled directly to the inverted 32 Hz. drive frequency available at the output of inverter 33. Assume now that the counter provides a count where the A and B leads are at a logical one. Further assume that the C lead is also at logical one indicating a logical zero for C and further assume that the D signal is also logical zero. In this manner the MOS devices 40, 41 and 42 are'on or exhibit a low impedance bidirectional path between their common electrodes. It is also noted that device 44 is also on due to the fact that its gate is also coupled to the B output of the counter. This therefore provides a current return path between the a segment and the output terminal of inverter amplifier 33. It is also noted that device 44 is in cascode with devices 40, 41 and 42. Hence, the cascode configuration permits higher voltage drive and serves to allow the sharing of dissipation between the devices, therefore reducing the normal power dissipation in any one device. This cascode configuration thereby permits the segment designated as a, to be energized. The path is through the P channel devices 40, 41 and 42 and device 44.
The common electrode of the liquid crystal receives a 34 Hz. clock at one phase and the a segment receives a 34 Hz. at opposite polarity via the above noted P channel devices. The clock alternates polarity every half cycle, but since the devices are symmetrical, they conduct for either polarity and hence maintain the a segment of the liquid crystal display activated.
From the above table it can be seen that all digits from 0 through 9 can be displayed by the segmented configuration of FIG. 3. I
While there are 16 possible states evidenced by a four stage counter, it is well known to confine the count to ten, and to eliminate the counts representative of l l to 16 or binary 1010 to 1111.
It can also be seen from the above tabulation that in the majority of instances the return current path for each segment is through a series path provided by more than one P channel device.
For example, segment f may be activated via P channel device 48 and thence through P channel device 49, and then through P channel device 43, 44, 45 or 46. This, of course, specifies at least three devices in cascode, providing the above described advantages in voltage breakdown and power sharing.
The only instances where this does not actually hold true involve segments b and c However, this is no problem as one can design the four P channel devices '50, 51, 52 and 53 with this operation in mind, as these devices are only four out of 27. In any event, the output of inverter 33 can be fabricated as a P channel device which would appear in cascode with all devices in the above described decoder-driver circuit.
In this manner the circuit of FIG. 2 can be used as both the decoder matrix for the counter and the driver circuit for the segments. The series parallel configuration serving to greatly reduce device tolerance and breakdown ratings in regard to both current and voltage. For example, even in regard to devices 50, 51 and 52, there ar e conditions where device 51 conducts indicative of C and this is shunted by devices 54 and 55; or the only time device 50 is solely conducting is for the conditions when A and B are not both at logical one or A and B are not both at logical one. At all other times the C condition assures that device 50 is shunted by at least one additional path, thus serving to share current. The same conditions are applicable to devices 51, 52 and 53.
Referring to FIG. 4 there is shown a decoder-driver arrangement using complimentary MOS devices or a CMOS configuration.
Due to the fact that the liquid crystal display 50 requires an AC driving source, as previously indicated, bidirectional switches are necessary.
This decoder driver comprises a plurality of paired field effect transistors as 51 and 52. The devices 51 and 52 are respectively a N channel device and a P channel device, connected in shunt. The plurality of devices are activated by the outputs of a counter (four stage) indicated by the A, A, B, E, C, C, and D, D inputs.
A flip-flop or bistable multivibrator 53 is shown. The input of the flip-flop 53 is coupled to a source of pulses such as may be derived from the divider 11 of FIG. 1. Since a bistable performs a division of two, one may use the 64 Hz. signal directly as a trigger to then obtain 32 Hz. opposite polarity output signals at the two output electrodes of the flip-flop 53. One output terminal of the flip-flop 53 is connected to the common terminal 54 of the liquid crystal display 50. The other output terminal of the flip-flop 53 is connected to a drive line 55 associated with the decoder-driver array.
The liquid crystal display 50 is again a seven segment display, wherein the segment electrodes are respectively designated as a b d e fi, and g Each of these segment electrodes is connected to a designated point in the decoder-driver matrix and are activated according to a decoding format, similar to that used in conjunction with FIG. 2, and as shown from the logic table of FIG. 4.
It can be seen from FIG. 4 that each pair of field effect transistors as 51 and 52 have their gate electrodes returned to opposite sides of a counter flip-flop output. For example the gate electrode of transistor 51 is coupled to the D output of the counter circuit, while the gate electrode of transistor 52 is coupled to th e D output of the counter. Hence, when D is one and D is zero, transistors 51 and 52 are both conducting. The P channel device will conduct on the negative clock cycle, while the N channel device conducts on the positive half clock cycle. Since the transistors are designed to be symmetrical, there is no apparent DC offset on the display.
In a similar manner each count obtained from the counter is represented by a unique activation of a seven segment display, as previously described. There are also multiple series paths provided in the operation of this decoder driver matrix and thus the advantages of power sharing occur in this configuration as well.
The decoder-driver network serves to provide a bidirectional current return path from the liquid crystal common electrode 54 to the network common electrode 55.
Let us assume that it is desired to access the d segment of the display for the following conditpn of the counter, A= l, A=O, B= l, =O, C=O, C= l, and D 0, D l. Proceeding with the D and D input lines from the counter, it is seen that transistors 60 and 61 are both activated. This is due to the gate electrode of transistor 60 connected to the D line which is at one, and the gate electrode of transistor 61 connected to the D line which is at zero. Hence, there is a first bidirectional path from d via transistors 60 and 61.
Transistors 62 and 63 are also activated because g is at zero and B is at one. Thus, there is a second low impedance path via transistors 62 and 63 to the common return line 55. Hence, segment at; is activated.
It can also be seen that because A is logical one, and A is zero transistors 64 and 65 are both biased off, thereby blocking this path to common. But if A was zero and A was one, these transistors 64 and 65 would also provide a return for the d segment even if B was at zero.
It is of course understood that the counter inputs can accommodate a number of useful counting formats, such as divide by l2, 10, six, five, two and so on. They can be straight binary devices or binary coded devices. The important factor being that a different number of display segments be activated for each unique count to enable proper time display.
Such counting arrangements are well known in the art, as is the formation of truth tables to enable proper decoding.
The novel aspects of this invention residing in the unique presentation of decoder driver circuits to networks to enable dual operation.
1. Apparatus used for driving a display, said display being of the type including a first common electrode and a plurality of display electrodes, said display adapted to be activated by a source of bidirectional potential having first and second terminals for being connected across said display with said first terminal connected to said common electrode of said display, said display capable of indicating any different one of a plurality of presentations according to which of said display electrodes are connected to said second terminal of said source, in combination therewith apparatus for selectively connecting said second terminal to any desired ones of said display electrodes, comprising:
a. a plurality of bidirectional field effect transistors each having a source electrode, a drain electrode and a gate electrode, said field effect devices operative in a first state to provide a low impedance bidirectional current conducting path between said source and drain electrodes when said gate electrode is biased by a first operating potential and in a second state to provide a high impedance between said source and drain electrode when said gate is biased by a second operating potential,
b. means for coupling said second terminal of said source to any desired one of said display electrodes including a series path formed by at least two of said field effect transistors having the source electrode of one directly connected to said desired one of said display electrodes and the drain electrode of said one directly connected to the source electrode of said other, with the drain electrode of said other directly connected to said second terminal of said source,
0. a code generator capable of providing a series of codes each manifesting a different indication capable of selecting a different display presentation, said codes defined by two potential levels which correspond to either said first operating or said second operating potential dependent upon the code provided, said code generator having a plurality of output terminals each providing either of said operating potentials dependent upon said code provided, and
d. means coupling a predetermined one of said output terminals of said code generator to said gate electrode of said one transistor and another predetermined one of said output terminals to said gate electrode of said other transistor, whereby when said code generator is providing said first operating potential at said predetermined output terminals, said display electrode is connected to said second terminal of said source through said low impedance path provided by said at least two field effect transistors both operating in said first state and to provide said high impedance path between said display electrode and said second source terminal when either of said predetermined code generator output terminals is providing said second operating potential.
2. The apparatus according to claim 1 wherein said display comprises a liquid crystal display having a first common electrode and a plurality of segment electrodes.
v 3. The apparatus according to claim 1 wherein said plurality of bidirectional field effect transistors are a plurality of MOS devices each having a drain output 5. In a liquid crystal display of the type having a comv mon electrode and a series of segment electrodes, said display adapted to be energized by a source of bidirectional potential, said source having a first terminal connected to said common electrode and a second terminal to be connected to any desired one of said segment electrodes, in combination therewith apparatus for selectively connecting said second terminalof said source to a desired one of said segment electrodes, according to a predetermined code format, comprising:
a. a plurality of bidirectional field effect transistor devices, each having a gate input electrode, a source electrode and a drain electrode, and operative to provide in a first operating mode a low impedance bidirectional path between said source and drain electrode upon application of a first biasing potential to said gate electrode, and operative in a seeond mode presenting a high impedance between said source and drain electrodes upon application of a second biasing potential to said gate electrode,
b. means for coupling at least two of said plurality of devices in a series path between a selected one of said segments and said second terminal of said bidirectional potential source, said remaining devices of said plurality being coupled in a similar series path between said other segments, each of said paths including at least two of said devices arranged with the source electrode of one of said devices connected to said selected segment, the drain of said device connected to the source of the other device and said drain of said other device connected to said second terminal of said bidirectional source,
c. code generating means having a number of individual output terminals, each terminal capable of providing a first state corresponding to said first biasing potential a second state corresponding to said second biasing potential, and
d. means coupling said gate electrode of said one device to a selected one of said output terminals and said gate electrode of said other device to another one of said output terminals, whereby each device has coupled to the associated gate electrode one of said output terminals of said code generating means, whereby when said code generating means is providing said first biasing potential, said selected segment is connected to said second terminal of said bidirectional source through said series low impedance path and when one of said output terminals of said code generating means is providing said second biasing potential, said selected segment is isolated from said second terminal of said bidirectional source by said high impedance.
6. The apparatus according to claim 5, wherein said plurality of bidirectional devices comprises a plurality of MOS devices each having an output drain electrode, a common source electrode and an input gate electrode.
7. The apparatus according to claim 6, wherein said plurality of MOS devices are P channel MOS devices.
8. The apparatus according to claim 5, wherein said code generating means comprises a binary counting chain.
9. The apparatus according to claim 5 wherein said liquid crystal display has seven of said segment electrodes and one common electrode.
10. In a liquid crystal display of the type having a common electrode and a series of segment electrodes, said display adapted to be energized by a source of AC potential connected between said common electrode and any selected one of said segment electrodes, in combination therewith apparatus for selectively activating any segment according to a predetermined code format comprising:
a. a plurality of MOS devices each having a gate, source and drain electrode, and operative to provide a low impedance bidirectional current conducting path between said source and drain electrodes, when said gate electrode is biased by a suitable operating potential, said devices arranged in a plurality of current conducting series path with at least a source electrode of a first MOS device connected to a drain electrode of another MOS device and said source electrode of said other connected to a drain electrode of a last MOS device, said series path formed between said segment electrodes and a suitable terminal associated with said source of AC potential, to provide a series of paths enabling a selected plurality of said segment elec-' trodes to be connected to said source upon activation of said gate electrodes of said MOS devices;
b. a code generator capable of providing a series of codes each manifesting a different indication capable of selecting a plurality of different segment connections to said source of AC potential; and
0. means coupling certain preselected ones of said gate electrodes of said MOS devices to said code generator to cause certain of said series paths to provide said low impedance bidirectional paths for each one of said series of codes.
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|U.S. Classification||345/52, 968/962, 326/108, 368/242|
|International Classification||H03K21/08, G04G9/00, G09G3/18, G04G9/12, H03K21/00|
|Cooperative Classification||H03K21/08, G09G3/18, G04G9/12|
|European Classification||H03K21/08, G04G9/12, G09G3/18|
|Jun 1, 1987||AS02||Assignment of assignor's interest|
Owner name: REFAC ELECTRONICS CORPORATION
Effective date: 19870526
Owner name: REFAC INTERNATIONAL LTD., 1551 FORUM PLACE, STE. 2
|Jun 1, 1987||AS||Assignment|
Owner name: REFAC INTERNATIONAL LTD., 1551 FORUM PLACE, STE. 2
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:REFAC ELECTRONICS CORPORATION;REEL/FRAME:004748/0436
Effective date: 19870526
Owner name: REFAC INTERNATIONAL LTD., FLORIDA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:REFAC ELECTRONICS CORPORATION;REEL/FRAME:004748/0436