|Publication number||US3821729 A|
|Publication date||Jun 28, 1974|
|Filing date||Mar 9, 1973|
|Priority date||Mar 24, 1972|
|Also published as||CA1025139A1, DE2214585A1, DE2214585B2, DE2214585C3|
|Publication number||US 3821729 A, US 3821729A, US-A-3821729, US3821729 A, US3821729A|
|Original Assignee||Siemens Ag|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (13), Classifications (10), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
United States Patent [191 Schultze m1 1 3,821,729 [451 June 28, 1974  Inventor: Manfred Schultze, Munic Germany  Assignee: Siemens Aktiengesellschaft, Berlin and Munich, Germany  Filed: Mar. 9, I973  Appl. No.: 339,565
 Foreign Application Priority Data Mar. 24, 1972 Germany 221 4585  U.S. Cl. 340/324 A, 315/18  Int. Cl. .Q. G061 3/14  Field of Search 340/324A; 235/197, 198;
 References Cited UNITED STATES PATENTS 3,597,757 8/1971 Vincent-Carrefour et al. 340/324 A IREPITITION MORY ADDRESS ADDRESS MEMORY SWITCHING STAGE Primary Examiner-John W. Caldwell,
Assistant Examiner-Marshall M. Curtis Attorney, Agent, or Firm-Hill, Gross, Simpson, Van Santen, Steadman, Chiara & Simpson 571 ABSTRACT An arrangement for illustrating characters which consist of charactersegments in which data is fed in in the form of code words by means of a character input device, such as a keyboard or a computer. A read only memory stores the character segment data for retrieval and display on a'data display device via digital- /analog converters and a deflection unit which causes deflection of a character creating element, such as an electron beam, in accordance with the character segment data. An adder is connected to the read only memory and is fed syllables of the-charactersegment data corresponding to angles by which the character to be illustrated is to be disposed with'respect to a coordinate .system or with respect to a character segment. The adder feeds the digital/analog converters by way of register and decoding apparatus.
6 Claims, 6 Drawing Figures CHARACTER GENERATOR l7l3 FLIP-FLOP DECODER PATENTEDJUN28 m4 31821; 729
SHEET 1 OF 5 INTENSITY MODULATOR 'E'I5L'$ 12 1L PICTURE TUBE CHARACTER e GENERATOR 13 DEECECTION 15X 16X UNITS r AMPLIFIERS az'm 12 2 ggggggqg: I-VII I Vm 1 =g I ADDRESS d I l il kw" as t] I 1 I: 35 I-X 1 Gama E 1 REe|sTER FLHLFLOP b I 22 XI-XVIU 28 I I [-X e READ QC 11 MERRY I I XHXH REGISTER XIX 30 I H M I hxxlv y 1 I I I I I I I l QATENTEBJUN281Q1LE 3821729 SHEET 3 0F 5 Fig.4
?ATENTEDJUH28 11114 38211729 SHEET 5 OF 5 Fig.6
111 X11 11111 11111 il i'i? li9E lk I 1 5 gg -R e11 51 lg 53 57 I I ADDE R REGISTER 1 g 59 5e G A I'E BACKGROUND OF THE INVENTION 1. Field of the Invention I This invention relates to an arrangement for the illustration of characters consisting of character segments in which data is fed into the arrangement in the form of code words by means of a character'data input de vice, and more particularly to such an arrangement in which the deflection of a character creating element, such as an electron beam, is effected through the utilization of a readonly memory which stores character segment data and digital/analog converter and deflection apparatus, depending on the character segment data.
2. Description of the Prior Art Theterm character, as used herein, is to be understood in its widest scope to include any type of symbol which is made up of one or more segments. Therefore, we are here concerned with alphanumeric characters including both letters and numbers; however, also of primary concernare graphic characters which constitute more or less complicated characters. A computer or a keyboard may be provided as a character data input device and those cases should be taken .into consideration in which such character data input devices are located relatively remote from the read only memory of a data display device so that the code words corresponding to the characters have to be transmitted by way of considerable distances in a generally known manner. a
A cathode beam of a'cathode ray tube, for example, can be provided as a character creating element which is deflected by means of a deflection unit of a cathode ray tube into several coordinate directions and render the individual character segments of the characters visible on the screen of the cathode ray tube.
However, the character creating element can also be constituted by an ink stream which is also deflected by means of the deflection unit into several coordinate directions in such a way that it writes characters on a strip-shaped material, or on sheet-shaped material. In addition, recording stylii and recording pins can be provided as character creating elements which are deflected by means of the deflection unit into several coordinate directions for inscribing the characters on appropriate media.
If by using a data display device and a great number of alphanumeric characters and also graphic characters are to be illustrated, it is generally desired to provide for the illustration of many such characters, in particular many graphic characters, in order to increase the accuracy of the illustration. The accuracy of a graphic illustration, for example, increases as the available number of character segments increases, which segments are directed into different directions and which are of different lengths. However, the larger the number of the characters to be illustrated, the more difficult it becomes to select these characters to be illustrated by means of a prescribed number of code words.
Further problems result in connection with the orientation of individual characters on the screen of the data display device. It is desired, in many cases, to illustrate certain characters, for example a square, in such a way that the inidividual segments of the square are always oriented in the same way with respect to a prescribed coordinate system.
Also, it may be desired to illustrate these squares in such a way that two sides of the squares lie parallel to the prescribed frame of the rectangular screen. It can, however, also be required that the sides of the square be oriented relative to the series of lines which are already illustrated. I
SUMMARYVOF THE INVENTION directions are oriented with respect to a stationary coordinate system; and it should also be possible to illustrate such characters and other characters in such a way that the directions of the individual character segments of these characters is dependent on character segments which are already illustrated.
According to the invention, an adder is'required whose inputs are connectedto outputs of a read only memory which stores character segment data. The
adder is set via these inputs by syllables of the character segment data corresponding to the angles. of the character segments which are to be illustrated. It should be noted here that the term syllable is directed to that portion of a total data word which defines the unique orientation of the character segment which corresponds to the data word. In addition to the aforementioned apparatus, a register, is required whose inputs are connected to the outputs of the adder and whose outputs are connected byway of gates to further inputs of the adder. The'arrangement according .to the invention is characterized in thatthe directions of the characters to be illustrated can be oriented in a simple manner with little effort of programming, either with respect to the fixed, prescribed coordinate system or with respect to a variable direction. In particular, the respective orientation of the character can be influenced by using the adder. If the syllables which characterize the angles of the segments to be illustrated are not changed in the adder, the directions of the illustrated character segments are oriented with respect to a fixed, prescribed coordinate system. If, however, in the adder data are added to the syllables, the directions of the illustrated character segments are dependent on such syllables as well as on the added data. Therefore, code words for defining the characters to be illustrated can be saved, since code words do not have to be assigned to all directions. A relatively low number of code words is sufficient in order to be able to illustrate all desired directions.
In order to illustrate with a small number of prescribed code words, as many characters as possible to influence the gates by means of code words data are stored in the read only memory for causing the release of respective control data. By means of these control data, and by utilizing a further decoder, a signal is provided which causes the BRIEF DESCRIPTION OF THE DRAWINGS Other objects, features and advantages of the invention, its organization, construction and operation will be best understood from the following detailed description of a preferred'embodiment of the invention taken in conjunction with the accompanying drawings, on which the same. components and signals have been given'the same reference characters, and on whichi FIG. 1 is a schematic block diagram of a data display device; a Y
FIG. 2 is-a'schematic diagram'of the character generator illustrated in FIG. 1;
FIG. 3 is a schedule which illustrates the data feeding of the read only memory of the present invention;
FIG. 4 is a graphic illustration showing several directions of orientation and corresponding assigned data of character segments;
FIG. 5 is a detailed schematic diagram'of a control stage, which is schematically illustrated in more: general form in FIG. 2, for the controlof the deflection of a cathode beam of a cathode ray tube; and
. FIG. 6 is a detailed schematic diagram of a control stage which serves for the changing of the coordinate system to which the directions of the characterseg,
ments'tobe illustrated have to be referred.
DESCRIPTION OF THE PREFERRED EMBODIMENTS opening or blocking of the 12 The picture repetition memory 12 is connected to control a character generator 13 which has three outputs 13b, 13c and Be. The output 13e is employed for controlling the intensity of an electron beam of a cathode ray tube 19.by way of an intensity modulator 14. The outputs 13b, 130 are connected to control the xand ydeflection of the'cathode ray tube 19 by way of respective digital/analog signal deflection units 15x, 15y and deflection amplifiers 16x, 16y, respectively. The data display device has the task of illustrating on the screen of the picture tube 19 several characters whose type and position can be influenced by means of the character data input device '11.
Data in the form of words are fed into the arrangement bymeans of the character data input device 11. By means of these words the characters to be illustrated are selected and shiftings of the illustrated characters, elimination of individual characters and the insertion of characters at certain points on the screen of the picture tube 19 are carried out. As mentioned above, a computer may be provided as the character data input device 11 and can be arranged, via a nonillustrated trans- 4 mission network, at a great distance from the picture repetition memory 12.
The words of the character data input device 11 are stored in the picture repetition memory 12. Since the picture of the picture tube 19 has to be regenerated constantly, the individual characters are written approximately fifty times per second. The words which serve for the selection of the characters are therefore received approximately fifty times per second from the picture repetition memory 12. By means of these words, also the sequence of the illustrated characters and therefore also their positionson the screen of the picture tube 19 are determined.
Generally speaking, the characters consist of several character segments. The data which characterize these segments are'designated in the following paragraphs as character segment data and are stored in a read only memory 23 (FIGS. 2 and 3) of the character generator 13. These character segment data define the form of the written character segments and their'brightness.
The character segment data are directed to the digital/analog converterslSx and 15y,.respectively, which create analog deflection signals for the deflection of the cathode beam in the x and y directions,respectively. These analog deflection signals are amplified by means of the signal deflection amplifiers 16x and 16y and'are directed to the x deflection coil and the ydeflection coil of the picture tube 19. The cathode beam of the picture tube 19 then writes the character segments.
In addition, a brightness signal is created in the character generator Band is amplified in the-brightness control stage 14 to control the intensity of the cathode beam of the picture'tube 19. If, therefore, the words are released from'the picture repetition memory 12 approximately 50 times per second for selecting a certain character, the respective character segment data are released by the character generator 13 and in further sequence brightness signals, as well as deflection signals, are created and thereby the cathode beam of the picture tube 19 is deflected in'such a Way that it writes the desired character segments and thus the characters.
FIG. 2 schematically illustrates the character generator 13 of FIG. 1 in greater detail. The character generator 13 comprises an address selection-circuit 21; an address counting register22, the read only memory 23,'a
register 24, a switching stage 25, further switching stages 26, 28, 30, 31, a decoder 32 and a flip-flop 33.
For ease and clarity of illustration, parallel lines are only illustrated as a single line. The roman numerals adjacent the lines designate the bits which are transmitted via these lines. One-line is provided for each bit. The two binary values are denoted O and l. Signals which carry a 0 value, are-referred to as 0 signals or 1 signals, respectively. The two conditions which can be assumed by the flip-flop are referred to in a similar manner as a 0 condition or as a 1 condition, respectively.
Words in the seven-bit-ASCII-Code are released from the output of the picture repetition memory 12 by way of the lines IVII. In addition to these seven bits, the bits VIII, IX O, X O are released to the address selection circuit 21.
The address selection circuit 21 basically comprises a switch 35 which can be conditioned to the fully shown switching position 350 and to the broken line illustrated switching position 351) and which is controlled by means of the switching stage 26 into one of these two switching positions. In the position 35a a total of ten bits are released to the address counting register 22 via the lines I to X. In the switching position 35b, the address selection circuit 21 is connected with the contact 0 of the switching stage 25.
The bits I to X are directed to the address counting register 22 and the bit XIV is directed by way of the line 27 as a control signal. The address counting register 22 is operated in a first operational mode or in a second operational mode depending on this control signal. In the first operational mode, the bits I to X, which are directed by the address selection circuit 21, are stored in the address counting register 22 and are released unchanged as an address word to the read only memory 23. In the second operational mode, the bits I to X are alsostored in the address counting register 22; however, with each clock pulse T the binary number which is provided by the bits I to X is increased by a binary l. The bits of the increased binary number are released as an address word via the output 22e to the read only memory 23.
The read only memory 23 stores 1,024 words of twelve bits each. The ten lines I to X which are connected to the input 23a serve as address lines. The storage organization of the bits of the read only memory 23 can be seen in FIG. 3 and is explained below following the description of FIG. 2.
The words which are released from the read only memory 23 with the bits XI to XXII are subjected to an interim storage in the register 24 and the bits VI to XX are released by way of the output 24b to the switching stage 25. The bits XXI and XXII are released by way of the output 24c to the control stage 26.
The switching stage 25 can be conditioned to assume the switching positions25a, 25b, 25c and 25d and is controlled by the control stage 26 in accordance with the binary values of the bits XXI and XXII which are applied to the input 26a and in accordance with the bits XXIII which is fed to the input 26b of the switching stage 26. In addition, the switching stage 26 controls the switch 35. The following table illustrates these relationships.
The switching stage 28 causes the deflection of the cathode beam of the picture tube 19 illustrated in FIG. 1. The amount of deflection and the direction of deflection depends on the values of the bits X1 to XVII which essential in connection with the present invention and are therefore not described herein in greater detail.
The bits XI to XV are directed to the decoder 32 and the bit XXV is released via an output of the decoder 32. The decoder is constructed in a manner well known in the art using known components so that a detailed explanation of this structure is superfluous. The following table illustrates the manner in which the values of the bit XXV are dependent on the values of the bits XI to XV;
' TABLE2 xv x1v x111 x11 x1 xxv The flip-flop 33 can assume two stable conditions, as noted above. In its 0 condition it provides a 0 signal at its output d, and in its 1 condition it releases'a 1 signal at the output d. Starting from one of the two conditions, the flip-flop 33 always assumes a different condition than the previous'one if a signal is fed thereto via the line XXV and its inputs 33a and 330 and if simultaneously a pulse signal is applied at its input 33b.
FIG. 3 schematically illustrates the four storage areas of the read only memory 23. Altogether this read only memory can store 1,024 words of twelve bits each. The tabular form of this illustration includes some address words. These address words consist of the bit I to X. Entered thereunder are the word values in accordance with the binary value format starting from 2 to 2 The storage area 230 is reserved for a first index. It contains addresses of the segment data of alphanumeric characters and control data. This storage area 23c storesa total of 128 words which are addressed with the bits I to VII and with the bits VIII 0, IX 0 and X 0. g
The storage area 23d is reserved for a second index. It contains addresses of the segment data of graphic characters and control data. Again a total of 128 words can be stored which are addressed with the bits I to VII and with the bits VIII 1, IX O and X O.
The character segment data for alphanumeric characters are stored in the area 23e in the form of three times 128 words (384 words). The character segment data for graphic symbols are similarly stored in thestorage area 23f, also in the form of three times 128 words.
The subdivision of the read only memory 23 into individual storage areas depends on the number of the character segments and on the number of the control data to be stored and can otherwise be carried out in any other suitable manner.
It is a precondition for the explanation of the operational mode of the switching arrangement according to FIG. 2 that in the address selection circuit 21 the switch 7 35 is conditioned to the position 35a and that the switching stage 25 is conditioned to the position 25a.
In addition, it is assumed that the bits I to VII of the picture repetition memory 12 and the bits VIII =0, IX and X 0 characterize the letter A. With this precondition, the address counting register 22 receives the bits I to X, stores then and releases them via the output 22a as an address word to the read only memory 23. These bits I to X are enteredv in line 2 of FIG. 3. The
first word which is read from the storage area 230 is tions 25c and 35b. The address counting register 22 is controlled by way ofthe output 260 of the switching stage 26 in such a way that it operates in the first operational modeQThe bits XI to XX of the first word are therefore subject to interim storage in the address counting register 22 and are thereafter fed unchanged as an address word into the read only memory 23. Thereafter, a second word is released by the read only memory 23 and is stored in the register 24. The bits of this second word'are the segment data of the first character segment of the letter A. I
Since a first character segment is concerned, the bits XXI 0 and XXII 0 are provided-so that in the case of the switching position 25b the bits IX to XX of the second word are stored in the registers of the switching stages 28, 30 and 31. Since the bit XXIV O in addition, the counted result'of the address counting register 22 is increased by a 1 withthe bits XXI 0 and XXII The bits XI to XVIII of the second word are applied The intensity of the-cathode beam on the picture tube 19 illustrated in FIG. I is controlled with the bit XIX of the second word.
3 With the release of the I signal from the output 280?,
the cathode beam has reached the final point of the first segment. If the cathode beam was intensity modulated, the first segment of the letter A will be visible on the screen'of the picture tube 19 illustrated in FIG. 1.
If in the second word the bits XXI'= 0 and XX 0, the counting result of the address counting register 22 v is-decreased by a l, the decreased count is fedto the read only memory 23 as a new address and the third word which is released by the read only memory 23 is again stored by way of the register 24 into the registers of the control stages 28, 30, 31 in the case where the switch 25 is in the position 2512. Therefore, all segments of the letter A are written, whereby this process is continued as long as the bits are XXI 0 and XXII 0.
If the bits which are read out of the register 24 are XXI 0 and XXII 1 and if, in addition, at the input 26!) of the control stage. 26 the bit is XXIII 1, this would mean that now also the last segment of the letter A has been written and the switches 25 and 35 are conditioned to their respective positions 25a and 35a. These are the switch positions from which the writing of the letter A was initiated.
In a similar manner, further alphanumeric characters can be written. Thereby, it was heretofore presupposed that the bit VIII =0 is released from the output (I of the flip-flop 33 so that the storage area 23c is controlled with the bits IX 0 and X 0.
After some alphanumeric characters have been written, it is asseumed that it is desired to write a graphic character on the screen of the picture tube 19. In order to be able to write such graphic characters, first the bits I' to X of the address word 1000100000 are fed by way of the address counting register 22 into the read only memory 23. With this. address word, the control data 10001000001 1 are read from the storage area 23c'with the bits XI to XXII. The switch 25 is conditioned to the position 25d in response to the bits XXI l and XXII 1 so that the bits XI to XV 10001 reach the decoder 32 which, as shown in TABLE 2, releases because of this bit combination, the bit XXV l 'to the flip-flop stage 33. This bit XXV 1 now causes the 1 condition of the flip-flop 33 so that in afurther sequence the bit VIII 1 is released at the output d.
Now the storage area 23c is no longer controlled 'with the bit VIII I, but thejstorage area 23d which contains the addresses of the segment data of graphic characters and control data. The bit combination of the bits I to VII shown in line 3 of FIG. 3 is no longer interpreted as the letter A, but as a graphic character. The word which is read from the storage area 23d isstored in the register 24. This word is the address of the segment data of the first segment of the graphic character. In this word, again, the bits are XXI 1 and XXII 0 so that the control stage 26 causes the switches 25 and 35 to assume the switching positions 250 and 35b.
The bits XI to XX of this word reach, like the bits of the first word for the letter A in the switching positions 250 and 3512, the address counting register 22 which again operates in the first-operational mode. The word is therefore fed as an address into the read only memory 23 and the memory 23 provides a word whose bits are the segment dataof the first character segment of a graphic character. By using the control stages 28 and 30, the individual segments of the graphic characters are written in the same way as the segments of the alphanumeric characters. Therefore, any number of segments of the graphic characters and any number of graphic characters can be illustrated. During this time, the flip-flop 33 is in its 1 condition and provides the bit VIII l to its output d.
It is assumed that the last graphic character has already been writtenand that now it is desired to return to alphanumeric characters. In order to carry out this operation, a further address word is fed with the character data input device having the bits I to X as follows:
0010100100. The storage area 234' is addressed with this address word and the control data 001010010011 are read out from the read only memory 23. By means of the bits XXI l and XXII 1 of these control data, again the switch 25 is adjusted to the position 25d and the decoder 32 is controlled with the bits XI to XV: 00101 which, according to TABLE 2, releases the bit XXV 0. With this bit XXV 0, the flip-flop 33 changes from its 1 condition to its 0 condition so that by way of its output d the bit VIII 015 released.
Therefore, again the very condition is achieved which existed at the initiation of the writing of the letter A. Again, this condition can be maintained as long as alphanumeric characters are to be written.
Up to this point, it was presupposed that the bits IX 0 and X 0. Therefore, with the combination VIII 0, IX 0, X 0, alphanumeric characters were written; whereas, with the bit combination VIII 1, IX 0, X 0, graphic characters were written. It is also conceivable to reserve further bit combinations for further classes of characters. For example, with the bit combination VIII 0, IX 1 X 0 in combination with the bits I to VII, a further storage area of the read only memory could be addressed and this bit combination could be assigned to a further class of characters. In such a case, the decoder 32 would have to supply output signals which make the random release of the bits VIII 0, IX 1 and X 0 possible and dependent on the bits XI to XV- The TABLE 2 illustrates combinations of the bits XI to XV effect the provision of the bit XXV 1. Not only is the condition of the flip-flop 33 changed with these two bit combinations, but also a further control is effected. In this exemplary embodiments, a signal is released by way of the output b of the decoder 32 to the control stage 30 which causes, with the bit combination XI to XV 10001 a modulation of the electron beam to a light condition and with the bit combination 01001 a modulation of the electron beam to a dark condition.
A character generator 13 which is particularly suited for the control of the cathode beam of the picture tube 19 of FIG. 1 has been described by means of the above discussion and reference to FIGS. 1 and 2. The character generator 13 illustrated in FIG. 2 can, however, also be used for the control of an ink recorder. In this case, a picture repetition memory 12 is not required and the data are directly supplied to the address selection circuit 21 of the character generator 13 from a character data input device 11. The character generator 13 which is illustrated in FIG. 2 can also be used in combination with other character arrangements insofar as these character arrangements can be controlled by means of signals created in the character generator 13.
It was already mentioned above that by using the control stage 28, the cathode beam of the picture tube 19 of FIG. 1 can be deflected. The deflection of the s e b is bsae i e 99n9 212t wigdis te &
the one hand, the direction into which the cathode beam shouldrnove innin order to reach from one point toanother point and, on the other hand, to indicate the distance of the two points. The deflection of the cathode beam should take place in sixteen directions in order to illustrate the character with sufficient accuracy. I
Referring to FIG. 4, a diagram is provided'which illustrates sixteen different directions. Each of thesse directions has been assigned a syllable having four binary digits. The positive abscissa direction is, for example, assigned to the syllable 0000. In a clockwise manner, the directions having the assigned syllables 0001, 0010, 001 1, etc follow.
If a voltage pulse of a certain amplitude is directed to the xdeflection coil of the picture tube 19 (F IG. 1) the cathode beam is deflected in the direction which has been assigned the syllable 0000. If a voltage pulse of a certain amplitude is applied to thex-deflection coil, and a voltage pulse of the same amplitude is applied to the ydeflection coil of the picture tube 19, the direction will result which has beenassigned the syllable 0010. If a voltage pulse of double amplitude is applied to the x deflection coil and a voltage pulse of single amplitude is applied to the ydeflection coil, the direction 0001 will result. By the combination of voltage pulses of single and double amplitude the cathode beam can be deflected in directions which enclose angles with the coordinate directions being smaller than 45. In the deflection coils of the picture tube '19, a current is provided which starts from the leading edge of the voltage pulses, which increases in atime wise linear manner, the increase being larger in response to larger amplitudes of voltage pulses. V I
FIG. 5 illustrates details of the control stage 28 of FIG. 2. The bits XI, XII, XIII, XIV are reserved for some of the directions illustrated in FIG. 4 and are applied to the switching stage 35. If, for example, the cathode beam is to be deflected in the direction of the +y axis, the syllable XI 0, XII l, XIII 0, XIV 0 is applied to the switching stage 35. The outputs of the switching stage 35 are connected by way of respective AND gates 36, 37, 38, 39 to a decoder 40. By using the decoder 40 with each word with the bits X1, XII,
XIII, XIV a word is assigned having the bits x, x, +2x,
TABLE 3 XI XII XIII XIV +x x +2x 2x +y y +2y 2y o 0 1 1 1 0 0 0 o 0 0 I 1 o 1 1 1 o o 0 1 1 o 0 0 1 0 o 0 0 0 o 1 0 0 0 o 1 o 0 1 o 0 0 1 0 1 0 o TABLE 3 #QQUQUHQQ.
If, for example, the syllable XI =0, XII 0, XIII the output of the NOT element 56 so that the gates 36 0, XIV l is applied to the decoder 40, the decoder 40,- the decoder will release the word +x O, -x 0, +2x =1, -2x 0, +y= 1,-y 0, +2y =0, -2y =0, 31 52. $9.9m
The outputs are, on the one hand,
The canes 49x and @Yachli v stealin Z c, d, e, and an output f. If a signal arrives at the inputs 49m and 49ya the count of the two counters 49x and 49y. are increased by one unit. If signals arrive at the inputs 49xb and 49yb, respectively, the counts of the counters 49x and'49y, respectively, are decreased by one unit. If a signal arrives at the inputs 49x0 or 49yc the counts are respectively increased by two units and if signals are fed to the inputs 49x4 and 49yd the counts are decreased by two units. If a signal should arrive at the inputs49xe or 49ye, the respective counters are resetto apredetermined initial count. I
The characters which are written on the picture tube 19 (FIG. 1) comprises several character segments. The bits XXX to XL or the bits L to LX are released and fed to the digital/analog converters x or 15y by way of the outputs 49xf and49yf of the respective counters 49x and 49y. These bits define the x and y coordinates of a final point of the last written character segments. If a signal is fed by way of the switching point 51 a type of image flyba'ck is effected and by the resetting of the counter the coordinates of the initial point of the first character'segment are adjusted, which in this specific case is written in the upper left corner of the screen. If
a signal is fed byway of the switching point 52 and the OR gate 53, only the count of the counter 49. :v is reset so that a type of line flyback is effected and the coordinates of an initial point of a character segment are ad- J t at s ls t gs Q h ima The bits XV, XVI, XVII, XVIII are fed to a counting register54 and stored therein. The release of this syllable with the bits XV to XVIII takes place if the signal is fed to the input 54a. If a signal is fed to the input 54b the count of the counting register 54 is decreased by one. The syllable with the bits XV to XVIII characterizes the length of a character segment to be illustrated.
to 39 and 41 to 48-become open.
Under theseconditions, the syllable having the bits XI to XIV indicating an angle, as shown in FIG. 4, is fed byway of the gates 36 to 39 to the decoder 40 which releases a word according to TABLE 3 by way of its outputs +x 2y. If it is also presumed that the counters 49x and 49y take counts whichare formed from zeros, the cathode beam of the picture tube 19 would be directed to a point whose x, y coordinates consist of zeros. Starting from this point, the cathode beam is controlled by the syllable released from the decoder 40 in a direction according to FIG. 4. Simulta neously, however, by means of the syllable released from the decoder 40, the counts of the counters 49): and 49y are varied in accordance with the conditions of the gates 41 to 48. These counts are the coordinates of the written character segment point referred to the x or y axis. Thereafter, the count of this counting register is decreased by a 1 because of feeding of a signal by way of the input b of the counting register 54. If the count of the counting register 54 is still differentfrom zero, the gates 36 to 39 and 41 to 48 remain open so that a second character segment is written in the same direction. The count of the counters 49x, 49y are, in such a case, the coordinates of the final points of the second character segment. Thereafter, the count of the counting register 54 is again decreased by a l and this ten which is composed of several character segments running in'the same direction.
In a further sequence, a further direction can be fed with the syllable XI to XIV and a further length with the syllable XV to XVIII, whereby the cathode beam is deflected in a similar manner as already described.
FIG. 6 illustrates in a more detailed manner the switching stage 35, which is also shown schematically in FIG. 5. The switching stage 35 comprises an adder 57, a register 58, a register 59, a plurality of AND gates 60, 61, 62, 63 and an OR gate 64. The four digit syllables are added in the adder 57, which syllables are fed, on the one hand, by way of the lines XI to XIV and, on the other hand, from the registers 58 and 59 by way of the AND gates 60-63. The adder 57 only takes into consideration transfers insofar as such transfers refer to the four illustrated stages of the adder 57. The largest number which can be released by the adder 57 is the binary number 11 11 corresponding to the decimal number 16.
The syllables which are released from the adder 57 are stored in the register 58 and from the output of the register 58 the syllables are on the one hand fed to the gates 36 to 39 which are illustrated in FIG. 5 and, on the other hand, the syllables are fed to the registers 59 which is illustrated in FIG. 6. The register 59 only stores a fed syllable if the input 59a receives a 1 signal. If a is received at the input 59a, a syllable which is fed by the register 58 is not stored. If a 1 signal is fed by way of the input 59b, the contents of the register 59 is erased so that the register stores only 0 signals. If, for example, by way of the switching point 51 and byway of the gate 64 a 1 signal is fed, the contents of the register 59 are erased. The register 59 is therefore always canceled, or the content thereof canceled, if also by way of the switching point 51 illustrated in FIG. 5 a reset signal is released to the inputs e of the counters 48x, 48y. In addition, the register 59 has its information content canceled if a 1 signal is fed thereto by way of the switching point 65 via the OR gate 64.
The AND gates 60 to 63 are only conductive if a 1 signal is fed thereto by way of the switching point 66.
The switching stage 35 can be operated in three different modes of operation. In the first mode of operation, a 0 signal is fed by way of the switching point 66 so that, on the one hand, the gates 60 to 63 are blocked and that, on the other hand, the loading of the register 59 is avoided. Therefore, 0 signals are released from the outputs of the gates 60 to 63 to the four stages of the adder 57 so that the syllable with the bits XI to XIV is released unchanged by way of the output of the adder 57 to the register 58 and is stored in the register 58. The syllable which is released fromthe register 58 is applied by way of the AND gates 36 to 39 to the decoder 40 and causes thecathode beam of the picture tube 19 to write individual character segments, as described above. The coordinates of the final points of three character segments all refer to the x and y coordinate axes of the graphic illustration in FIG. 4 and to the side of a rectangular picture which runs horizontally and vertically with respect thereto. If, therefore, a certain direction is fed by the bits XI to XV, this direction would be completely independent of the previously fed syllables, which possibly could refer to other directions.
In a second operational mode, a 0 signal or a 1 signal, respectively, is fed by way of the two switching points 65 or 66 so that the register 59 stores the syllables fed thereto and releases such syllables by way of the AND gates 60 to 63 to the adder 57. If, for example, the syllable 0001 is fed over the lines XI to XIV and is subjected to interim storage in the register 58, a character segment with the direction 0001 is written in a further sequence, on the one hand by using the control stage 28 and on the other hand the syllable 0001 is subjected to interim storage in the register 59.
With the next pulse, this syllable 0001 is directed from the outputs of the register 59 and is applied to the adder 57 by way of the AND gates 60 to 63 and is there added to the syllable 0001 which is fed by way of the inputs XI to XIV. Therefore, upon completion of addition, the syllable 0010 is released from the output of the adder 57, which as is shown in FIG. 4 characterizes a direction which is inclined by 45, when compared to the +x and +y axes. The syllable 0010 is applied from the register 58 to the decoder 40 by way of the AND gates 36 to 39 so that the cathode beam writes a character segment in the direction 0010. If the syllables 0001 is further directed by way of the lines XI to XIV,
the character segments with the directions 001 l, 0100, 0101, etc are written. The directions of these written character segments of the second operational mode therefore do not refer to the x and y axes, but to the direction of the previous character segment.
In a third operational mode, 0 signals are fed by way of both switching points 65 and 66 so that, on the one hand, the AND gates 60 to 63 are blocked, and, on the other hand, data stored in the register 59 are not changed. In this operational mode, at first, a character segment is'written whose direction is determined by the bits X1 to XIV. As long as the AND gates 60 to 63 are blocked, since a 0 signal is fed by way of the switching points 66, the switching stage 35 is operated as in the first operational mode. In this operational mode, for example, a rhombus (diamondshape) can be illustrated whose size are oriented in a certain predetermined manner with respect to the x and y coordinate directions. If, after thewriting of this rhombus, a 1 signal is fed by way of the switching point 66, the AND gates 60 to 63 are opened and the syllable is added to the syllable which is stored in the register 59, which information is fed by way of the lines XI to XIV. The adder 57 therefore releases a syllable which characterizes the direction of orientation of a character, which depends on the direction of the last character segment written of the rhombus. Thereafter, a O'signal can, for example, again be fed by way of the switching point 66, so that the AND gates 60 to 63 are blocked. The direction of the written character segment, however, remains stored in the register 59 Now again a rhombus can be written whose sides are oriented in the same manner as previously described with respect to the x and y coordinate directions. If, thereafter, the AND gates 60 to 63 are released and the syllable which is stored in the register 59 is added to the syllable having the bits XI to XIV, a direction is determined by the stored syllable in a register 58, which again depends on the syllable stored in the register 59 and on the syllable of the register having the bits XI to XIV.
The addition of the words in the adder 57 is similar to a rotation of the individual directions in a clockwise manner. This is also applicable if the two added ayllables result in a number which is larger than the binary number 1111 (larger than the decimal 16); If, for example, the syllables l and 0101 are added, the syllable 0001 will result.
The switching stage 35 which is illustrated in FIG. 6, in combination with the switching arrangement illustrated in FIG. 2, provides a saving of code words which are required for the selection of the characters to be illustrated. For the illustration of graphic characters, code words are required, in particular, with which the syllables 1100, 1111, 0000, 0001, 0010 and 0100 are fed into the adder 57. Therefore, only code words for seven different syllables and for seven corresponding directions are fed in. Nevertheless, it is possible to move the cathode beam in all directions illustrated in FIG. 4. This takes place by the application of the second mode of operation. This is based on the recognition that the series of lines to be illustrated from one character segment to the next character segment, in most cases, only changes slightly with respect to their direction. If, however, a change of direction by a larger angle, for example by an angle of is to be carried out, the syllable 0100 can first be stored in the register 59 starting from the +x. If, thereafter, the syllable 0100 is fed again via the lines XI to XIV, the syllable 1000 will be released after completion of addition according to the second operational mode by the adder 57 causing an angle change of 180. a
The signals which control the aforementioned operational modes are released by using the read only memory 23, which is illustrated in FIG. 2, and the decoder 32. Thereby, control data are set as addresses into the read only'memory 23 by means of the character data input device 11 illustrated in FIG. 1 and the word which is read out from the read only memory is applied to the inputs of the deecoder 32. The signals are directed to the switching points 65 and 66 by way of nonillustratedoutputs of the decoder 32 in a manner similar to that described in connection with the bits VIII, IX and X. The read only memory 23 and the decoder 32 together act like an assigner which is initially fed control data by way of the character data input device 1 1, which control data corresponds to one of the three mentioned operational modes and signals are released by outputs of the decoder 32 which thereafter adjust one of these operational modes.
Although I have described my invention by reference to a particular illustrative embodiment thereof, many changes and modifications of the invention may become apparent to those skilled in the art without departing from the spirit and .scope of the invention. 1 therefore intend to include within the patent warranted herein all such changes and modifications as may reasonably and properly be included within the scope of my contribution to the art.
1. An arrangement for the illustration of characters consisting of character segments, comprising: a read only memory storing character segment data; a character data input device connected to said read only memory and operable to address said read only memory for providing character segment data including control data'corresponding to the angular disposition of a character with respect to a reference; a data display device including a deflectable character writing element; digital/analog deflection apparatus connected between said read only memory and said data display device for controlling the deflection of said writing element in accordance with the data read from said read only memory; and means for controlling the operation of said data display device, said means comprising an adder having inputs connected to said read only memory, said adder receiving data at said inputs corresponding to the angular disposition of the character to be illustrated, said adder including other inputs and outputs, a register connected between said outputs of said adder and said other inputsofsaid adder, and gating means interposed between said register and said other inputs and operable to effect adding to determine the orientation of a character.
2. An arrangement according to claim 1, wherein said gating means includes means for receiving a signal to effect the adding process, and comprising a decoder for receiving the control data from said read only memory, said decoder connected to supply the control signal to said gating means.
3. An arrangement according to claim 2 wherein said register includes a control input connected to said decoder for receiving a control signal for causing said re gister to feed data to said gating means.
4. An arrangement according to claim 1, comprising a decoder connected between said adder and said digital/analog deflection apparatus, and counting means connected to said decoder and to said digital/analog deflection apparatus for determining the initial points of a character segment referred to a set of coordinate axes.
5. An arrangement according to claim 4, comprising a counting register for receivinng data from said read only memory corresponding to the length of a character segment and operated to decrease in count upon the illustration of each character segment until a predetermined count has been reached, and further gating means connected between said adder and said decoder and operating to an open condition as long as said counting register has not reached said predetermined count and closed in response to said predetermined count.
6. An arrangement according to claim 1, comprising a further register connected between the outputs of ter.
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|U.S. Classification||345/33, 715/741, 345/649|
|International Classification||G09G1/10, B41J2/435, G09G5/24, G06K15/12, G09G1/06|
|Oct 11, 1991||AS||Assignment|
Owner name: SIEMENS NIXDORF INFORMATIONSSYSTEME AG, GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:SIEMENS AKTIENGESELLSCHAFT A GERMAN CORP.;REEL/FRAME:005869/0374
Effective date: 19910916
|Oct 11, 1991||AS02||Assignment of assignor's interest|
Owner name: SIEMENS AKTIENGESELLSCHAFT A GERMAN CORP.
Effective date: 19910916
Owner name: SIEMENS NIXDORF INFORMATIONSSYSTEME AG PADERBORN,