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Publication numberUS3823350 A
Publication typeGrant
Publication dateJul 9, 1974
Filing dateSep 5, 1973
Priority dateSep 5, 1973
Publication numberUS 3823350 A, US 3823350A, US-A-3823350, US3823350 A, US3823350A
InventorsC Stoner
Original AssigneeAtomic Energy Commission
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Protective carrier for semiconductor chips
US 3823350 A
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Description  (OCR text may contain errors)

United States Patent 1191 Stoner 1111 3,823,350 1451 July 9, 1974 PROTECTIVE CARRIER FOR SEMICONDUCTOR CHIPS [75] Inventor: Charles L. Stoner, Albuquerque, N.

Mex.

[21] Appl. No.: 394,585

[52] US. Cl... 317/234 R, 174/5052, 174/52 S, 317/234 E, 317/234 G, 317/101, 339/174 3,409,861 ll/l968 Barnes et a1. 317/234 G 3,539,875 11/1970 Fong et a1 317/234 G 3,575,546 4/1971 Liautaud 317/234 H 3,786,317 l/1974 Thierfelder 317/234 R Primary Examiner-Andrew .1. James Attorney, Agent, or FirmJohn A. Horan; Dudley W. King; lgnaceo Resendez [5 7] ABSTRACT A protective carrier for microcircuit devices, e.g.,

[51] Int. Cl. "0113/00, H011 5/00 58 Field of Search 317/234, 3, 3.1, 4, 4.1, semlcenductor chlps, havlng leads descnbed, 317/1 100 339/174. 29/453. wherein a cover retams the ch1p such that its beam 174750 5 52 leads are in electrical contact with electrically conductive leads of a base so that the chips may be readily 56] References Cited handles and tested while so retained.

UNITED STATES PATENTS 3,192,307 6/1965 Lazar 317/234 E 4 Claims, 5 Drawing Figures 14 34 I- Q I 34b 370 l- .....":'t:i!w -I\ 37b s a 1 36b Z i A 12 CHIPS BACKGROUND OF INVENTION The invention relates to a novel apparatus for carrying such as Semiconductor beam lead chips.

Integrated or the like circuits or portions of circuits are often formed on a semiconductor chip. Such chips having metalstrips or beams (i.e., beam leads) forming electrically conductive paths on the chips pennit their joining to a circuit component by positioning the chip with a desired orientation on the circuit component such that the beam leads contact electrically conductive paths on the circuit component. The beam leads may then be, as is known in the art, pressure bonded to the conductive paths by applying heat and pressure to the beam lead only and not the chip material.

A plurality of semiconductor beam lead chips may be formed on a commonsemiconductor wafer; each chip being of sufficient size to accommodate desired cir cuitry and, in general, may be about 0.017 inch square in size with beam leads extending therefrom. After forming, the chips may be removed or separated from the wafer and are commonly mounted on a carrier plate by some adhesive means such as wax and in such a manner that the orientation of the chips may be random. Although this method of transporting the chips may be satisfactory for some purposes, it does require that the chips be removed from the carrier plate, the mounting adhesive be cleaned off or otherwise re- I .moved, and the orientation of the chip be determined before the chip can be positioned in a circuit or otherwise tested. These various steps increase the potential for damaging the chips and the amount of service time required to identify damaged chips.

It is often desired that the chips be testedin some manner to determine circuit continuity and operation. The testing method may require 100 percent testing such as that demanded where circuits must function in a fno failure" manner. A second method of testing may be to test a certain number of the total number of chips and, if these pass, assume that the rest are serviceable. Present testing apparatus are limited in the temperature ranges in which the tests may be performed and satisfactory testing may not be feasible for depressed and elevated temperatures.

SUMMARY OF INVENTION In view of the above, it is an object of this invention to, provide a carrier device for the semiconductor beam lead chips which eliminates the need for applying an adhesive base to the chip for carrying or transporting and thereby reduces potential for damaging the chips.

, tures of from about 55C to about +150C of the beam lead chip without removing same from the carrier. v V

It is a further object of this'invention to provide a carrier device that positions and retains the beam Iead' semiconductor chip in position for testing at temperature ranges of from about 55C to about +l50C and is not affected by these temperatures.

Various other objects and advantages will appear from the following description of the invention and the most novel features will be pointed out hereinafter in connection with the appended claims. It will be understood that various changes in thedetails and structure of the embodiment herein described in order to explain the nature of the invention may be made by those skilled in the art without departing from the principles and scope of this invention.

The invention comprises a chip carrying device having a support base which has an open ended passageway or aperture extending therethrough, electrically conductive lead on the carrier support base or substrate oriented such that a portion of each conductive lead extends near to one end of the open-ended passageway; a carrier cover having a recessed portion which extends over the open ended passageway of the carrier base, and walls adjacent the recessed portion for maintaining electrical contact by compression between the beam leads of a chip and the electrically conductive leads on the carrier substrate, together with means for aligning the carrier cover on the carrier substrate and means for retaining the carrier cover in a biased mode against the carrier substrate.

DESCRIPTION OF DRAWING DETAILED DESCRIPTION As shown in FIGS. 1, 3 and 4, the carrier device 10 includes a generally planar carrier base or substrate 11 having certain cutout portions, grooves, raised portions and the like including a generally centrally located open ended aperture or passageway 12 extending therethrough. A plurality of electrically conductive leads or paths 14 on substrate 11 extend to a location adjacent one end of the open ended passageway 12 on a surface of substrate 11 and arranged to correspond with the beam leads of chips to be carried and tested.

Leads 14 may be made integral with or otherwise disposed on substrate 11 surface through methods well known in the art. For example, a conductor substrate of nickel-chromium may be deposited by vacuum deposition or sputtering techniques directly on substrate 11 and a gold coating may be subsequently deposited on the nickel-chromium layer using the same techniques. The leads 14 may likewise be deposited upon a suitable film which may subsequently be bonded to the substrate 1 l. The number and arrangement of leads 14 will be dependent upon the number and orientation of the beam leads in the beam lead chip or device which is to be'carried or transported by carrier device 10.

As is shown in FIG. 3, the electrically conductive leads 14 may have a narrow portion 15 extending near the open ended passageway 12 and a wider portion 16 removed therefrom so as to facilitate making electrical contact onto leads l4 and testing of the chips transported by this device. The opposite end of open ended passageway 12 may have a flared orwidened cone shaped portion 17 which facilitates placement of a vacuum probe over aperture or passageway 12 to retain the chip in position as will be described hereinafter. The substrate 11 may also include a first aligning port 20, a second aligning port 22, and locking slots or apertures 24a and 24b which co-operate with the carrier cover as will be described hereinbelow to align the carrier cover with respect to the orientation of the electrical conductive leads and to lock the beam lead chip in a compressed mode while the cover also remains in compression. Thus when placed on the carrier base 11, the cover urges the beam leads into electrical contact with electrically conductive paths or leads l4.

Locking slots 24a and 24b may contain a sloping or faceted portion 25a, 25b which facilitates the entrance of locking tabs as will be described hereinbelow. The substrate 11 may also contain a plurality of protruding walls 26, recesses 27, ports 28, and the like which may be used to carry, align, or lock the substrate 11 in automatic carrying equipment or the like, as well as to facilitate stacking and to safeguard to prevent incorrect alignment in the test setup.

FIG. 2 illustrates a beam leaded chip 29 which may typically comprise a body 30 and a plurality of outwardly extending or protruding beam leads 31. Chip 29 may be retained in position'as described hereinbelow.

I means such as outwardly extending or protruding flanges or locking tabs 33a and 33b which project outwardly from downwardly extending wall portions 340,

34b along two sides or edges of cover 32 and cooperate with locking slots or apertures 24a, 24b to retain the carrier cover in position. One skilledin the art will readily recognize that although locking tabs are described, various other arrangements may serve the i same purpose. The locking tabs or flanges 33a and 33b may contain an outside sloping portion or wall 36a and 36b which cooperates with the sloping portions 25a and 25b respectively to guide the locking tabs into locking slots or apertures 24a and 24b; As the locking tabs slip past undercut portions 37a, 37 b, the tabs flare out or expand and lock or engage cover 32 with substrate 11.

Cover 32 may further contain an aligning pin 38 or "the like-which co-operates and is engageable with first alignment or registry of the cover with the beam lead device and substrate1l. Second aligning port 22 cooperates and is engageable with second aligning pin 40 which likewise contains a guide sloping or faceted portion 41 for facilitating entry of second aligning pin 40 into second aligning port 22. Aligning port 22 may be of a rectangular, oblong, or the like configuration although second aligning pin 40 may be of generally cylindrical or other suitable configuration.

It may be desirable that there be a slack or loose fit between second aligning pin 40 and second aligning port 22 in the direction indicated by arrow A in FIG. 3 and this slack may be maintained at from about 0.002 inch to about 0.004 inch per side. This facilitates snapping on of cover 32 onto carrier substrate 11 without dimensional or other problems arising from such as covers 32 being slightly out of shape. Further, this dimension permits cover 32 to be deformed or give" slightly when locking covers 32 into position. The dimension in the direction of arrow B, FIG. 3, may be maintained as for port 20, i.e., with a clearance of from 0 to about 0.001 inch. Carrier cover 32 may contain on its underside a protruding annular wall 45 which forms a chamber or recess 47 designed to accommodate the chip device without the chip touching any portion of cover 32. The wall 45 rests under compression or in a compressed mode upon the beam leads of the chip which is to be retained in place thereby insuring electrical contact between the beam leads 31 and electrically conductive paths 14.

FIG. 1 illustrates an assembled cover 32 and substrate 11 of this invention which is adapted to carry a four beam lead device. FIG. 4, which is a cross section along line 4-4 of FIG. 1, better illustrate how, in a preferred embodiment, the cover 32 co-operates with the carrier substrate 11 to maintain alignment and electrical contact between the beam leads of the chip and the electrical leads integrated into or formed on generally planar surface of substrate 11. The beam lead chip carrier substrate 11 may contain a pair of legs or downwardly extending walls 53 and 56. As shown, in FIG. 1, a wall 53 may include an elongated slot 55 which may be used in the same manner as downwardly extending walls 53 and 56, i.e., for automatic processing purposes such as alignment, movement, and retention as well as orientation in test fixtures.

The dimensions of the chips 29 and beam leads 31 may vary but typical dimensions are about 0.017 inch square for the body and about 0.004 inch long by about 0.002 inch wide for the beam leads 31. Semiconductor chip body 29 is disposed, located or positioned in recess 47 such as not to touch any portion of cover 32 other than contact between wall 45 and beam leads 31 as described hereinabove. Beam leads 31 are in contact with the narrow portion 15 of leads 14.

To place the beam lead chips on the carrier device 10, the chips may be disposed on a glass plate with the beam leads having the same orientation. The substrates 11 may be fed onto a belt or track in orderly arrangement by using such as a vibratory bowl feeder or tumbler. In operation, a first vacuum probe mounted on a swivable arm may be positioned over a beam lead device of known orientation and, using this vacuum probe, the beam lead device 29 may be picked up and positioned on a substrate 11 over open ended passageway 12 with appropriate beam leads 31 over and in contact with corresponding electrical leads 14 on substrate 11. Another vacuum probe of the type known in the art may be positioned at an opposite end of open ended passageway 12 over flared portion 117 to hold the semiconductor chip 29 in position while the first vacuum probe is removed and an additional vacuum probe positions the carrier cover 32 onto substrate 11 using aligning port 20 and aligning pin 38 together with second aligning port 22, and second aligning pin 40. Pressure is supplied by suitable means such as pneumatic means engaged to fingers disposed upon carrier cover 32 to insert protruding flanges or locking tabs 33a and 33b into their counterpart locking slots or locking apertures 24a and 24b. Locking tabs 33a and 33b are pushed through appropriate slots until the tab portion slips under undercut portions 37a, 37b of the slot or aperture 24a, 24b.

Mating of the tab with the undercut portion using appropriately dimensioned side walls 34a, 34b and locking tabs 33a, 33b proportionately sized to provide compression as illustrated in the drawings and described hereinabove retains a compressive bias upon covers 32 such that the wall portion 45 urges or otherwise maintains a compressive force against the beam leads 62 and narrow portion of electrical conductor lead 14 to effect electrical contact.

The carrier device as loaded may be safely transported without damage to the chip. lf desired to test prior to use, the device 29 may be tested by placing the carrier 10 in an appropriate test fixture and contacting the electrical conductors 14 with appropriate test apparatus. After testing, the carrier cover 32 is removed by inwardly compressing the protruding flanges or locking tabs 33a and 33b and applying an upward force upon cover 32 while retaining substrate 11 in a fixed position. The upward force may be provided by use of such as a vacuum probe. Another vacuum probe may be positioned before the cover removal over the open end of open ended passageway 12 to retain the chip in a fixed position. When desired, a further vacuum probe may be positioned over the chip to transport the chip to its desired position in an integrated circuit.

FIG. 5 illustrates, in a fragmentary cross sectional view, an alternate method that may be employed for aligning and locking of cover 32a with respect to a desired orientation of lead beam device 29 on substrate ll. As shown, locking split pin 70 is inserted into the port or opening formed by wall 74 forming a port a on substrate 11. The outer wall 76 of locking split pin 70 conforms to geometry of wall 74. Pin 70 contains a split, channel, or separated portion 72 which permits insertion of pin 70 into the port 20a formed by wall 74 on substrate 11 and subsequent positioning or locking upon expansion of pin 70 so as to effectively maintain compressive contact by wall 45 of beam lead 31 and electrical conductor 14 as well as alignment of the beam leads with respect to the electrical conductors or paths on substrate 11.

The beam lead chip carrier device described herein provides safe transportation of chips without having to apply any type of adhesive material which must be removed at a later time and at the same time providing an apparatus or device which lends itself to electronic testing of the chip. The material used for the carrier cover and the carrier substrate may be any suitable material which is sufficiently rigid and which may not be affected by the temperatures required for testing. Polysulfone material has been successfully used for this camera device 10. It may be desirable to use clear or transparent polysulfone which further facilitates knowing whether the carrier device is loaded or not. Devices made of polysulfone material have been tested at low temperatures such as about 55C and at elevated temperatures such as at about +150C without adverse effects.

The carrier chip combination described herein permits the bum-in test which is highly desirable for this type of semiconductor device. These tests have been made upon devices of this invention by applying full power to the chips continuously for a period of about 168 hours while the chip is at about 150C. Chips tested by this device have been successfully put into service and the carrier device of this invention has been reused without any harmful effects upon the substrate or cover.

Although a device suitable for use with a four beam lead semiconductor chip has been illustrated and described, one skilled in the art will know that the number of beam leads or electrical conductors is not limited to four but may be less or more depending upon the requirements. Thus devices which will accept beam lead semiconductor chips having eight, 12, 20, etc., beam leads have been used. The dimensions of the carrier may be enlarged to accept a higher number of leads. For example, a four or eight beam lead semiconductor chip carrier may measure approximately l inch long by three quarters of an inch wide whereas a carrier for a semiconductor chip having 20 beam leads may measure 2 inches long by 2 inches wide.

What is claimed is:

l. A carrier for a microcircuit chip having beam leads to facilitate handling and testing operations, comprising a substrate having a surface with a plurality of electrically conductive paths thereon and an aperture extending through the substrate from said surface, each of said paths having an end adjacent said aperture; a cover having a projection for contacting a portion of a said chip to maintain the chip in registry with said aperture and for retaining said chip beam leads in electrical contact with said substrate electrically conductive paths; means for aligning said cover with said substrate and said chip beam leads in registry with said substrate electrical paths; and interlocking means for releasably holding said cover and said substrate together and urging one toward the other.

2. The carrier of claim 1 wherein said aligning means comprises a plurality of protrusions carried by said cover and said substrate has ports for receiving and guiding said protrusions.

3. The carrier of claim 2 wherein said interlocking means comprises locking tab portions carried by said cover which coact with locking slots on said substrate to releasably hold said cover on said substrate.

4. The carrier of claim 3 wherein said projection on said cover comprises a protruding wall forming a recess for housing said chip.

l= =l l

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3988648 *Jul 18, 1975Oct 26, 1976The United States Of America As Represented By The United States Research And Development AdministrationProtective carrier for microcircuit devices
US4007479 *Mar 29, 1976Feb 8, 1977Honeywell Information Systems, Inc.Fixture for an integrated circuit chip
US4018491 *Mar 8, 1976Apr 19, 1977Rockwell International CorporationCarrier for devices
US4654693 *Aug 27, 1985Mar 31, 1987Matsushita Electric Industrial Co., Ltd.Electronic parts carrier with a chip-supporting top tape
US4706811 *Mar 3, 1986Nov 17, 1987General Motors CorporationSurface mount package for encapsulated tape automated bonding integrated circuit modules
US4734755 *Jun 7, 1985Mar 29, 1988Semikron Gesellschaft Fur GleichrichterbauAlternating load stable switchable semiconductor device
US5136366 *Nov 5, 1990Aug 4, 1992Motorola, Inc.Overmolded semiconductor package with anchoring means
US5407068 *Jan 13, 1993Apr 18, 1995Strong; Leslie G.Method and apparatus for transporting test boards
US6576989 *Nov 28, 2000Jun 10, 2003National Semiconductor CorporationLocking of mold compound to conductive substrate panels
DE3235995A1 *Sep 29, 1982Apr 28, 1983Molex IncAufnahmevorrichtung fuer einen integrierten schaltkreis
EP0103888A2 *Sep 20, 1983Mar 28, 1984Siemens AktiengesellschaftMethod and device to protect film-mounted integrated circuits (micropacks) against disturbance by electrostatic charges
WO1992008242A1 *Oct 21, 1991May 14, 1992Leslie G StrongMethod and apparatus for transporting sensitive electronic components
Classifications
U.S. Classification439/68, 257/735, 174/50.52, 174/551, 257/692, 257/702, 174/528, 174/535
International ClassificationH01L21/673, H01L21/67
Cooperative ClassificationH01L21/6735, H05K7/103
European ClassificationH05K7/10E3