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Publication numberUS3823551 A
Publication typeGrant
Publication dateJul 16, 1974
Filing dateMay 3, 1971
Priority dateMay 3, 1971
Also published asCA1000510A, CA1000510A1, DE2221681A1
Publication numberUS 3823551 A, US 3823551A, US-A-3823551, US3823551 A, US3823551A
InventorsRiehl R
Original AssigneeRiehl Electronics Corp
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Solid state electronic timepiece
US 3823551 A
Abstract
A wristwatch has a plurality of light emitting digital readout elements which are located along one end of the watch above the watchband. A hermetically sealed time capsule is enclosed within the watch case and includes an integrated circuit chip which divides the frequency output of a battery powered quartz crystal oscillator into a series of pulses which are counted and selectively interrogated to provide a series of electrical outputs corresponding to seconds, minutes, hours, days, months and years. The time capsule includes sealed control switches which are actuated by magnets slidably mounted on the case and which provide for selecting different outputs for visual display on the readout elements, corresponding to either hours and minutes, month and day or seconds. The electronic circuitry automatically compensates for twenty-eight, thirty and thirty-one day months as well as for leap years, and the readout may be selected for repetitive twelve hours or twenty-four hour display. When the twelve hour readout is selected, the AM/PM indicating light is energized when the hours and minutes readout is selected. A solar cell is positioned on the top surface of the watch case and functions to control the intensity of the readout elements according to the intensity of ambient light, as well as to recharge the batteries. The control switches also provide for setting the watch by either changing the minutes output while holding the seconds output at zero, or by changing the hours output without changing the minutes, seconds and days outputs, or by changing the days output without changing the second, minutes, hours and months outputs.
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lTrl tD [451 July 16, 1974 I SOLID STATE ELECTRONIC TIMEPIECE [75] Inventor: Roger W. Riehl, Troy, Ohio [73] Assignee: Riehl Electronics Corporation, Troy,

' Ohio [22] Filed: May 3, 1971 [211 Appl. No.: 139,468

[52] US. Cl 58/23 R, 58/23 BA, 58/50 R [51] Int. Cl. G04c 3/00, G046 19/30 [58] Field of Search 58/23 R, 23 A, 23 BA, 50 R, 58/85.5; 350/160 LC [56] I References Cited UNITED STATES PATENTS 3,129,557 3/1964 Fiechter 523/23 R X 3,333,410 8/1967 Barbella 58/23 R X 3,576,099 4/1971 Walton 58/23 R X 3,630,015 12/1971 Lehovec 58/50 3,643,418 2/1972 Polin 58/85.5 X

3,646,751 3/1972 Purland et a1 58/50 R X 3,654,440 4/1972 Hanchett 58/23 A X 3,664,116 5/1972 Emerson et al. 58/50 R 3,668,859 6/1972 Polin et a1 58/85.5 X

3,672,155 6/1972 Bergey et a1. 523/50 R OTHER PUBLICATIONS Hamilton Watch Company, Timely Topics, 5-6-1970, pages 1-4.

Primary Examiner-Edith Simmons .lackmon Attorney, Agent, or Firm-Jacox & Meckstroth [57] ABSTRACT A wristwatch has a plurality of light emitting digital readout elements which are located along one end of the watch above the watchband. A hermetically sealed time capsule is enclosed within the watch case and includes an integrated circuit chip which divides the frequency output of a battery powered quartz crystal oscillator into a series of pulses which are counted and selectively interrogated to provide a series of electrical outputs corresponding to seconds, minutes, hours, days, months and years. The time capsule includes sealed control switches which are actuated by magnets slidably mounted on the case and which provide for, selecting different outputs for visual display on the readout elements, corresponding to either hours and minutes, month and day or seconds. The electronic circuitry automatically compensates for twenty-eight, thirty and thirty-one day months as well as for leap years, and the readout may be selected for repetitive twelve hours or twenty-four hour display. When the twelve hour readout is selected, the AM/PM indicating light is energized when the hours and minutes readout is selected. A solar cell is positioned on the top surface of the watch case and functions to control the intensity of the readout elements according to the intensity of ambient light, as well as to recharge the batteries. The control switches also provide for setting the watch by either changing the minutes output while holding the seconds output at zero, or by changing the hours output without changing the minutes, seconds and days outputs, or by changing the days output without changing the second, minutes, hours and months outputs.

12 Claims, 28 Drawing Figures PATENIEU 1 6 1974 MET 01F 14 INVENTOR ROGER w. RIEHL ar z HZMZ! IATTORNE'YS PATENTED 1 61974 3. 823 .551

I sum 02 or 14 FIG-5 I9 FIG-6 PATENTEDJUL 1 s 1914 FIG-l5 VOLTAGE SENSOR PATENIEDM 1 61914 sum 12 or 14 FIG-17B alb MIN. TENS MIN. UNITS FIG-17 A BACKGROUND OF THE INVENTION There have been many proposals for solid state electronic Wristwatches and clocks which employ bistable electronic counters to display the time. Commonly, the indicating or display means are located on the top of a wristwatch since this is the location which is conventional for the dial face and hand pointers ofa mechanical watch. For example, in US. Pat. Nos. 3,427,797; 3,540,209; 3,258,906; 3,466,498; 3,509,715; 3,276,200; 3,485,033 and 3,505,804, continuous reference is made to the watch face as a synonym for the top of the watch. US. Pat. No. 3,194,003 shows a similar form of electronic timepiece.

Various means have also been suggested for setting the time on an electronic clock, but these means have the disadvantage that they mimic th action of the mechanical watch by continuing the time readout during setting. This continuing readout is difficult to set at exact synchronization with an actual time signal. That is, since time is passing while the adjustment is taking place. the operator must watch his readout and at the same time observe another clock whose seconds indication is in motion or listen for a time signal and hope to advance his readout to within a few seconds of the actual time. after the signal. U.S. Pat. Nos. 3,456,152 and 3,l95,0ll relate to electronic timepieces having this form of time setting.

Such time setting means also carry from the lower order counters into the higher order counters. This is not objectionable when carrying from minutes to hours, however, it would be annoying to have the trial and error pulses feed into the days and months and years counters of a calendar watch. This would require further cycling to bring the counters back into proper place after adjusting the lower order counters for time zone changes or timing correction. While calendar circuitry has been previously considered, most suggestions leave the resetting of the day at the first of each month up to the operator. Months counters, and especially one with leap year provisions, have been deemed impractical due to the difficulties encountered in displaying and adjustingthe counters. It has also been assumed that the calendar circuitry requires additional readouts and associated additional wiring interconnections.

In other proposals of electronic Wristwatches, it has been assumed that a continuous display is required. When using light emitting elements, however, a continuous display requires a prohibitive power supply, in view of the efficiency of known light producing elements and the size ofa battery required within the present state of the art. Furthermore, separate electronic components. such as resistors and capacitors for noise and signal control. have been found necessary in previous work. In addition, separate connections from each readout element to the electronics circuit required as many as 33 connections for a four digit seven segment display and decimal points.

SUMMARY OF THE INVENTION The present invention is directed to an electronic timepiece which addresses all of the above problems and provides means for eliminating or minimizing them. In accordance with a preferred embodiment of the invention as described herein, many carefully selected methods and components are disclosed for achieving the functions which the invention performs. in general, the timepiece comprises integrated circuits which sustain and divide the oscillations from a quartz crystal to produce a one pulse per second timing source and which also count seconds, minutes, hours, days, months and years. The circuits then multiplex, select and distribute coded outputs from the counters to a decoder matrix which translates them into seven segment numeric readouts consisting of light emitting diodes in a four digit array which is time shared one digit at a time.

A two cell nickel-cadmium battery is connected to a solar cell array which maintains its charge from ambient light as a power source, and magnetically actuated reed switches provide for selecting readout functions and adjust timing. That is, three switches provide for selecting the time, in hours and minutes or in minutes and seconds and also for selecting the date, in day of month and month number for display on the readout. When neither time nor date is being selected, the readout is turned off to conserve power. Three other control switches provide for adjusting for time zones and for setting to the correct time. They advance the minutes, hours and day counters one step for each push of the switch.

The hour and day switches will recycle their respective counters repeatedly without carrying into the day or month counters to aid in preventing erroneous advances of the month and year counters. The minute advance switch advances the minutes counter one count for each actuation of the switch, and when the switch remains closed, the seconds counter remains at zero so that it can be released in synchronization with a time signal which occurs at an even minute. The time readout may be energized while the minutes advance switch is held closed so that the operator may observe the time signal indication which is being awaited.

The readout is mounted at the edge of the watch perpendicular'to the top surface of the watch and above the point where the wristband is normally attached so that the display is in a natural wrist position when being viewed and so that ambient light from above will be partially shaded to prevent washout of the light emitting diodes. The edge location of the readout also provides for the maximum area on the top of the watch for receiving solar cells or to permit a case construction with a more solid top wall. The readout area is covered with a red color filter and circular polarizing material to maximize constrast ratio by minimizing reflected light.

The entire inside assembly is sealed by the case or by means of potting in a transparent plastic material to fonn a time capsule which is impervious to moisture and dirt. The only connections to the outside of the capsule are the light inputs and outputs and the magnetic fields for actuating the reed switches. The hours counter is arranged so that it can be simply altered from counting in twelve hour intervals to counting in twenty-four hour intervals, by connecting a single wire on the electronics enclosure to the positive or negative terminal of the power supply. When the watch is operated in a twelve hour cycle, a small indicating light is illuminated during the time display in the PM hours so that in adjusting for time zones, the operator will have a midnight reference to prevent date change at noon.

Connections are brought out of the electronics package to provide for sensing and setting leap year in the years counter. These leads are accessible to the technician only. When the date is displayed, the light used for PM indication is also used to indicate even years, and another light is provided to indicate that the even year is a leap year, thus indicating in binary form, the portion of the four year cycle that the calendar is in.

BRIEF DESCRIPTION OF FIGURES FIG. 1 is a perspective view of a wristwatch constructed in accordance with the invention and showing a portion of a wristband attached.

FIG. 2 is a section taken generally on line 2-2 of FIG. I and showing the relationship of the mechanical components.

FIGS. 3-8 illustrate the left, right, rear, front, top and bottom views respectively of the wristwatch shown in FIGS. I and 2.

FIG. 9 is a block diagram of the entire electronics for the wristwatch. and which is sectioned by dashed lines into areas that are covered in more detail by figures referred to thereon;

FIGS. 10-18 show the detailed electronic construction of the sections shown in the block diagram of FIG.

FIG. 19 shows the dynamic digital frequency divider circuit which is used in the counter dividers of FIGS. 11 and I6; and

FIG. 20 is a circuit diagram of a synchronized astable divider.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the drawings which illustrate the preferred embodiment of the invention, and particularly to FIGS. I and 2, the entire inner components of the watch 10, are cast into a clear plastic block and then inserted into the wrist-watch case 12 from the bottom side. There may be a secondary window 13 covering a silicon solar cell 15 at the top of the case, or the plastic encapsulation of the mechanism. may serve as this surface. Pairs of magnetically actuated reed switches 17 or Hall effect magneto-resistors are embedtied in the plastic package and are activated by magnetic slide control buttons 18, 19 and 20 affixed in a track at the edges and rear edges of the wristwatch. Each slide button is centered by spring return and selectively activates one of the two magnetic switches by sliding forward or backward along the side of the case.

Nickel-cadmium sealed cells and 26 are located at the bottom of the case 12 adjacent an enclosure for a quartz crystal 27. The electronic package 30 consist of a hermetically sealed ceramic block which contains the integrated circuits and driver transistors. The block also serves as a strong mounting surface for the silicon solar cells 15. The leads out the forward end of the package are attached to a circuit board 32 which holds the readout elements or modules 35-38. The leads out the rear of the package 30 connect to the power supply and the corresponding reed switches I7. The wristwatch case has a bottom cover 39 or may be opened to reduce the overall thickness of the watch by permitting the lower surface of the plastic block to form the bottom surface of the wristwatch.

Referring to FTG. 9, the readout modules 35-38 consist of four seven bar plus decimal point modules. These can be on a hybrid array substrate or may be purchased individually packaged. The colon indication 40 is accomplished by mounting the third digit from the left in an upside down position so that its decimal point forms the upper dot ofthe colon. and the decimal point of the preceding digit forms the lower dot of the colon.

The module 35 (HG. 6) is mounted upside down so that its decimal point 41 is located in the upper lefthand corner of the display. As will be explained later, this decimal point 4] and the decimal point 42 located at the right of the fourth module 38, are used to give a binary indication of the position of the years counter whenever the date is being displayed. The decimal point 41 on the fourth digit on the left 35 is also used to indicate the PM hours whenever the hours counter is set in the twelve hour counting mode and the time is being displayed.

The readout modules 35-38 consist of light emitting diodes which provide a matrix isolation which permits a multiplexing or time shared usage of the decoder which drives them so that the digits to be displayed are synchronously selected and positioned in the readout in a repetitive manner to produce the effect of continuous display. If the display were to consist of incandescent elements, separate diodes would have to be placed in series with them or the elements could be individually driven instead of commonly driven as shown in FIG. 9.

In FIG. 16, a quartz crystal 27 establishes the time base for the entire timepiece. In the preferred embodiment. this crystal is cut to oscillate at a frequency of 32.768 kHz. and connected in an oscillator circuit 28, the output of which is connected to a binary frequency divider 45. This divider has several outputs. the highest of which is 2,048 Hz. The divider also has an output at L024, 512, 256, I28 and 64 Hz. The exact frequency of quartz crystal 27 is relatively unimportant as long as it is an integral multiple of the 2,048 Hz. signal required.

These output signals are used to develop strobing and timing signals as shown and described with reference to FIGS. 10 and 15. The 64 Hz. output signal is also divided by a plurality of counters which provide BCD (Binary Coded Decimal) output signals which represent time and date.

The frequency division down from crystal or tuning fork frequency to the 64 Hz. level is provided for by dynamic digital flip-flops 45 described in detail in FIG 19. These flip-flops utilize a single phase clock provided by the output lines of the preceding stage and produce a single phase output on the Q and G outputs which is divided by two. These flip-flops utilize ten integrated transistors ofthe P and N field effect type. Their advantage lies in the fact that commonly used digital dividers employ sixteen transistors in order that they may be stable in both of their possible output states.

The normal divided by two arrangement is shown in FIG. I7A. It consists of two storage sections coupled one to the other in series by two transmission gates. The clocking phase of the transmission gates is arranged such that one section is storing while the other section is changing by feedback in an alternating manner such that for each clock alternation, the output stage changes one time thereby dividing by two. The conditions proceed statically one after the other as the clock transfers from one state to the other and there is no time constant requirement. This circuit requires sixteen transistors no matter how it is used.

The dynamic digital divider of FIG. 19A requires only ten transistors and works in the following manner: Inverters 50 and 51 are connected in series and their outputs from the O and Q outputs respectively. Inverter 52 adjusts to a state determined by the Q output through transmission gate 53 when clock is low. Transmission gate 54 is open when the clock is low thereby permitting the input to Inverter 50 to float at a static voltage roughly equal to what it was the last time that transmission gate 54 was closed connecting it to the output of Inverter 52.

The gate capacitance and the extremely high input impedance of the insulated gate field effect transistors used, permit this voltage to remain stable for a period determined by the open impedance of transmission gate 54. The opening of transmission gate 54 does not influence this voltage since the changing clock is coupled to it with roughly the same capacitance from each phase thereby producing a net zero influence at the transition point of the wave form. When the clock rises, transmission gate 54 closes the circuit from Inverter 52 output to Inverter 50 Input, and transmission gate 53 opens the circuit from Inverter 51 Output to Inverter 52 Input. The input to Inverter 52 floats at the potential last coupled to it from the 0 Output Terminal. Transmission gate 53 opens fully before the new reverse charge from Inverter 52 Output can be fed to Inverter 50 input and ripple through to the 0 terminal clue to the transition delays of Inverters 50 and 51.

Therefore, the state of Q and 0 reverse at the rise of the clock since the output of Inverter 52 is the reverse of the former state of Q and is now fed to the input of Inverter 50 which reinverts the O to the state formerly held by Q whereupon Inverter 51 reverses the state of Q at a time slightly too late to influence the floating potential at the input to Inverter 52. When the clock falls,

the state of Q and Q is preserved by the floating potential at the input of Inverter 50 because transmission gate 54 opens, a new state is switched to the input of Inverter 52 by transmission gate 53 which couples the new state of the 0 terminal thereto. The output of Inverter 52 at this time reverses a little too late to influence the input to Inverter 50. Thus the output reverses once for each time the clock rises or, in other words, completes a whole cycle of two discrete states for each two such changes of the input clock thereby dividing by two.

The semi-static version of this flip-flop shown in FIG. 19B is essentially the same except that an additional transmission gate 55 is installed from Q to the input of the Q Inverter thereby permitting any of the two states at the output to be permanently preserved when the clock is low. This arrangement utilizes two additional transistors for a total of twelve and still, in many applications. will serve as well as the sixteen transistor type previously required.

If the circuit in either flip-flop is broken at terminal 57, access to the device through the 5 input shown will permit operation as a data type flip-flop wherein the state of the l5 input is captured by the output of the unit at the rise of the clock and changes the D input other than at the transition moment of the clock have no eflect at the output.

These two flip-flop arrangements require much less area for the active devices on the chip of an integrated circuit and, therefore, result in a cost savings in high volume production. It also has several other advantages. One is that the input clock signal must drive only half as many transmission gates as in the sixteen transistor flip-flop in the case of the basic divide-hy-two stage thereby reducing capacitive loading of the incoming signal which, in turn, reduces the power dissipation required by the driving device. This has an advantage in higher frequency applications in power savings which is especially advantageous in a wristwatch permitting the use of higher quartz crystal frequencies in the oscillator at approximately the same power dissipation or reducing the power required for a given input frequency.

There is less power consumed in the transition of the inverters since there are only three of them instead of four, so the dissipation due to transition is reduced by a factor of 25 percent. This flip-flop will also work better the higher the input frequency is, due to load consideration factors and the inherent better float potential preservation on short duty cycles of the input to Inverters 50 and 52. This design should also provide for a higher total possible frequency of operation for a string of dividers at a given power supply voltage in that the first stage minimum operating speed is limited by the output capacitance that it must drive. With this configuration, the input capacity of the succeeding stage is less.

For slower operating frequencies, capacitance in the fonn of a larger gate electrode or metalization area over the substrate oxide pad, can be added at the inputs to Inverters 50 and 52 or a simpler flip-flop requiring only six transistors can be implemented using an integrated capacitor as shown in FIG. 19C. In this unit, the state of Inverter 60 output is fed to Capacitor C l by transmission gate 61 when the clock is low. Transmission gate 62 is an open circuit permitting the input to Inverter 60 to store a floating potential which determines the Q output. When the clock rises, transmission gate 62 transfers the reversed phase to Inverter 60 input from the voltage stored on Capacitor Cl while transmission gate 61 opens to pennit the voltage on C1 and the input of Inverter 60 to float together. With this circuit, Capacitor C1 must be significantly larger in capacity than the input capacitance of Inverter 60 or other devices attached to the 0 output when summed.

An additional Inverter may be attached to the Q terminal to provide the 0 function in cases where the ratio of capacitance of Capacitor C1 to the Q load and the input of Inverter 60 is going to dictate an excessively large value for CI. Essentially Capacitor Cl must be large enough so that when transmission gate 62 closes,

' the stored charge on the input of Inverter 60 does not become a major determining factor of the new voltage. If Capacitor Cl were equal to the gate input capacitance of Inverter 60, then the new voltage would be one-half of the supply voltage when transmission gate 62 closes. Therefore. C 1 should be on the order of four or five times the gate input capacitance of Inverter 60 so that the voltage will not be at an indeterminate point of the transfer characteristic of Inverter 60.

In FIG. 11, six dynamic divider stages 75 reduce this 64 Hz. signal to one pulse per second. This one pulse per second signal is fed into a seven-stage binary counter 77 which, beginning at the all zero state, counts until a binary ten is detected at NAND Gate 78. This trips NAND Gate 80 and enables NAND Gate 81 which admits high speed 1,024 Hz. pulses into the input of the binary counter 77. This quickly advances the counter 77 through binary states Nos. 10 and 11 whereupon NAND Gate 83 detects binary l2 and by enablement through NAND Gate 80 into NAND Gate 81 permits the continuation of these fast pulses moving the birllaiiys counter quickly through binary states l2, l3, 14 an At the next pulse, the binary state of the first four stages is zero and the binary state of the fifth stage is one, yielding a BCD (Binary Coded Decimal) 10 output. NAND Gates 78 and 83 repeatedly exclude States 10-15 by quickly counting through them at the 1,024 Hz; rate. This amounts to six pulses at 1,024 Hz., which therefore takes somewhat less than six milliseconds. This six milliseconds is significantly shorter than one second, therefore, it does not overlap the output pulse from the divider section 75 which caused the seven stage binary counter 77 to advance to the first of the undesired states (10) when it fell thereby permitting NAND Gate 85 to accept pulses from another source without interference for k second.

The quick advancing through the undesired states of this binary counter is also too fast to be noticed on the display and amounts to a very insigificant fraction of the totally displayed numeral. This procedure continues until binary 6 is detected by NAND Gate 86 in the last three stages of the binary counter. This enables NAND Gate 80 which, in turn, enables NAND Gate 81 to admit l,024 Hz. pulses to the input of the counter. Since NAND Gate 86 detects both the 6 and binary 7 state of the last three stages it will continue to admit pulses until these three stages are returned to binary zero which, as it turns out, is coincident with the first four stages returning to binary zero due to the natural counting sequence of a binary counter.

In this way the units and tens binary coded decimal (BCD) outputs are generated for the seconds display of the wristwatch. These outputs are fed into the multiplexer section of FIG. 10 for distribution to the seven bar decoder and display elements 35-38. NAND Gate 86 also produces a negative going pulse on line 89 which begins at the time of the first undesired state in the last three stages and ends when the counter returns to zero. This is used as a pulse to advance the minutes counter.

In a hybrid version of the wristwatch using individual gate packages this may be an advantage to have a negative going output carry pulse. The actual carry connection in an integrated electronics package using a single monolithic array would utilize the Q and 6 outputs of the seventh stage of counter 77.

This particular circuitry of stepping the counter through the undesired binary states can be implemented by using relay logic on a complementary symmetry metal oxide semi-conductor monolithic integrated circuit using fewer transistors than the normal feed-back gating system would permit for synchronous counters or counters that count in the actual BCD mode or scale while simultaneously providing a pulse type carry output when this is necessary or desired.

NOR Gate 90 detects whenever the counter is off the zero state or, in other words, when there is a logic one bit coming out of any of the stages of the counter. During any time, except the zero state, the reset switch 19A (FIG. 11) will enable NAND Gate 93 which, in turn, activates NAND Gate and enables NAND Gate 81 to admit 1,024 Hz. pulses into the counter while the dynamic stages preceding are held at zero by a reset line also connected to this reset switch.

The switch 19A (FIG. 11) serves a dual purpose in that each time it is actuated it will advance the minutes counter one whole minute and can be used for making course corrections of the time indication. Normally less than a minute error will be found due to the high accuracy of the quartz crystal and tuning fork type oscillators. Therefore, one push of the button will advance the watch to the nearest whole minute and the operator may wait for the time signal to catch up with the new setting that he has just accomplished.

Setting the watch to a time several minutes before th actual indicated time, as far as the minutes and seconds counter is concerned, can be accomplished by repeatedly actuating this same switch so as to advance the minutes counter completely around through one hour until it reads the desired minutes indication.

Activating switch 19A also makes the counter advance through the remainder of its states until the zero state is reached whereupon the admittance of the 1,024 Hz. pulses is discontinued and thereby holding the seconds count at zero and completing one carry pulse on line 89 to the minutes counter thereby advancing it to the next minute indication. This switch also holds the dynamic stages at the zero count thereby reducing possible error in the release timing of this switch to k cycle of the 64 Hz. signal or l/ 128 second. The purpose of this switch is for synchronizing the wristwatch with a time signal so that upon release of the switch the wristwatch begins to count seconds from a starting point of zero.

In the seconds counter 77, the primary purpose of this action is to provide a system which takes into account the switch bounces that may occur when the reset switch is closed. It will be noted by examination that the highest seconds indication would be 59 at the time that the switch might be closed. If the switch bounces and provides multiple pulses to NAND Gate 93, the counter will be stepped by these multiple pulses when the fast pulsed 1,024 Hz. source is high at the input to NAND Gate 81. The fact that it takes the counter a discrete number of pulses to scan back to the zero state, automatically allows for the timing required to assure that all switch bouncing has subsided before the end desired state is reached.

It has been shown by experimental work that the actual number of bounces to be expected from a magnetic reed switch of minature variety varies between four and sixteen. Even if all of these sixteen bounches occurred during such a short time as the 1,024 Hz. signal is high, the counter could not be advanced more than sixteen discrete steps. Therefore, it will not overshoot the zero state since from the highest BCD output of 59 it takes at least 32 individual pulses to return the seven stage binary counter to zero. Therefore a digital switch bounce filter is accomplished without using external timing components such as resistors and capacitors and without the use of a digital clocked switch bounce filter which is employed elsewhere in this wristwatch,

Thus the complete switching system can be integrated as a purely active device circuit. Another method of accomplishing the same thing would be to install well known feed-back loops to make the counter count in the desired scale and to have the switch simply reset both the dynamic and static stages of the seconds section while activating a one-shot or monostable multivibrator which could be ORed in with the carry pulse output line. This would require some sort of timing and resistance capacitance network and implemented digitally requires at least two stages of binary division, one of which would have to be a clocked switch bounce filter so that the output would go through both an state and an Off state before the catch was released so that the minutes counter would actually advance to the next whole minute and sit in that state in such a manner that the time display button of the wristwatch could be activated so that the time being held by this reset switch could be observed by the operator before he releases the switch.

Another advantage of this step around feed-back system wherein a faster pulse is admitted to quickly step around the undesired states is that the binary stages of division can be integrated in standard form with only their 0 outputs brought out, eliminating the need for metalization connection to either the 6, the data input or the reset terminals of the binary counter stages. This should result in a savings of integrated circuit chip space which will be important if employed on a systemwide basis especially as it reduces the metalization area requirements.

P16. 178 shows the minutes counter section 100 of this wristwatch which employs seven standard static type flip-flops, such as shown in FIG. 17A, connected in cascade, to form a seven stage binary counter and undesired states are detected-and quickly skipped over in a manner exactly like that of the seconds counter. In this case it is desirable that a single pulse carry be generated at the point of reset from 59 to zero minutes so that the carry pulse into the hours counter 120 will not hold the input of the hours counter in a state which to install exclusive OR Gate so that the input to the first counting stage of the hours counter would he phase inverted by each manual advance input pulse regardless of the state of the carry pulse or carry signal from the minutes counter. However, this would add to the complexity required to implement the function both directly and indirectly by complicating the further functional requirement that the manual hours advance pulses not advance the day counter in going through midnight.

FIG. 12 shows the hours counter 120, of the wrist- 'watch. The first counting stage 121 of this hours counter is allowed to alternate its states continuously without subjugation to the feed-back pulses. NAND Gates 122 and 123 detect the binary 10, 11, 12, 13, 14 and 15 states in counter 12S and enable the 1,024 Hz. signal to quickly step the counter around to zero whenever its first four stages are in a state higher than a BCD 9. The first counting stage 121, which controls the A" line of the hours units indicator, is triggered to a new state at the end of the input carry pulses so that when A is high the input carry pulse is carried forward to the remaining five stages by NAND Gate 124 and at the end of the input carry pulse, the A line falls to zero thus obeying proper sequence for binary outputs A, B, C and D from counters 121 and 125.

This carrying system permits the A line to be high or low when an undesired state is detected by the feedback system. This is required since this counter of hoursis arranged to count in either a twelve or twentyfour hour mode as selected by a single exterior control line 128 which is connected to a plus for the twelve hour mode and a minus for the twenty-four mode and each mode reaches its first undesired state at a different state of counter 121. In other words, the twenty-four mode has a first undesired state which is a BCD 24 or an even number and the twelve mode has its first undesired state at BCD 13 which is an odd number. Therefore, line A of counter 121 is high for one and low for the other so for the 1,024 Hz. signal to occur, the carry signal from the A line must be of a pulse nature so as to be out of the way.

In this arrangement shown a latch consisting of NAND Gates 126 and 127 is used to turn on the 1,024 Hz. signal. It is tripped by the first undesired state as determined by the mode select switch and is shut back Off when the count reaches zero as defined by the same switch. In the case of the twelve hour count the latch is tripped by the main input carry pulse from the minutes counter when the output is a BCD 12 on lines A, B, C, D and E of counters 121 and 125. Line E controls the ones code of the BCD hours output for the tens of hours display. The twos output of the BCD code for the tens of hours display is held negative by NOR Gate No. 2 in the twelve counting mode. The latch is reset by NAND Gate 129 when line E falls to zero. Whenever line A of counter 121 is in the high state, during this procedure, reset is to a BCD 1 instead of zero. Line F of counter is fed to the AM/PM indicator 41 when the time is being displayed so that the operator knows whether he is at an AM or PM hour when he is adjusting his watch for a time zone so that he will not leave it adjusted at such a point that the date counter will transfer at noon instead of midnight.

1n the twenty-four hour mode a BCD 23 is detected and pulsed into the latch at the next main input carry pulse and the 1,024 Hz. signal steps the counter until the F" line falls. This is synonymous with the zero state of the counter and provides the zero hour indication for midnight in a twenty-four hour clock system. The AM/PM indicator 41 is disabled in the twenty-four hour mode. NOR Gate 131 generates a date carry pulse on line 132 whenever the counter passes midnight due to an input pulse from the minutes counter. The F line insures that this will occur in the PM hours in the twelve hour count mode. The line connected to the minutes input gate 135 insures that it will not occur as the result of a manual advance input pulse.

Gate 136 illuminates the Z indicator decimal point 42 when the date is displayed and the years counter is at an even state in the four-year leap year cycle of the

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Classifications
U.S. Classification368/66, 968/961, 968/450, 327/437, 968/960, 368/29, 968/959, 968/958, 968/914, 968/504, 968/505, 368/22, D10/39
International ClassificationG04C10/04, G04C3/00, G04G5/00, G04G9/00, G04C10/00, G04C10/02, G04G5/04, G04G9/10
Cooperative ClassificationG04C10/04, G04G5/04, G04C10/02, G04C3/005, G04G9/107, G04G9/102, G04G9/10, G04G9/105
European ClassificationG04G9/10, G04G9/10D, G04G5/04, G04C3/00K4, G04G9/10C, G04C10/04, G04G9/10B, G04C10/02
Legal Events
DateCodeEventDescription
Nov 24, 1986AS06Security interest
Owner name: MICROTRONICS CORP. A CORP. OF NJ
Effective date: 19861120
Owner name: SANWA BUSINESS CREDIT CORPORATION, ONE SOUTH WACKE
Nov 24, 1986ASAssignment
Owner name: SANWA BUSINESS CREDIT CORPORATION, ONE SOUTH WACKE
Free format text: SECURITY INTEREST;ASSIGNOR:RAGEN CORPORATION, A CORP. OF NJ;REEL/FRAME:004647/0319
Effective date: 19861120
Free format text: SECURITY INTEREST;ASSIGNOR:MICROTRONICS CORP. A CORP. OF NJ;REEL/FRAME:004647/0347
Free format text: SECURITY INTEREST;ASSIGNOR:RAGEN DATA SYSTEMS, INC. A CORP. OF NY;REEL/FRAME:004647/0333