US 3824558 A
Apparatus for use in a mill having a plurality of operating machines, wherein the apparatus includes sensing means for detecting machine malfunctions, memory means for determining the order in which repairs should be made to malfunctioning machines, and a repair operator's carriage having means for moving it from one malfunctioning machine to another in the predetermined order and along the shortest route.
Claims available in
Description (OCR text may contain errors)
United States Patent [1 1 on 3,824,558 Koshiba July 16, 1974 AUTOMATIC APPARATUS FOR 3,559,131 1/1971 Carlock et al. 340/1725 SEQUENCING REPAIR WORK IN eem a OPTIMUM ORDER 0N MALFUNCTIONS OF 3,588,832 6/]97] Duncan 340/1725 GROUPED OPERATING MACHINES  inventor: Hefii Koshiba, l4-l7, lzuminomachi 6-ch0me, Kanazawa Japan Primary Examiner-Paul J. Henon Assistant Examiner-Melvin B. Chapnick  filed; June I972 Attorney, Agent, or FirmRobert E. Burns; Emman [2|] Appl. NO,1 267,013 uel J. Lobato; Bruce L. Adams Related US. Application Data  Continuation-impart of Ser. No. 73,694, Sept. 2],
I970, abandoned.  ABSTRACT Foreign Application Priority Data Apparatus for use in a mill having a plurality of oper- Sept. 19, l969 Japan 44-74840 ating machines, wherein the apparatus includes sensing means for detecting machine malfunctions, mem-  U.S. Cl. 340/1725 ory means for determining the order in which repairs [5| Int. Cl. G06f 11/00 should be made to malfunctioning machines, and a re- Field of Search-m 340/1725. 6.l C pair operators carriage having means for moving it from one malfunctioning machine to another in the  References Cited predetermined order and along the shortest route.
UNITED STATES PATENTS 3,173,335 3/1965 Bateman H 340/1725 X 7 Claims, 13 Drawing Figures l g LOOM LOOM LOOM 0 CAR 0 [9 0 49 0 LOOM I f 19 0 O O O O 9 LOOM LOOM I O l 19 0 DE TEC TOR SWITCH Pmminmw 3.824.558
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START 806 ACCUMULATOR Y J DISPLAY 1 cobi r ien 35m 808 MEMORY MEMORY 8 omvme 1L MOTOR E CRYFT 8H 830 GATE 3 Q L MOTOR 3|6A 802 8'4 DRIVE 8|8/- & 828
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812 i 7' unraoargg MOTOR 330A 803 294833 -825 CONTROL 822 MEMORY DETECTOR AUTOMATIC APPARATUS FOR SEQUENCING REPAIR WORK IN OPTIMUM ORDER ON MALFUNCTIONS OF GROUPED OPERATING MACHINES RELATED APPLICATION This application is a continuation-in-part application of our copending application Ser. No. 73,694 filed Sept. 21, I970, now abandoned.
BACKGROUND OF THE DISCLOSURE The present invention relates to automatic apparatus for moving a carriage for transporting a repair operator between a plurality of machines. The apparatus senses malfunctions of the machines, determines the priority in which repairs must be made, and advances'the carriage to the various malfunctioning machines according to the priority sequence and along the shortest route.
When manufacturing work such as a weaving operation is performed by a plurality of operating machines installed in a mill, cases are encountered wherein two or more machines stop simultaneously due to such causes as consumption of the material, malfunction of some machine parts, completion of an operation cycle requiring the machine to be reset, or accidental breakage of the material during processing. Furthermore, it may be necessary in some instances to perform service procedures even when the machines themselves do not stop. Such servicing and repair of the machines must be performed as quickly as possible so as to maintain the operational efficiency of the machines. Usually, this repair work is performed by operators who watch the op erational condition of the machines in the mill, and eliminate any malfunctions which are recognized. Some of the malfunctions can be repaired very easily and within a short time, while other malfunctions require complicated repair and a long down-time for that machine. Therefore, when multiple malfunctions occur simultaneously, and at different machines, it is necessary for the operator to decide the sequence in which the machines must be serviced. In the case ofa weaving mill, for example, wherein thread breakage may occur in one of a plurality of weaving looms, it is necessary for the weaver to rush to that loom to mend the thread. When the abovedescribed malfunction takes place at several looms simultaneously, the weaver has to decide which loom he should rush to first. Conventionally, this decision is based on the operators empirical judgement, and if such decision is erroneous, it results in a serious decrease in the operational efficiency of the machines.
A principal object of the present invention is to provide an apparatus capable of sequentially carrying the repair operator to a plurality of malfunctioning machines in accordance with the optimum priority in which repairs should be made, thereby maintaining the highest operational efficiency of the machines.
SUMMARY OF THE INVENTION In order to attain the above-described object, in the automatic apparatus of the present invention, information signals corresponding to the causes of the machine malfunctions are compared with predetermined patterns of operational priority signals for the machines, whereupon an address signal of the machine producing the information signal of first priority is produced. This address signal is compared with an address signal of the carriage, and the resultant distance signal is used for selection of the driving direction of the carriage. Both the priority machine address signal and the direction signal are brought into a control circuit of the carriage, which produces a corresponding operational signal for exciting the driving means of the carriage. The instantaneous location relationship between the carriage and the machine of the first priority is continuously detected, and the carriage is stopped when it arrives at the location of the priority machine. Driving control of the carriage can be shifted from automatic to manual and vice versa.
BRIEF DESCRIPTION OF THE DRAWINGS Further features and advantages of the present invention will be made apparent from the ensuing description, which is directed, for the convenience of the explanation, to the case wherein a plurality of weaving looms are installed in a weaving mill, reference being made to the accompanying drawings, wheerein:
FIG. I is a block diagram of a principal arrangement of the automatic apparatus of the present invention,
FIG. 2 is a block diagram of a detailed arrangement of the memory means shown in FIG. 1,
FIG. 3 is a block diagram of the memory circuit shown in FIG. 2, together with its related display parts,
FIG. 4 is a schematic plan view of a mill equipped with a plurality of machines and corresponding car riage detector switches,
FIG. 5 comprising FIGS. 5-] and 5-2 is a detailed logic circuit of memorizing means 2 and comparing means 3 of FIG. 1,
FIG. 5A is the waveform of the output signal of control unit 101 of FIG. 5,
FIG. 6 is a detailed block diagram of direction selector circuit 6 of FIG. 1,
FIG. 7 is a logic circuit of gate circuit 320 of FIG. 6,
FIG. 8 is a block diagram of the auxiliary circuits which apply the control signal to a carriage,
FIG. 9 shows a plurality of machines and corresponding paths of a carriage together with a plurality of cross points,
FIG. 10 shows the logical structure of a cross point, and
FIG. 11 is a detailed block diagram of the logic circuit of a carriage 9 of FIG. 1.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT In a preferred embodiment of the invention, as illustrated in FIG. 1, the automatic apparatus includes a plurality of looms I, which have means for sensing failures and for generating malfunction signals A, composed of cause-information signals A and machine address signals A The signals A are centralized and brought into memory means 2 connected to respective looms l. The cause-information signals A are given characteristic patterns in accordance with the kinds and types of the causes of the loom malfunction, while the locations of the looms l producing the cause information signals A, are represented by the predetermined machine address signals A:-
The combined output signal A, from the memory means 2, defining the priority values and positions of the malfunctioning machines is coupled to a priority comparator and memory means 3, which is provided with a circuit for scanning the priority sequence of the information signals A, in reference to a reference operation pattern signal B previously stored in the comparator and memory means 3. By the operation of this priority scanning circuit, the information signals are sequentially registered in a register of the comparator and memory means 3 in the order of their priority.
In some cases, two or more loom malfunctions have equal priority. In order to select the loom malfunction of the first priority, the address signals of the looms producing the registered information signals are compared with a carriage address signal G. In the case where the malfunctions of two looms are ranked equally, in view of the reference operation pattern signal B, the loom located closest to the position of the operators carriage is selected as the loom of the first priority, and a corresponding priority loom (machine) address signal C is produced so as to be transmitted to a control circuit 4 on the operators carriage 9. This priority loom address signal C is compared with the carriage address signal G within the comparator and memory means 3. Both the address signal C and the carriage address signal G are brought into a direction selector circuit 6 and a resultant direction signal E is coupled to the control circuit 4 of the carriage 9. Upon receipt of the priority loom address signal C from the comparing means 3 and the direction signal E from the direction selector circuit 6, the control circuit 4 produces an operational command signal F which is coupled to the driving means 7 for the carriage. The driving means 7 is provided with a device for producing the carriage address signal G showing the location of the operators carriage 9 with respect to a reference point fixed in the mill. This carriage address signal G is transmitted to a carriage-loom address comparator 8 also receiving the priority loom address signal C from the comparator and memory means 3. When the carriage 9 arrives at the location of the loom of the first priority, the carriage loom address comparator 8 produces a stop signal H, and the driving operation of the driving means 7 is thereby terminated. Upon arrival at the loom, the operator performs the repair work necessary to eliminate the malfunction of that loom, and, after completion of this repair work, the loom is restarted and a signal reporting this completion of the repair work resets the automatic apparatus of the present invention.
Control of the driving means 7 can be shifted from automatic to manual by operating a switch mounted on the carriage 9, so that it is also possible for the operator to manually control the driving means 7 of the carriage to direct it on the basis of his empirical judgement.
In a practical embodiment, signals C and E are transmitted to a carriage 9 through an auxiliary circuit (not shown in FIG. I). The structure of said auxiliary circuit will be explained later in connection with FIG. 8.
A detailed arrangement of the memory means 2 is shown in FIG. 2, wherein there are provided encoders 11 related to the respective looms I, an information center 12 connected to the respective loom encoders 11, and a buffer memory 13 coupled between the information center 12 and a memory 14.
When the malfunction takes place on a certain loom 1, this malfunction is first sensed by a corresponding mechanical signal. For example, breakage of a warp may be detected by a downward movement of a corresponding dropper. Next, this mechanical signal is transduced into a corresponding electric signal and further encoded into a corresponding malfunction causeinformation signal by the encoder ll associated with that loom l. Malfunction cause-information signals, obtained in this manner, are subjected to a scanning operation by a scanning pulse signal I emitted by the information center 12, and the picked up information signals are transmitted to the information center 12. Simultaneously, the address signals of the malfunctioning looms are also transmitted to the information center 12. In this case, the address signals are informative of the location of the loom of malfunction with respect to the 0 reference point suitably selected in the mill. The address of the looms may be given in the form of matrix representations or in the form of X Y coordinates. From this information center 12, the information signals are transmitted to the buffer memory 13 which is provided with a distribution circuit. By the operation of the distribution circuit, these information signals are compared with data signals previously provided in the buffer memory 13 and are registered into the memory 14 according to the kinds and types of the causes of the loom malfunctions.
In the arrangement shown in FIG. 2, the memory 14 may be connected to additional elements as shown in FIG. 3. An accumulator 16 for accumulating the nonrunning time of the looms and a display panel 18 for the causes of the loom malfunctions are connected in parallel to the memory 14, in an arrangement receptive of the output signal of the memory 14. A display panel 17 for the nonrunning time for the respective malfunctions is connected to the accumulator 16.
In the case of the above described embodiment, the driving means 7 is provided with a device for producing the carriage address signal G showing the location of the operator's carriage 9 with respect to the 0 point fixed in the mill. However, this device can be replaced by spaced detector switches 19 planted in the floor of the mill along the advancing paths of the operators carriage 9, as shown in FIG. 4. When the operators carriage 9 passes the position of a certain detector switch 19, that detector switch 19 produces a signal corresponding to the carriage address signal G and this signal is transmitted to the comparator and memory means 3. The pattern of the signal is formed according to the relationship of the location of that detector switch 19 with respect to the 0 point fixed in the mill. Further, the advancing direction of the operators carriage 9, during its travel, is also sensed by these detector switches 19. The detector switches 19 may be interspersed so as to show the location of the carriage 9 either in a matrix representation or in the form X Y coordinates.
The operation of memorizing means 2 and comparing means 3 in FIG. 1 will now be explained in full in connection with the logical circuit of FIG. 5. In FIG. 5, machines la, 1b, 1n correspond to a loom l of FIG. 1. A circuit having address counter 102, binarydecimal converter 102a and driver 103 corresponds to information center 12 of FIG. 1. A circuit having gate 126, register 13], gate 134 and their relating circuits corresponds to buffer memory 13 of FIG. 1. A circuit having register circuit and step up circuit 161 corresponds to memory 14 of FIG. I. And the rest of FIG. 5 corresponds to comparing means 3 of FIG. 1. Further priority signals 141, 142 and 143 correspond to signal B of FIG. 1, and output signals 234 and 235 correspond to address signal C of FIG. 1. As the structure of the logical circuit of FIG. 5 is easily understood by anyone skilled in the art from above explanation and reference number table at the end of this specification, no explanation about the structure of the logical circuit of FIG. 5 is necessary, and the operation of FIG. 5 is next explained.
l. A pulse signal from control unit 101 steps up the content of address counter 102, which scans the machine address and gives an address of the machine which should forward the data. Each output terminal A, B, C, D and E of control unit 101 gives the corresponding signal shown in FIG. 5A.
2. The machine address given by address counter 102 is converted from binary number to decimal number by binary-decimal converter 102a, and the driving signal appears at one of the address lines 104 which provide the output signal of driver 103.
3. Data 106 from machine 1 (1a, 1b, In) is received by receiver 107, and said data 106 is stored in register 109 by read-signal 108 from control unit 101 to register 109. Data 106 has condition flag 111, endflag 112, working information, and priority informatron.
4. When condition flag lll stored in register 109 is on, it means the corresponding machine is requesting the work, and data 106 is processed only when said flag IS on.
5. When condition flag 111 is on, and end flag 112 is off, AND gate 114 and 115 connected to gate 113 open together with gate 113, then data 110 is sorted by priority circuit 140 according to the priority of data 110. Said priority circuit 140 provides one of priority signals 141, 142 or 143, which open one of the corresponding gates 144, 145 and 146. Accordingly, the machine number of the problem is stored in register 160. The actual data 110 sent from the machine 1 is not stored in register 160, but is indicated at the panel of the machine.
6. Said register 160 is controlled by step-up circuit 161 so as to store the data from the most significant digit.
7. Suppose that end flag 112 of data stored in register 109 is l, flip-flop 151 is set to l and one-shotmultivibrator 166 is triggered, and the highest priority stored in one of registers 162, 163 and 164 is detected by priority detector 165. One of flip-flops 171, 172 and 173 is set to 1 according to the coincidence of the output of one-shot multivibrator 166 with one of the outputs of priority circuit 160.
8. If there is no data in register 160, that is to say, if work is not requested, zero-detection circuit 168 detects this state and outputs zero to output line 169, which closes gate 147. Therefore the operation of the circuit in FIGS. 5-1 and 5-2 finishes, and said circuit waits data 110 by keeping open gate 113.
9. If there is some data stored in one of registers 162, 163 and 164 of register 160, gate 147 opens and the output 120 of OR gate 121 becomes 1, and said output 120 closes gate 113 through the invertor. Therefore input data cannot be received and gate 149 opens. The clock pulse 129 from output terminal D goes through said gates 147 and 149, and opens gate 185, and the operation of priority decision begins.
10. At the same time output signal 148 of AND gate 147 opens AND gate 130 through OR gate 121 and output signal 120, and data from machine 1 is stored in register 131, which stores both the content of data and the address of the machine.
11. Initial operation control 216 has two flip-flops 186 and 188, and some gates. Said flip-flops 186 and 188 are reset to zero by the output of AND gate 228, The output of AND gate 228 is provided if there are both pulse signals 228. from one-shot multivibrator 166 just after appearing end-flag 112, and output signal 169 of zero detection circuit 168. Said circuit 168 tests it there is any data stored in register 160.
12. In the condition that initial operation control 216 is set to initial condition, when the second clock pulse appears from the output of gate 149, output 189 of flip-flop 188 becomes 0 and gate 185 is closed. Accordingly the operation of control 216 stops automatically.
13. The first clock pulse inverts flip-flop 186, and the output 169 of zero detection circuit 168 opens gate 191 and closes gate 192. Gate 200 is closed as output 230 of flip-flop 188 is zero. Accordingly output of gate 199 becomes zero and gate 198 closes. At the same time register is stepped up.
14. When there is only one data in one of three registers 162, 163 and 164 chosen according to priority, the second clock pulse provides zero at output line 169 of zero detection circuit 168, and closes AND gate 191. Gate 195 closes too as the outputs of gate 178, 179 and 180 are zero. At the same time, gate 192 opens, which opens gate 212 and sends data relative to the location of the machine from buffer register 202 to output line 215.
15. Output signal of zero detection circuit 168, which is now zero, is applied to gate 229 through the invertor. and clock pulse 150 is also applied to said gate 229 through gate 149. The output signal 157 of said gate 229, and output signal 158 of gate 192 reset flip-flop 151 to zero through gates 153, 154 and 152. At the same time one-shot multivibrator 231 is triggered, which provides priority signal 232.
16. When there are more than two data chosen according to priority in one of three registers 162, 163 and 164, output line 169 of zero detection circuit 168 provides 1. Therefore gate 191 opens, which opens gate 195, and the machine location data 181 of the second machine, which is the output signal of gates 178, 179 and 180, and distance data 184 to a carriage are stored in a buffer register 196. At this time flip-flop 188 inverts, which closes gate 185. And as output line 230 provides signal 1, gates 203 and 204 open. Accordingly distance data stored in buffer registers 196 and 202 are applied to comparison circuit 205.
17. Comparison circuit 205 provides the output signal and opens gate 213 when distance data stored in register 202 is larger than that stored in register 196. Accordingly machine location 208 stored in buffer register 202, which has low priority, is sent to a buffer register 217 through output line 214. Said register 217 also stores said data from the most significant digit by means of step-up circuit 218.
18. As gate 210 opens at the same time, machine location data 207 stored in the buffer register 196 appears at output line 215. Further as gate 200 and 198 open, the next data stored in a register having the second priority goes to the buffer register 202 with the next clock pulse.
19. On the other hand, when distance data stored in the register 196 is equal to or larger than that stored in the register 202, the output of comparison circuit 205 is zero and gate 209 opens. Accordingly machine location data 207 stored in the buffer register 196 goes to the buffer register 202 through output line 214. Further, as gate 212 opens, machine location data 208 stored in the buffer register 202 appears at output line 215, and, opening gate 193 and 195, the next data is stored in the buffer register 196.
20. The above operation, of comparing two distances, is repeated until output 169 of zero detection circuit 168 becomes zero. The machine location data with a larger distance which has a lower priority is stored in a buffer register 217.
21. As explained above, when the content ofa register with the highest priority becomes zero, X coordinate 234, Y coordinate 235 and priority signal 232 relating to the machine with the highest priority are provided by output signal 169 of zero detection circuit 168.
22. When the output of zero detection circuit 168 becomes zero, one of gates 222, 223 and 234 opens and the data stored in the register 217 returns to the original register.
23. Said operation finishes when the output signal 226 of zero detection circuit 225 becomes zero. Said output signal 226 opens gate 134 of the buffer register 131 through OR gate 121, and AND gates 136 and 137. A clock pulse from output terminal E of control unit 101 is applied to gates 134 through 137. Said clock pulse is divided into short period pulses, the number of which are proportional to the maximum memory ca pacity ofa register 131. The data 125 showing machine location and data 110 showing working information stored in a register 131 go to priority circuit 140. The address of a machine corresponding to data 125 is stored in register 160 from priority circuit 140 through one of gates 144, 145 and 146. Control unit 101 is designed so as to apply the next clock pulse 129 (D in FIG. 5A) just after all data stored in the buffer register 131 has been stored in the register 160.
24. Signal 226 opens gate 154 and resets flip-flop 151 through the invertor just after the transportation of data between buffer registers finishes. At this time as output 120 of OR gate 121 becomes zero, gate 113 opens again and input data from machine 1 can be received.
FIG. 6 shows a detailed block diagram of direction selector circuit 6 of FIG. 1, and FIG. 7 shows detailed logical circuit of gate circuit 320 of FIG. 6. Carriage address signal G of FIG. 1 is applied to gate 304 and 305 in FIG. 6 as X coordinate 620 and Y coordinate 621. Output signal 330, 331 and 332 correspond to direction signal E of FIG. 1. The output signal of gate circuit 320 is applied to points in FIG. 9 so as to control said points and lead the carriage 9 to the front of the machine which delivered a request. In FIG. 7, output 4 of decoder circuits 318 and 319 are shown, but the outputs of more than 5 of decoder circuits 318 and 319 are not shown for the sake of brevity.
The operation of FIG. 6 and FIG. 7 is described hereinafter.
1. As machine 1 is arranged to locate both sides of a path as shown in FIG. 9, a carriage 9 turns right or left according to the location of a machine. If the machine stands on the right side of the path, the carriage turns to the right and vice versa. Priority signal 232 sets X coordinate 234 and Y coordinate 235 of the machine location to registers 300 and 301, respectively. Output signal 330 which handles the carriage toward the machine with the problem is provided according to the sense (0 or I of the least significant digit 334 of the X coordinate of machine location signal 234.
2. The path number that the carriage must go through in FIG. 9 is calculated from X coordinate 234 of machine 1. The least significant digit ofX coordinate 234 of machine location stored in the register 300 is cleared as it has been used for handling of a carriage. The path number 302 that the carriage must go through is obtained by shifting said X coordinate right for one digit. Said path number 302 is applied to comparison circuit 308 and compared with X coordinate 620 of the carriage at this time, which is also applied to comparison circuit 308 through gate 304. Output 324 of comparison circuit 308 determines whether path number 302 is larger than X coordinate 620 of the carriage or not. Points A, B and C in FIG. 9 and FIG. 10 are controlled by said output signal 324, the output of decode circuit 318 which decodes path number 302, and the output of decode circuit 319 which decodes the X coordinate of a carriage at this time.
3. Comparison circuit 308 provides output signal one when path number 302 is larger than X coordinate 620 of the carriage.
4. As explained hereinafter points A and B are controlled by one of signals a b (12b2, which are the output signals of gates 415 419 in FIG. 7. Point C is controlled by one of signals ,6 which are the output signals of gates 410 414. For instance, suppose comparison circuit 308 provides an output signal, decode circuit 318 provides an output signal at output terminal 0, and decode circuit 319 provides an output signal at output terminal 0. In such a case signals a b, and c appear as in FIG. 7, and thus corresponding points a,, b, and c, are controlled.
5. The direction of movement of the carriage is controlled as follows. A carriage stands on the desired path when path number 302, where the machine is located, coincides with X coordinate 306 of a carriage. In this case comparison circuit 309 provides zero output. The other comparison circuit 310 compares Y coordinate 621 of a carriage through gate 305 with Y coordinate 303 of the machine. When Y coordinate 621 of the car riage is larger than Y coordinate 303 of the machine, said comparison circuit 310 provides output signal 326 and normal signal 331. On the other hand when Y coordinate 621 of the carriage is equal to or smaller than Y coordinate 303 of the machine, said comparison circuit 310 provides zero output, and reverse signal 332 is provided. The normal signal 331 or the reverse signal 332 drives the carriage to the normal direction or the reverse direction in the particular path.
6. The comparison circuit 309 provides output signal I when X coordinate 306 of the carriage is not the same as path number 302. In this case Y coordinate 303 of the machine and Y coordinate 307 of the carriage are applied to an adder 311, which provides the sum 312 of them. The comparison circuit 313 compares said sum 312 with N provided from constant number generator 314, where N is equal to the number of machines lined in one path. If N is larger than the sum 312, the comparison circuit 313 provides output 327 and normal signal 331 through some gates. On the other hand if N is equal to or smaller than the sum 312, said comparison circuit 313 provides zero output and reverse signal 332.
FIG. 8 shows a detailed block diagram of an auxiliary circuit which sends a signal to the carriage and receives a signal from the carriage. In FIG. 8, priority end signal 333 from FIG. 6, coordinates 316 signal of the goal machine, normal signal 331, reverse signal 332, and handling signal 330 are applied to a unit circuit 610, 610A, The unit circuit 610 provides output signal 622, which includes information of each input signal 333, 316, 331, 332 and 330. Output signal 622 is applied to the carriage 9 through detector switch 19 by wireless. Further, the carriage 9 provides signal 623 through detector switch 19 to unit circuit 610 by wireless. The X coordinate and Y coordinate of the carriage 9 at any moment are obtained from said signal 623 through encoder 619. The number of unit circuits 610 installed corresponds to the number of detector switches 19.
FIG. 9 shows the arrangement of a machine 1 and a path 21 of a carriage 9 together with a point 22. A plurality of machines 1 are arranged on both sides of a path 21 (0, l, 2, and constitute a pair of machine lines and l, 2 and 3, 4 and 5 Further common paths 21a and 21b are provided for all machines commonly. Transportation of a carriage 9 between path 210 or 21b, and path 21 is carried out through the switch over ofa point 22. The switch over ofa point 22 is carried out, as mentioned above, by the output signal of FIG. 7. That is to say, the carriage 9 of FIG. 1 is introduced to the front of the machine of the problem through suitable control of a point 22 of FIG. 9.
FIG. shows the logical structure of a point 22. A point 22 has sub-paths 31, 32, 33 and 34, and subswitches A, B and C. Sub switch C connects sub-paths 31 and 34 when the control signal from gates 410 414 in FIG. 7 is zero, while it connects sub-paths 32 and 34 when said signal is one. Further sub-switches A and B control the transportation of the carriage between subpath 33 and 34 through sub-path 31 or 32. Sub-switch A connects sub-path 31 with sub-path 33 when the control signal from gates 415 419 in FIG. 7 is zero, and disconnects sub-path 31 with sub-path 33 when said signal is one. Sub-switch B connects or disconnects sub-path 32 with sub-path 33 according to the control signals from gates 415 419 in FIG. 7.
FIG. 11 shows a circuit carried on the carriage 9 in FIG. 1. In FIG. 11, a circuit including drive circuit 820,
driving motor 821, motor drive circuit 827 and handling motor 829 corresponds to driving means 7 in FIG. 1. A circuit including gates 811 and 812, memory 813 and coincidence circuit 815 corresponds to address comparator 8 in FIG. 1. The rest of FIG. 11 corresponds to control circuit 4 in FIG. 1. In FIG. 11, reference numbers 331A, 332A, 316A and 330A mean sensors which pick up the information signal from 331, 332, 316 and 330 in FIG. 8 through detector switch 19 by wireless.
1. Normal signal from sensor 331A and reverse signal from sensor 332A are stored in memories 808 and 817 through amplifiers 800 and 801, respectively. On one hand, a repairman watches and confirms the next address of the machine to be repaired and its direction (normal or reverse) by means of display 805, and switches on the start switch 804. On the basis of said information, the output 819 of motor controller 818 is applied to drive circuit 820. Therefore, the driving motor starts to rotate in a predetermined sense, and the carriage 9 moves forward or backward according to the sense of rotation of motor 821. Accelerator 806 con trols the speed of the carriage 9 as desired.
2. Handling information from handling sensor 330A is stored in memory 822 through amplifier 803. Handling motor 829 rotates in a sense according to the sense of said handling information. Therefore, the chair on which a repairman sits on the carriage 9 (not shown) turns its direction to the desired machine, and memory 822 is cleared by limit switch 823.
3. During the carriage 9 stops, output 819 of motor controller 818 is zero, therefore, said output 819 opens gate 811 through invertor 830. Accordingly the coordinates of the goal machine as picked up by sensor 316A is stored in memory 813 through said gate 811. When the carriage 9 starts, gate 811 closes, and gate 812 opens. Coincidence circuit 815 provides an output signal when the output of memory 813 coincides with the output of gate 812. Said output signal clears memories 813, 808 and 817 to zero, causing the motor 821 stop. Thus the carriage 9 stops in front of the desired machine.
The foregoing description has been given for clear ness of understanding only. No unnecessary limitations should be understood therefrom, as modifications will be obvious to those skilled in the art.
As an aid in the understanding of the logical circuits, described in this specification, a reference number table is provided below.
Reference number table loom memorizing means comparing means control circuit direction selector circuit driving means address comparator carriage encoder information center buffer memory memory accumulator display panel display panel l9. dcteclnr switch 2|. path point output signal of u llip-llop l5l data showing machine location AND gale AND gate output signal of AND gate I35. I37. I38. I39. I40. I41. I42. I43. I44. I45. I46.
149. I50. I51. I52. I53. I54. I55. I56. I57.
I62. I63. I64. I65. I66. I67. I68. I69. I70. I7].
I72. I73. I74. I75. 176. I77. I78. 215.
302. 303. 304. 305. 306. 307. 308. 309. 310. 3] I. 312. a 313. 62l.
path path path path divided pulse AND gate zero detection circuit output signal of I38 priority circuit priority signal priority signal priority signal AND gate AND gate AND gate A ND gate output signal AND gate clock pulse OR gate AND gate AND gate output signal of AND gate I53 output signal of AND gate I54 output signal output signal register step up circuit register register register priority detector one shot multivibrator pulse signal zero detection circuit output line AND gate flip-flop flip-flop AND gate AND gate AND gate AND gate AND gate smaller data register register path number Y coordinate of a machine gate gate X coordinate of the carriage Y coordinate of the carriage comparison circuit comparison circuit comparison circuit adder output of 3] I (sum) comparison circuit Y coordinate of a carriage output of 605 Reference number table I29. I30. l3l. I32. I33. I34.
I80. I81. I82. I83. I84. I85. I86. I87. I88. I89. I90. I91. I92. I93.
I96. I97. I98. I99. 200.
210. 2Il. 2l2. 2l3.
clock pulse AND gate register step up circuit clock pulse AND gate AND gate AND gate machine location data computer circuit for distance the same as 620 and 621 distance data to the carriage gate AND gate output signal AND gate gate gate
buffer register AND gate gate gate
AND gate hufl'er register gate gate
comparison circuit output signal machine location data machine location data gate gate AN D gate AN D gate A N D gate larger data constant number generator gate output of 315 one shot circuit decode circuit decode circuit gate circuit output of 308 output of 309 output signal handling normal signal reverse signal priority end signal LSD (least significant digit) AND gate OR gate binary-decimal converter AND gate output of 60] gate amplifier pointer pointer one shot circuit unit circuit encoder X coordinate of the carriage memory (X, Y)
output signal of memory 813 coincidence circuit output signal of coincidence circuit 8I5 Reference number table 623. signal indicating carriage pass lil7. memory (reverse) 800. motor amplifier 8 l 8. controller 803. 8 l 9. output of Blll B04. start switch 820. drive circuit 805. display 82 I. driving motor 806. accelerator 822. memory (handling) 80?. output of 800 823. limit switch B24. detection circuit of direction of the chair 808. memory (normal) 825. output signal 809. output of 80] 826. motor control circuit 8 IO. output of 802 827. motor drive circuit 8| 1. gate 829. handling motor 8l2. gate 1 claim: 15 signals comprises means detecting a fault at a corre- I. An automatic apparatus for transporting an operadi g one of the looms and said work information tor t0 a plurality Of o tat ons in an p i signals comprising information content representative quence comprising, a driven carriage for transporting f th at r f the faults. an operator to work stations in an optimum sequence, 3 A t mati apparatus for transporting an operamoans at each Work Station having moans developing tor to a plurality of work stations in an optimum seoutput work information signals representative of work quence a rdi to clai 2, in which said memory that i8 10 b6 preformed at ll'lt? individual work stations means comprises encoders means connected to said and Work information signals having a P y and encoders emitting scanning signals for said encoders, a addressmemory means receptive of the output work buffer memory connected to the last mentioned means information Signals and Work information signals for provided with a distribution circuit and a memory concombining them into combined work information sigr d to id buff r memory rials and memorizing them, a P y comparator 4. An automatic apparatus for transporting an operacuit receptive of the combined work information sig- [or to a l li of work stations i an optimum mils from Said memory means for determining the p quence according to claim 3, in which said memory ority sequence of all the Combined 0rk inform i n means comprises accumulator means for accumulating Signals received and developing output P r y address the downtime of the individual looms, a display panel signals representative of the address priority of the seconnected to said memory means and another display quence of work at the work stations, a directionnnected to said accumulator means. selector circuit receptive of the priority address signals 5. An automatic apparatus for transporting an operaand asignal representative of the instantaneous address tor to a plurality of work stations in an optimum seof the carriage developing resultant direction signals, a quence according to claim 4, in which said priority control circuit receptive of the priority address signals comparator circuit comprises means receptive of a reffrom said priority comparator circuit and said resultant erence signal and means for comparing the work infordirection signals from said direction-selector circuit for mation signal with said reference signals for developing developing operational command signals for driving said output priority address signals when some of the the carriage in accordance with the command signals work information signals have equal priority. and having means developing a signal representative of 6. An automatic apparatus for transporting an operathe instantaneous address of the carriage relative to a tor to a plurality of work stations in an optimum segiven reference address, and a work-address comparaquence according to claims 5 including means to shift tor means for applying a stop signal to the driving said driving means to manual control from automatic means when the carriage arrives at the work stations secontrol. quentially in accordance with said priority. 7. An automatic apparatus for transporting an opera- 2. An automatic apparatus for transporting an operator to a plurality of work stations in an optimum setor to a plurality of work stations in an optimum seq n r ng to Claim in which Said driving quence according to claim 1, in which said means at. means comprises means for reversibly driving said careach work station comprises a loom at each work stariage. tion and said means developing the work information UNITED :SLIATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3 824,558 D t d July 16, 1974 I HEIJI KOSHIBA It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:
COL. 5, line 64, delete "gates 147 and" and insert --gate-.
COL. 6, line 8, delete "228" and insert l67--.
REFERENCE NUMBER TABLE COL. 9
N0. 3. delete "comparing means" and insert comparator and memory means;
NO. 102A. delete "102A" and insert l02a. NO. 113. delete "AND".
NO. 144. delete "AND";
NO. 145. delete "AND";
NO. 146. delete "AND";
NO. 150. delete "clock pulse" and insert --output signal of gate 149";
NO. 178. delete "AND";
Page 2 Patent No. 3,824,558
D d July 16, 1974 Inventor )1113 L] I KOSHIBA It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:
[SEAL] delete delete gate-- delete delete delete delete delete.
output "smaller data" and insert -output line--;
"timing counter" and insert -initial operation control-.
is to be added after "134. AND gate";
IIANDII "larger data" and insert -output line;
signal-- is to be added after "135. output of after "handling" insert --signal;
inverter-- is to he added after "816. output signal coincidence circuit 815";
Signed and Scaled this twenty-ninth D3) Of July 1975 A trees I.
RUTH C. MASON Allflslillg Officer