|Publication number||US3827357 A|
|Publication date||Aug 6, 1974|
|Filing date||Sep 12, 1973|
|Priority date||Sep 12, 1973|
|Also published as||DE2446937A1|
|Publication number||US 3827357 A, US 3827357A, US-A-3827357, US3827357 A, US3827357A|
|Original Assignee||Sperry Rand Corp|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Referenced by (9), Classifications (12)|
|External Links: USPTO, USPTO Assignment, Espacenet|
United States Patent 1191 Mahoney 1 Aug. 6, 1974 ON-THE-FLY PRINTER WITH SHORTENED I 3,303,776 2/1967 Rausch 101/93 c PRINT CYCLE 3,656,427 4/1972 Foley i .1 101/93 C 3,681,760 8/1972 Salava i 1 .1 340/1725  Inventor: Ralph W- Ma n y, Telford, Pa. 3,697,958 10/1972 Laren 340/1725 3,701,991 10/1972 L'k 11 101/93 CX  Ass'gnw i f 'f New 3,760,366 9 1073 GI'EZQOETY. 340/1725  Filed: Sept' 12! 1973 Primary Examiner-Robert E. Pulfrey 2 App] 39 3 Assistant Examiner-Edward M. Coven Attorney, Agent, or FirmCharles C. English  1.1.8. Cl. 101/93 C, 340/1725  Int. Cl. B4lj 7/08, G06f 3/12  ABSTRACT  Field of Search 101/93 C; 340/1725; ,9
235/61 P A11 on-the-fly prmter 1s equipped wlth an assoclative memory which is arranged to automatically ac-  Reerences Cited count for all the non-printable characters in a print UNTED STATES PATENTS line and to shorten the print cycle time of the printer.
3,289,576 l2/l966 Bloom et al 1. 101/93 C 9 Claims, 7 Drawing Figures q so 301 IF? 2113515 MEM. LOCATIONS 0-63 I I SELECY ADDRESS 1 D l rg mmhi's 700 CHIPS 31,12,311 3O T3 -31O 21 670 L 0 }r0 cums -680 F 31,32,33
1332mm I I 82 T.
TO CHIPS '*l FF F'F' "'5 T2 223: c1.. 1 SET CL. 1 SET 26 rem/1mm: COUNTER 48b 491: m T 'T 64 equal DATA Icr W 63 65 66 W5 39o 1 420 TM TF4 n SP 480 49a 52 TF3 2 -1 -F i .J217 :F 93 39 842 62 3?, s zt 48 49 27 TF2 't'lfi '8 "'7 w t 5 T0 CHIPS t3; 3|, 32, 33 2 BUS 22 PATENIEUIUB 61974 SHEEI 1 OF 5 mmooomo EmE Mi Mwfimmmw mommmuomm 225182 M68 55;: 3526 IMPZEQ 26x6 mm PATENIED 51974 SHEEI 2 IF 5 mm mam non 0m nOm om Ow mm mm mm mmm m mZOFdOOJ 552 mm mm com 2m ON-THE-FLY PRINTER WITH SHORTENED PRINT CYCLE BACKGROUND This invention relates to an on-the-fly high speed printer for use with automatic digital computer systems and in more particular to an improved means for shortening the print cycle time of such printers.
The oscillating bar printer described in US. Pat. No. 3,282,205 or the moving band printers described in U.S. Pat. Nos. 3,303,776 and 3,289,576 are examples of the different classes of on-the-fly printers with which the present invention is concerned. Rotating drum printers, now well known to the art, are also illustrative of another class of on-the-fly printers with which the present invention is concerned.
In general, an on-the-fly printer is comprised of two basic components; namely, an electro-mechanical print mechanism and an electronic control section therefor. The print mechanism includes a constantly moving type carrier; a plurality of print hammers; and means for guiding and feeding a print record medium between the hammers and the type carrier. The type carrier which may be a chain, a band, a bar or a drum has a plurality of different type characters so located thereon as to form at least one complete character set. The character set is arranged on the carrier so that as the carrier is moved one or more complete character sets sequence past each hammer during the print cycle. Generally a separate print hammer is provided for each print column and each of the hammers is actuated when the type character aligned therewith corresponds to the character to be printed in that particular print column.
The electronic control section usually includes, a line buffer memory for storing a line of data to be printed; a code generator synchronized with the movement of the type carrier to identify the type characters coming into printing position; and a comparison circuit for comparing the type characters coming into printing position with the data characters stored in the print line buffer memory. Whenever the comparison circuit indicates that the type character coming into a printing position in a print column corresponds to the data character to be printed in that column, the corresponding print hammer is actuated and the character is printed. After all of the columns have been printed the printer electronic section generates a print end" signal which may be fed back to the data source to request the next line of data to be printed.
One common method of generating the print-end signal is to use a counter circuit or the like which counts the number of equal comparisons generated by the comparison circuit and when this count reaches a predetermined value the print-end signal is generated. A shortcoming with this mode of operation is that the printing rate or the print cycle time remains fixed even though the ratio of printable to non-printable characters in a line of data may vary. In more particular, the line of data stored in the print line buffer memory may frequently include data characters which are not part of the character set contained on the type carrier. In this case, those characters which are not on the type carrier are, of course, non-printable and an equal comparison will not result. As a consequence, the electronic section of the printer will contain means for generating a print ending signal after it has been established that all the different type characters of a complete set have sequenced past each of the print hammers. This action requires aminimum fixed period of time.
To avoid the fixed cycle print rate limitations the prior art (US. Pat. No. 3,289,576) has suggested the use of a print cycle control memory plane. The print cycle control memory plane parallels the print line buffer memory which is addressed synchronously with the print line buffer memory.
Initially, each memory location in the print cycle control memory plane is set to its zero state. During the time that data is being read into the print line buffer memory, each location in the print control cycle memory corresponding to those locations in the print line buffer memory storing a printable character is set to a binary one'. Blanks or other types of non-printable characters loaded into the print line buffer memory are identified and prevent the setting of the corresponding locations in the print cycle control memory to their one state. Thus, at the end of a read in cycle every printable character stored in the print line buffer memory is represented by a one stored in the corresponding print cycle control memory location.
During read out, the memory locations in the print cycle control memory are switched to their zero state for each equal signal comparison from the comparison circuit. Finally, when all of the locations in the print cycle control memory have been switched back to zero it is known that all of the printable characters have been optioned for printing and the printing of a line of data should have been completed.
The disadvantages of the above prior art approach are that a special no print" signal must be generated by the program or by providing special hard wired decode circuits for each non-printable character. Moreover, the entire process of clearing the print cycle control memory and setting up the one states in the appropriate memory locations of the print cycle control memory must be repeated for each line of data stored in the line buffer.
SUMMARY OF INVENTION The present invention resides in the electronic control section for an on-the-fly high speed printer. The control section is conventional in organization except that it includes an associative memory which is used to automatically step the comparison counter for each non-printable character received by the print line buffer memory. The associative memory of this invention has as many storage locations as there are possible binary code combinations utilized by the printer system. For example, if an eight bit binary code is utilized by the system, the associative memory will contain 256 storage locations.
Initially, during the start up of the printer, all of the memory locations in the associative memory are set to a first state. Then the code combinations used to represent the character set contained on the type carrier are sequentially fed to the associative memory as memory address signals. Each distinct code combination addresses a different location in the associative memory, and as it does so it causes the addressed location to be set to a second state. At the end of this operation, the memory locations in the associative memory which correspond to the complete character set contained on the type carrier are all set to a second state while the memory locations which have no correspondence to the character set (non-printables) all remain set to their first state. After the associative memory has been set up as above described, the printer is ready to go into its print mode. During this phase of operation, the data bytes forming a line to be printed, are transmitted from the data source to the print line buffer where they are stored. As these characters are being stored they are also used to automatically address the associative memcry and read out the state of the addressed location. Those locations which are in their first state (non printable) generate a stepping signal which is sent to the comparison equal counter to step this counter once for each non-printable character being stored in the print line buffer. In this way at the end of the data input cycle before printing has started the comparison equal counter has taken into account all the non-printables contained in the print line. Thus when printing actually starts only the printable characters need be counted before a print-end signal is generated. Consequently, the print cycle time is not fixed since the printing can be terminated and the next line of data requested as soon as all the printable characters have been printed.
It is accordingly an object of the present invention to provide an automatic control over the print cycle time of an on-the-fly printer.
It is another object of the present invention to provide a simple means for automatically controlling the print cycle time of a large class of on-the-fly printers.
These and other objects and features of the present invention will become apparent upon a careful consideration of the following detailed description when taken together with the accompanying drawings wherein:
FIG. I is a highly simplified block diagram of a typical on-the-fly printer system showing the incorporation of my invention therein;
FIG. 2 is a simplified diagram showing the addressing scheme, during read out, for the associative memory;
FIGS. 3, 4 and 5 taken collectively show in somewhat more detail the addressing and controls for the associative memory;
FIG. 6 is a block illustration of a timing pulse generator useable by the present invention; and
FIG. 60 comprises a set of timing diagrams useful in explaining the operation of FIG. 6.
Reference is now made to FIG. I. In this figure the block 10 represents the central processor of a computing system. The central processor 10 is of conventional design and includes within its organization a suitable input/output channel. Connected to the input/output channel is a data bus 24 and a set of control cables 25. The data bus in the present example includes eight parallel signal lines over which the 8 binary bits of an 8 bit character byte is applied to the main printer control circuits II which is also of conventional design. The printer control circuits ll typically include a data output register for storing a byte of data delivered thereto from the central processor 10, and a control register for storing command signals also delivered thereto by the central processor over the data bus 24. The printer control logic 11 further includes a decoder network connected to the control register for decoding the commands stored therein and for delivering suitable control signals to the rest of the printer. Further circuits typically included in the printer control logic 11 are: counters for counting data bytes comprising a line of print, or for counting and controlling certain operations in the system, a clock source for providing timing signals used in timing the operation of the printer; and a number of control flip-flops for producing various control signals which are also used by the printer.
The block labelled 12 is the print line buffer memory for the printer and as shown it is understood to be a non-destructive memory which includes the usual read/write control and memory addressing circuits. The print line buffer 12 is used to store the line of data characters to be printed and thus contains as many character storage locations as there are columns of print utilized by the printer. Each location of the print line buffer is capable of storing one 8 bit character byte which is transmitted thereto from the output data register of the control circuits 11 via an eight line cable designated 22.
The block 14 represents a code buffer memory which as shown is understood to be a non destructive read out memory which includes the usual memory addressing and read/write control circuits therefor. The purpose of this buffer memory is to store the binary coded signals representing each of the printable characters carried on the type carrier of the printer mechanism 21. Thus, code buffer memory 14 will contain at least as many 8 bit character memor locations as there are different type characters in the character set on the type carrier. In practice, and particularly with band printers one complete type character set may be repeated several times on the band in order to increase the printing rate of the printer. For example, a 48 character set may be repeated as many as eight times on the band. In this case the code buffer may have as many as 384 locations, one set of 48 locations for each character set on the band, and each set of 48 locations stores the codes for the characters making up the character set contained on the type carrier. The code buffer 14 like the print line buffer 12 is connected to the output data register of the printer control circuits 11 via the data bus 22.
Connected to the outputs of the print buffer memory 12 and the code buffer 14 is the comparator circuit 16. The comparator circuit 16 has a first set of eight input terminals connected to the 8 bit output of the print line buffer 12 via cable and a second set of eight input terminals connected to the 8 bit output of the code buffer 14 via cable 14a. In operation, the comparator compares the coded output from line buffer 12 against the output from code buffer I4 and whenever the character codes simultaneously being read from these memories are the same, the comparator l6 develops an output signal on line 17.
Further included in the printer illustrated in FIG. I is the print mechanism 21 itself. This mechanism, it will be understood, includes the type character carrier; a set of print hammers, (usually one for each column of print); and a ribbon and paper guide and feeding mechanism. Also included in the printer system is a comparison equal counter 19 which is connected to receive and count the outputs of the comparator l7. Initially the counter 19 is set during the print cycle to a count corresponding to the maximum number of columns of print. Then the counter 19 is decremented by one each time the comparator 16 produces an output. A decoder network is connected to the output of the counter 19 and detects when the counter has been decremented to zero. When this condition is obtained, the decoder 20 sends a print-end signal to the control circuits 11 via path 15.
The foregoing described structure is conventional and its operation is as follows. During system start up, the central processor 10 issues an 8 bit load command over the data bus 24 to the printer control 11. At this time the central processor energizes one of the control lines 25 to indicate to the printer control 11 that a command is being transmitted. The printer control 11 senses the signal on the control line 25 and gates the load command into its control register. The decoder associated with the control register decodes the load command and causes the control line 26 to be energized which in turn places the code buffer 14 in a write mode. Thereafter, the processor 10 sends a set of code characters to the code buffer memory 14 via bus 24, control circuits 1] and bus 22. The code character set transmitted to the code buffer 14 correspond to the type character set contained on the type carrier of the printer mechanism 21 and the transmission is serial one character at a time. As each character is transmitted one of the control lines 25 is energized to cause the characters to be gated into the output data register of the control circuits 11 and then into the code buffer 14. During this period of time the memory addressing circuits within the code buffer memory 14 are made operative to place the successively received code characters in successive address locations of the memory 14. When the loading operation is completed, the printer control logic ll energizes one of the control lines 25 to signal the central processor 10 that the loading process has been completed and is ready to accept the next command. The next command in this case is a print command, and it is stored in the control register of the print control circuit I] and decoded to energize the print command line 27. Energizing the print command line 27 places the print buffer 12 in a write mode. Thereafter the processor 10 transmits a complete line of data characters to be printed over bus 24 to the Print Line Buffer 12 via the output data register in control circuits 1] and the bus 22. This transmission takes place one character at a time with the successively received characters being stored in successive memory locations of the print line buffer 12. After the complete line of print characters have been stored in buffer 12 (this fact may typically be indicated by a line character counter in the print control circuits 11 or the processor 10) the control circuit 11 develops a printing signal on the control line 28. The printing control signal appearing on line 28 together with an index pulse developed by printer mechanism 21 and appearing on line 29 are applied to the print and code buffers 12 and 14. The index pulse appearing on line 29 is generated each time a new group of type characters on the type carrier comes into printing position. The index pulse appearing on line 29 together with the printing signal appearing on line 28 cause the memories 12 and 14 to pass thorugh a read out cycle where the code for each type character on the band then in printing position is read out of code buffer 14 and the characters to be printed in these positions is read out of memory 12. The read out cycle is repeated for each index pulse appearing on line 29 and usually continues until all of the different type characters of a character set have sequenced past each of the print hammers. As the code and print characters are read out of the memories 14 and 12 respectively they are applied over buses 14a and 12a to the comparator 16 where they are compared. Each time these characters produce a match, a signal pulse is produced on line 17. The printing signal then present on line 28 opens the AND gate 18 to permit the compare signal to be applied to the print hammers contained in the printer mechanism 21. The printer mechanism 21 contains in addition to the aforedescribed components, a print actuator matrix which switches the output from gate 18 to the proper print column actuator. At the same time, the compare output signal from gate 18 is also applied through the 0R gate 23 to decrement the count stored in counter 19. Counter 19 is initially set in response to the print signal appearing on line 27, at the start of a print cycle, to a count which represents the maximum number of columns of print. After the counter has been decremented to zero, the decoder 20 detects this event and sends a signal back to the printer control circuits 11 via path 15. The control circuits ll sense the signal on path 15 and generates in response thereto a request for the next line of data or in the alternative terrninates the printer operation.
The aforedescribed structure and operation is conventional. The departure provided by the present invention lies in the incorporation of an associative memory 13 in the above-described structure. The associative memory has as many memory locations as there are possible binary codes in the multi-bit code em ployed by the printer. For example, in the present case where an 8 bit code is assumed, the associative memory has 256 memory locations and each location is capable of storing 1 binary bit. The associative memory also includes a set of address lines which when activated will access any of the 256 memory locations in accordance with the binary coded signal applied to the address lines. These address lines are connected to the output bus 22 of the data output register of the printer control circuits 11 so that each character appearing on the output data bus 22 will automatically access a corresponding location in the associative memory.
in operation and in response to the load command signal appearing on line 26, a circuit within the memory 13, as will be described hereinafter, operates initially to clear all of the memory locations in memory 13 to zero". After the clearing operation, the memory 13 is placed in a write mode so that as each code byte is loaded into the code buffer 14 it will also address the memory 13 via bus 22 and store a one in the addressed location. Thus at the end of the load operation when the code buffer 14 has stored all the incoming code bytes, the memory locations in the memory 13 corresponding to these code bytes will all be set to one. The rest of the memory locations in memory 13 will remain set to their zero state.
Following this operation the printer is placed in a print mode and a print control signal is developed on line 27 as previously indicated. When the printer is placed in a print mode and while the print buffer 12 is being filled with a line of data, the print signal on line 27 places the associative memory 13 in a read mode. Then as the bytes of data comprising the line to be printed are received and are stored in the print buffer 12 they are also applied via bus 22 to the address lines of the associative memory 13. Each data byte being stored in memory 13 thus causes a read out of the memory location it addresses in memory 13. If the addressed memory location stores a one the signal output from the associative memory 13 has a first level, while if the addressed location stores a zero the associative memory produces a read out signal of a second level. The second level or zero output signals of the memory 13 is applied to the decrementing input of counter 19 via line 23a and the OR gate 23. Thus while the print buffer 12 is being loaded and before a printing operation occurs, all the non-printable characters, which are those addressed locations having a binary zero stored therein are used to decrement the counter 19. As a consequence, at the end of the cycle where the print buffer is being loaded with a line of data, the counter 19 will be decremented to a count which equals the number of printable characters which are stored in the print buffer 12. Then as printing proceeds the counter 19 will be further decremented via gate 18 and OR gate 23 to zero as soon as all of the printable characters stored in buffer 12 have been made available for printmg.
From the foregoing it will be apparent that a feature of the present invention is that with a conventional load command where each printable character is being stored in buffer 14 the associative memory is simultaneously and automatically being set to distinguish between printables and non-printables without further program intervention. Also that during the execution of a print command where the buffer memory I2 is being filled all the non-printable characters are accounted for automatically.
It will be further apparent that the load command, which functions to simultaneously load the code buffer 14 and set the associative memory 13, need be executed only once during the printer start up and then thereafter the associative memory will automatically distinguish between printable and non-printables for each successive line of print data. Moreover, if it becomes desirable to change the code used by the system a new load command will automatically set the associa tive memory to recognize the new code without further intervention.
Before discussing the associative memory in detail, a discussion of this memory and its organization during read out will now be made in connection with the simplified illustration of FIG. 2 to which reference is now made. As herein illustrated, the memory is made up of four Integrated Circuit Chips 30, 31, 32 and 33 each of which are stock items made by lntersil and others. For example, the Integrated Circuit Chip designated No. IM55OI made by Intersil Corporation of Cupertino, Calif. is suitable for the present application. Each chip contains the facility for storing l6 4-bit words and thus four such chips can be used to store 256 bits or I bit for each of the 256 code combinations possible with an 8 bit signal byte. Each of the chips has a 4 bit address section with a built in decoding circuit arranged so that energization of the 4 bit address input will select one of the l6 4-bit words for reading or writing. The four bit address terminals for chip 30 are shown at 30a, 30b, 30c and 30d and it will be understood that the other chips 31, 32 and 33 have similar address inputs. Each of the chips also further contains a 4 bit output section shown at 30e, 30f, 30g and 30h for chip 30; at 3le to 31h for chip 31 and so on. These outputs are arranged so that on readout the 4 bits (MSB to LSB) of a selected word appear simultaneously on the respective e to )1 terminals of the selected chip. All of the chips also contain, but not shown in this figure, a 4 bit data input section for feeding input signals into the chip during a write operation and a write enable terminal which when held at a first potential level permits nondestructive readout from the chip and when held at a second potential level permits writing. The write enable terminals of the chips are normally all held at their read out potential level except during a write operation. Finally, each chip has a chip select terminal 35 to 38 which has to be energized to render, the input, the output, and the addressing circuits of the chip active.
The addressing information for the memory appears on the eight line bus 22 connected to the output data register in the control circuits 11. This bus has the code characters applied thereto during the load command and the print data characters during the print command. In each instance the coded characters can be thought of, insofar as the associative memory is concerned, as having the following format:
Bit Position Format In this format the least significant two bits BB are used to select one of the 4 bits of a word, the 4 middle bits 3 to 6 (WWWW) select one of the sixteen words of a chip and the two most significant bits 7 and 8 (CC) are used to select one of the four chips. For example, it will be seen from FIG. 2 that when the 2 CC bits are 0-0, chip select gate 39 connected to the number 7 and 8 bit lines responds to energize the chip select terminal 35 associated with chip 30. Chip 30 is thus selected for reading or writing when gate 39 is active. The small circles at the base of gate 39 and the other gates, indicates a signal inverting action on the corresponding inputs to the gate. Thus, when the number 8 and 7 bits correspond respectively to O-l the chip selector gate 40 responds to energize the select terminal 36 to select chip 3]. Finally, from the connections shown in FIG. 2, a 1-0 condition and a l-l condition respectively for the number 8 and 7 bits will select chips 32 and 33 respectively. The four gates 39 to 42 taken collectively thus form a decoding network for chip selection.
Returning to the output section of the chips 30 to 33, it will be seen that the corresponding output bit lines from each of the chips are buffed together via a respective one of four OR gates. Only the first (MSB) and fourth (LSB) of the OR gates are shown at 43 and 44 respectively. The output of each of these four OR gates serves as one input to a respective AND gate; only the first and fourth of which are shown at 45 and 46. The second input to each of the four AND gates is in turn derived from the four outputs of a decoder which comprises a four AND gate matrix only the first and fourth gates of which are shown at 48 and 49 in the drawings. These latter gates are connected to the 1st and 2nd bit lines of bus 22 so that each of the four gates represented by 48 and 49 is opened by a different signal input combination on lines 1 and 2 of bus 22. For example, when the input signal combination on lines 1 and 2 are both zero gate 49 is opened which in turn renders gate 46 operative. Similarly, when the input signal combination to gate 48 is l-l, gate 48 is open which in turn renders gate 45 operative. While not shown the other two gates of the decoding matrix connected to lines 1 and 2 of bus 22 operate to respond to the 10 and the signal combinations to in turn open up the two intermediate output gates (not shown) between gates 45 and 46. Finally, the outputs from all four of the output gates represented by gates 45 and 46 are buffed together by the OR gate 47 to form common output line 50 for the memory.
From the foregoing it will be recognized that, during read out, an imcoming coded signal byte appearing on bus 22 and ranging from 00000000 to 001111 11 will address one of the 64 bit locations in chip 30; an incoming coded signal byte ranging between 01000000 and GI l l l l ll will address one of the 64 bit locations in chip 31; an incoming coded signal byte ranging from 10000000 and lOl l l l l 1 will address one of the 64 bit locations in chip 32; and finally, an incoming coded signal byte ranging from I 1000000 and l l l l l 1 l 1 will address one of the 64 bit locations in chip 33. For example, assume the incoming coded signal byte to be 101 l 11 l l CCWWWWBB It will be seen that in this byte, the CC bits are decoded by gates 39 to 42 to select chip 32 which contains storage locations 128 to 19]. The WWWW bits are internally decoded by the chip 32 to select the 16th 4 bit word in chip 32, and the BB digits are decoded by the four gates represented at 48 and 49 to select gate 45, the MSH bit position of the 16th word in chip 32.
Reference will presently be made to FIGS. 3, 4 and 5 for a more detailed description of the operation of the associative memory 13 during both reading and writing. Before such description proceeds, however, reference will now be made to FIGS. 6 and 6a which show a representative timing pulse generator usable, for example, in the control circuits 11 for timing the operation of the printer. As illustrated, the timing pulse generator is of the recirculating type and includes a delay line 51 which has an input terminal 53 connected thereto, and a recirculation path 54 in which a shaping amplifier 52 is included. In operation, a single short duration pulse applied to the input terminal 53 propagates down the delay line 51 to its output terminal where it is returned to the input terminal 53 through the reshaping amplifier 52 and the feedback path 54. With this interconnection the single input pulse continuously recirculates through the delay line 51. The delay line in turn contains a series of generally equally spaced tap points indicated in the figure as TP-l through TP-6 arranged so that the recirculating pulse appears sequentially at the respective tap points during its propagation through the delay line 5]. This action will thus generate a recurrent series of pulses, such as illustrated in FIG. 6a, at each of the tap points TP-I through TP-6. As shown in FIG. 6a a pulse will appear at each of the tap points during each recirculation cycle with the pulses appearing at successive tap points being predeterminedly delayed from one another. In a typical embodiment the generated pulses might be, for example, I50 nanoseconds in duration and the time delay between the successive tap point pulses TP-l to TP-2, TP-2 to TP-3, etc. set at 200 nanoseconds.
Reference will now be made to FIGS. 3, 4 and 5. In connection with these figures it should be noted that the illustration given therein has been simplified by showing only one of the integrated circuit chips 30 from FIG. 2. It is believed, however, that the manner in which the remaining three integrated circuit chips 31 through 33 are incorporated in this structure will be obvious.
In the following description, the operation of the associative memory will be set forth in two phases. The first phase will cover the write operation which occurs during the load command and the second phase will cover the read operation of the memory which occurs during the print command. From the previous description it will be recalled that the first step in a write operation (load command) is the clearing of all locations of the memory to binary zero. A clear flip-flop 56, FIG. 4, is added for this purpose. The clear flip-flop 56, together with a load flip-flop 57 and a data request flipflop 58 comprise the basic controls for the memory 13. Initially it is assumed that all of these flip-flops are in their cleared condition and that their respective output lines are thus inactive. The output 60 of the load flipflop 57 is connected to a set control gate 59 for the clear flip-flop. The load flip-flop in its cleared condition and with its output line 60 inactive partially conditions the set input gate 59 of the clear flip-flop 56 as is indicated by the small inverter circle at the base of the gate 59. The second input to gate 59 is derived from the control line 26 of the control circuits II and this line is activated when the load command is given. Thus during a load operation line 26 is rendered active and gate 59 is opened to gate a TP-l timing pulse to the set input terminal of the clear flip-flop 56. When the clear flipflop 56 is set the clear output, terminal A, of the flipflop 56 is rendered active. The output of the clear flipflop at terminal A is applied (FIG. 5) in parallel via four OR gates to the chip select terminals 35 to 38 of all four chips 3033. Only the first 39a and last one 42a of the four OR gates are shown in the FIG. 5. The output of each of these OR gates 39a to 42a is applied to the respective select terminals 35 to 38 of all four chips thereby rendering all chips active.
The clear output, terminal A, of flip-flop 56 is also used via line 62 to jam the data inputs to each of the memory chips 3033 to zero at this time. Each chip (3033) has its own set of data inputs which comprise a set of four flip-flops. Only the first and last data input FF for chip 30 are shown in FIG. 5 at 67 and 68. Flipflop 67 is the M58 input while flip-flop 68 represents the LS8 flip-flop. As indicated, the data input flip-flops for each chip are set to zero or their cleared condition by the clear signal which appears on line 62 and is applied to the clear input of each of the data input flipflops via a set of OR gates only the first and last of which for chip 30 are shown at 65 and 66. Thus when the clear signal is applied to line 62 and thence through the respective OR gates represented by 65 and 66 it jams all four data input flip-flops for each chip to zero. In this condition, each of the data input lines to all of the chips is inactive or at a zero condition. The data input lines for the M88 and LSB positions for chip 30 are shown at 670 and 68a. When the clear signal first appears on line 62 it energizes a single pulser circuit 63 which send a momentary pulse out on its output line 64 to the clear terminal (CL) of a four stage, scale of 16 counter 55 clearing this counter to its zero state. The counter 55 is a standard integrated circuit chip which has a clear terminal labelled CL, a load terminal labelled LD, a counter terminal labelled CT and a set of four data input temiinals labelled DATA. A circuit such as that designated SN 74 l 93 sold by Texas Instruments Inc. of Dallas, Tex. and described in catalog CC 41 1 published l973 is representative of such a counter circuit. In operation when a pulse is applied to the clear terminal CL via lead 64 it clears the counter to zero while the activated clear line 62 operating on the load terminal LD renders the data input circuit of the counter inactive but the count terminal CT active. At this time the timing pulses TP-2, TP-4 and TP-6 are applied through OR gate 69 to the count terminal CT to sequence the counter through its 16 states. As it does so the output of the four stages of the counter are applied in parallel to the address lines of the four chips 30-33 so that as the counter is sequenced through its 16 states each of the l6 words of the associated chips will be addressed in sequence. The address lines for chip 30 are shown in FIG. 5 at 30a to 30d. Simultaneously with the addressing of the 16 words in each chip, the write enable termianl labelled WE of each of the chips 30, 31 32 and 33 is energized from the output of an OR gate 70 which receives the output of an AND gate 71. The latter gate has as its two inputs, the clear output of the clear flip-flop 56 as indicated by the terminal A and the further output from OR gate 72 which receives the TP-l, TP-3 and TP-S timing pulse signals. Thus as the counter 55 is sequenced through its 16 states addressing the 16 words in each of the chips in succession, the timing pulses TP-l, TP-3 and TP-S which are applied to the write enable terminals WE cause binary zeros to be written in each of the four bit positions of each of the l6 words. When the counter reaches its l6th count, (1 l l l the output of the counter 55 is decoded in an AND gate 73 to produce an output signal on terminal F. The output of decoder gate 73 at terminal F is applied as one input to the AND gate 61, FIG. 4, so as to gate a TP-2 timing pulse through the gate 61 and gate 75, which is being held open by the load command signal applied thereto via OR gate 260, to the set input of the load flip-flops 57. Setting flip-flop 57 applies a signal to the clear input of the clear flip-flop 56 thereby resetting the clear flipflop to remove the clear signal from its terminal A and from the line 62. Removing the clear signal from line 62 activates the load terminal LD of the counter 55 which in turn renders the CT terminal inactive to stop further counting by the counter 55 and at the same time renders the four bit data input terminals to counter 55 effective. At this time the counter 55 acts as a unity gain amplifier wherein the binary signal appearing on its data input terminals from bit lines 3 to 6 of bus 22 are amplified and appear as the addressing inputs to each of the four chips 30 to 33 in parallel. At the time the load flip-flop 57 is set via gates 61 and 75, its activated output 60 opens the set input gate 76 of the data request flip-flop 58. The latter gate, gates a TP-6 timing pulse to the set input of the data request flip-flop 58. When flip-flop 58 is set the output line 78 and terminal B becomes active. At this time the active output 78 of the data request flip-flop 58 is applied as shown in FIG. I to the printer control circuits 11. The latter device responds to the activation of the control signal 78 to send a data request to the central processor 10. The central processor in turn sends back the first signal byte comprising the coded characters to be stored in the buffer memory 14. As the central processor 10 returns the coded signal byte to the output data register of the printer control circuits 11 and hence to the output data bus 22, the control circuits ll responds to the receipt of a data byte by activating line 79. The
control signal so developed on line 79 is applied to a clear input gate 79a of the data request flip-flop, FIG. 4, to in turn gate a TP-l timing pulse through to the clear input of the data request flip-flop 58 to clear this flip-flop and to remove the output 78 from its active condition. When the requested data appears on bus 22 all 8 of its bits serve to address the corresponding location of the associative memory. Bits 7 and 8 are de coded by the four gates which are represented at 39 and 42 of FIG. 5 to activate the appropriate chip select terminal 35 through 38. Bits 3 through 6 of the received coded signal byte are applied through the data terminals of counter 55 to the address terminals of the four chips to effect a word selection within the four chips. Bits l and 2 are decoded by the four gates represented at 48 and 49, FIG. 5, to provide bit selection of the selected word in the selected chip. In this latter context the output of each of the four gates represented by gates 48 and 49 is applied through the respective OR gate 480 and 49a to the one input of each of the respective AND gates shown at 48b and 49b to the set input terminals of the data input flip-flops represented at 67 and 68. The l and 2 bits of the received data byte on the bus 22 will be decoded by gats 4849 to open one of the four gates 48b 49b and thereby gate a TP-4 timing pulse to the set input terminal of one of four flipflops 67-68. Gate 82 in the write enable circuit is new active and gate 7] inactive. Gate 82 will therefore gate a TP-S pulse through buffer 70 to the write enable line 70a to cause a binary one to be written into the bit position selected by flip-flop 67-68. Then at TP-6 following the storage of a binary one in the selected bit position of the selected word of the selected chip, the data request flip-flop 58 is again set by a TP-6 passing through gate 76 to make the next data request. Then at TP-l following receipt of the next byte, the data flip-flop 58 is cleared by gate 79a. Clearing flip-flop 58 renders gate 82 effective to pass the next TP-S through OR gate 70 to activate the write enable circuit and thus store a binary one in the next addressed bit position of the selected word and chip. This action continues until the printer control ll detects (such as by a counter) that all of the code bytes have been received from the processor. At that time the printer control ll places a signal on line to clear the load flipflop 57 and thus block gate 76 terminating the load operation.
A characteristic of the memory chips 30-33 is that the writing is destructive, so that upon energization of the write enable (WE) circuits all four bits of the selected word in the selected chip will store the binary condition present in the four associated input flip-flops. Thus to prevent the destruction of the unselected three bits of a selected word, the output bit from each bit position of a chip is fed back through corresponding lines shown as lines -91 for chip 30 and buffers 48a to 49a to the set input gates 48b to 49b. In operation then, at TP-3 each of the input flip-flops 67-68 is cleared to zero by the TP-3 applied to the reset input OR gates, 65-66. At TP-4 each of the set input gates 48b-49b is strobed to set each of the unselected flip-flops 67 and 68 to the state previously stored in the corresponding bit position of the memory as fed back via lines 90 to 91 and while the selected bit position is set to binary one via the decode gates 4849. Then at TP-S the write enable circuit (WE) is rendered operative via gate 82 to store the conditions of all four flip-flops 67-68 back into the selected word of the selected chip.
After the memory 13 has been cleared and then set by the load command as described above, the central processor issues the print command. The print command when recieved by the control circuits 11 causes the activation of control lines 27 and 80. Activating these two lines sets the load flip-flop 57 via gate 92. Setting the load flip-flop 57 conditions the setting of the data request flip-flop 58 via gate 76. This flip-flop is set at TP-6 via gate 76 and then reset at TP-l via gate 790. Each setting of the data request flip-flop causes a byte of data to be transmitted from the central processor 10 to the control circuits 11. This time, however, the bytes that are transmitted are those forming a line of data to be printed. Finally, after a predetermined number of such bytes are transmitted, the control circuit 11 deactivates line 80 to clear the load flip-flop 57 and cause the cessation of further data requests.
As each byte of print data is received and applied via bus 22 to the addressing circuit of the associative memory 13 it reads out the bit stored in the addressed location in the manner previously described in connection with FIG. 1. Specifically, bits 7 and 8 select the chip for read out; bits 3 to 6 select the word in the chip and bits I and 2 select the bit position of the word being read out. To select the bit position of the selected words, bits I and 2 are decoded by the four gates represented at 48 and 49 to energize one of the terminals R to U (FIG. 5) thus opening one of the four output gates repre sented at 45 and 46 (FIG. 3). The output of these four gates are applied to the OR gate 47 so that as each bit is read out of the memory it passes through the OR GATE 47. The binary zeros read out are inverted at the output of OR gate 47 as indicated by the small circle at the output of this OR gate and applied to AND gate 470. This gate also has impressed thereon the control signals from control lines 27 and 80 which are both ac tive during the time that the print data bytes are being transmitted. Also applied to this gate is the output line 78 of the data request flip-flop 58. This line becomes inactive at TP-l following receipt of a data byte and stays inactive until TP-b. Thus during this period a binary zero read out of the memory is gated through gate 47a to line 23a where it appears as a decrementing pulse for the comparison match counter 19 (FIG. 1).
In the operation of the printer, it will frequently occur that the code utilized by the printer will call for the printing of capital letters, for instance, while the type carrier will have only lower case letters carried thereby or vice versa. In certain codes the distinction between upper and lower case letters is represented by different combinations of the 7th and 8th bits. The re maining six bits for a capital and a lower case letter is represented by identical code combinations. When this occurs the programmer can elect to have the printer print the available print characters (upper or lower case) irrespective of the bit combinations used for the 7th and 8th bit positions by issuing a fold command. In this case, the fold command follows the *load" command and precedes the print command. When the fold command is recieved by the control circuits ll of the printer it causes the activation of line 81 from the control circuit 11 which in turn enables gate 93 (FIG. 5). Then when the print command is received it causes the activation of line 27 to apply a chip select signal via the four OR gates 39a to 420 to all the chip select terminals 35 to 38 thereby activating all of the chips. Then on read out the corresponding bit location of all four chips will be read out and any one of the four locations storing a one will be recognized as containing a printable location. Conversely, if all of the four locations being read out store a zero, this condition will be recognized as a non-printable and it will cause the counter 19 to be decremented.
From the foregoing description it will be seen that a single conventional load command operates to automatically and simultaneously load the code buffer and set the associative memory so that on issuance of the print command the printable and non-printable characters are accounted for automatically as they are stored in the print buffer.
What is claimed is:
1. In a high speed printer system which includes a moving type member having a predetermined number of different type characters carried thereby, a code buffer memory for storing a multi-bit binary coded representation of each character on the type member, and a print line buffer memory for storing multi-bit binary coded representations of the characters to be printed; the improvement which comprises: an associative memory having a set of addressing input terminals and at least as many one bit storage locations as there are different characters to be printed by the system, means for initially setting each of the storage locations in said associative memory to store a first binary bit, means storing a set of coded signal representations in said code buffer, said set representing the characters on said type member, means for simultaneously applying the coded signal representations comprising said set to the addressing input terminals of said associative memory to cause each storage location in said associative memory addressed by said coded signal representations to store a second binary bit, means storing a set of data characters in the print line buffer memory, means simultaneously applying the set of data characters to the addressing input terminals of said associative memory to cause the binary bits stored in the storage locations being addressed by the data characters to be read out from the associative buffer, and counting means for counting the number of first bits read out from said associative memory.
2. The system of claim 1 wherein said associative memory has as many storage locations as there are possible code combinations in the multi-bit binary code utilized by the system.
3. The system of claim I wherein means are provided to permit different data characters codes to address the same associative memory location.
e system of claim 3 wherein the last-named means may be selectively rendered operative.
5. The system of claim 1 wherein means are provided to permit a single data character to address a plurality of locations in said associative memory.
6. The system of claim 5 wherein the last-named means may be selectively rendered operative.
7. The system of claim 1 wherein the associative memory is made up of a plurality of similar memory sections and each of said sections includes a first decoder responsive to a first portion of a coded addressing signal to select a corresponding location in each of said sections and a second decoder means responsive to a second portion of the addressing signal to select one of the sections.
8. The system of claim 7 wherein means are provided to by-pass the second decoder means.
9. The system of claim 8 wherein the by-pass means may be selectively rendered operative.
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|U.S. Classification||358/1.16, 101/93.14|
|International Classification||G06K15/02, B41J1/00, G06K15/08, B41J1/32, G06K15/06, G06F3/12|
|Cooperative Classification||G06K15/06, B41J1/32|
|European Classification||B41J1/32, G06K15/06|