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Publication numberUS3828321 A
Publication typeGrant
Publication dateAug 6, 1974
Filing dateMar 15, 1973
Priority dateMar 15, 1973
Publication numberUS 3828321 A, US 3828321A, US-A-3828321, US3828321 A, US3828321A
InventorsBuhrke R, Rice V, Wilber J
Original AssigneeGte Automatic Electric Lab Inc
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
System for reconfiguring central processor and instruction storage combinations
US 3828321 A
Abstract
A system is disclosed including duplicate copies of central processors and storage means for switching active copies of central processor and primary copies of instruction through all combinations to find a working combination. The reconfiguration may be effected either through a fixed wired recovery control circuit which changes state in predetermined sequence or, alternatively, under program control.
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Description  (OCR text may contain errors)

United States Patent 1191 Wilber et a1. 5] Aug. 6, 1974 [54] SYSTEM FOR RECONFIGURING CENTRAL 3,409,877 11/1968 Alterman et al 340/1725 mCESSOR INSTRUCT'ON 5223312 31133? ??2""';;;i 2381535? 011 me t r ,1 STORAGE COMBINATIONS 3,623,014 11/1971 Doelz et al 340/1725 [75] Inventors: John A. Wilber, Elk Grove Village; 3,641,505 2/1972 Artz v. 340/1725 verner K. Rice whgaton; Rolfe E. 3,654,603 Gunning Cl 81. 340/1715 X Buhrke, La Grange Park, all of Ill.

{73] Assignee: GTE Automatic Electric Primary Examiner-Harvey E. Springborn Laboratories Incorporated, Northlake, Ill. 22 Filed: Mar. 15, 1973 [57] ABSTRACT [2]] Appl. No.: 341,428 A system is disclosed including duplicate copies of central processors and storage means for switching active copies of central processor and primary copies of [52] 'i g 315 instruction through all combinations to find a working [51] G m combination. The reconfiguration may be effected ei [58] 0 arc 3 I ther through a fixed wired recovery control circuit which changes state in predetermined sequence or, al- [56] UNITE D ;$?ES S:FENTS ternatively, under program control.

3,386,082 5/1968 Stafford et a1. 340/1725 11 Claims, 51 Drawing Figures ACCESS TRUNK! Pram/rm. car/mourn MATRIX DECODE a c DATA ms E5 1 0 cmcurT EGISTER INS TRU CTION STORE TO OTHER URI 5 CENTRAL PROCESSOR nccrss CIRCUIT NPUT- OUTPUT CIRCUIT PROCESSOR CONTROL C I RCU/T TO OTHER PS UM T5 PATENTH) Mill 5 7374 FIG.3

SHEEI 0% 0f 23 TIMING GENERA TOR CIRCUIT 6P4) 50 5O CPI ma 1 T66 LEVEL LEVEL ,52 MC "ENERATDR sEMRAr MAC 666 cm. I SWITCH/N6 "smrcnma cnns ccc SSBYL r X CONTROL ssan. mc MCC .Iswrrcmwa smmnma ncc PMC NETWORK NETWORK pm L51 5/ 1| Rcc rmma mum Rcc rmE LEVELS LEVELS TIME r0 6P0 T0 4 H6 4 he nooEpaAm READ/WRITE g; MEMORY AND LEVELS '00 [SR PERIPHERAL MAC ICC INSTMTION UNI];

cow 0L CIRCUITS 55 DP 6 CMPALCIPU AND 0pc DECODING Mm E INEXFRL CIRCUITS MMC 10c REGISTER 53 AND PLACE ACCEPT A no LEVELS ACCEPT DPC I CONTROL CIRCUITS us RANSFER aus .LEVELS TRANSFER com'RoL 0M cmcu/rs V 55 PROCESSOR CONTROL CIRCUIT (FCC) PATENTED 3.828.321

saw near 23 CPQ FIG. II cm I RCC a RC6 is CH Q M46 M66 1 I MCC MAC I I I I I, CONFIGURATION I I counaurmnow corvmoL cozvmoz. CIRCUIT I cmcu/r I CPAL I I cPAL I00 I I c cPAL (BUS I mus CONFIGURATION) CONFIGURATION) II TLGC MMC [cc I use MMC [60 f5? fix CONFIGURATION con/mm cmcu/r FIG. I2 MA'sB Q1 100 I :00 0 c 0P6 oPc 0P6 P cc I I Pcc TGC CCC IMRB I I MR3 IMDB I IM 08 uvsa I ms I rec PCC rec P00 060 I00 ccc 100 R66 rcc ncc rcc me we I ma mwc MAINTENANCE ACCESS CIRCUIT PATENTED 3.828.321

SHEEI 10 Q? 23 FIG [5 TIM/N6 GENERATOR PULSE CHART 0 l0 0 REcOIvEIOuRArIOIv CYCLE 0 r! 2 .0 4O 5. 6.0 Z0 8.0 90 IO .5 I5 2 .5 I05 #20 l I 1 15 l 1 1 415 F 1 I 1 l I 1 l I START OF TIMING GENERATOR 5001/ sEc, Rrz JLusEO T0 GENERATE CPTL, SICBL, RICCL, MIALL AND MAALL O .5 SEC I40 SEC RT2L| I USED TO GENERATE CPSWL 0 l0 1! SEC.

IOOsEc. RrsL I usEO r0 GENERATE RcEL 50011 SEC. RT4L2 n usEO r0 GENERATE ASE'L AND ASOL NOTE) RCC LOCKED OUT TO TRIGGERS FROM START OF CYCLE UNTIL END OF CYCLE (2) RT4L CAN OCCUR ANY TIME AFTER RT3L AND RT5L, NEW

RCC STATE STARTS AT END OF RT4L E5621 NEXT E z; C g smrE I'RAIvsITIOII TABLE ROEQROPSI EEEQQMEGEZZQ FUNCT'ON PRIME Rcc FOR CP SWITCH III CASE 5 P X 5 I X X X X REcOvERY PROGRAM INDICATES AOr/vE OP MALFUNCT/ON 5O X 5/ XXX X X 57,497 5gp SWITCH cP's IF STANDBY Is NOT X 52 X X X X III TROUBLE,- sTARr sRP I51 BECOMES PRIMARY INSTRUCTION 52 X 53 X X X X X TQRE smRr sRP EORcE CP SWITCH; Isc REcOIIIEs 53 X 52 X X X X X X X X PRIMARY/NSTRUCT/ON STORE srART sRP MAIN rEIvcE OOIWROL GROUP 9 000/0203 MCG-8 31 F1619 R H R R c c c c s s s r R c c O F F O R R s Rcc coIvrRoL POINTS MAINTENCE sEIvsE GROUP 8 00 00203 use-s 31 R 5 g 0 FIG 20 8 c A a s F F F F PATENTEDAUG 61w 3.828.321

sum NW 23 FIG 2 2 5 T D T OUTPUT szr com/1110s szr/ RESET RESET comm/1110s -D DUAL RANK FLIP FLOP IMPLEMTATION FIG. 23

INST FETCH DATA FETCH g gi ALT-UP sa CP ACTCP 50/ CP 0 a r 0 55m) 11105510011: swam: $1110 1110 Is CONFIGURATION 0 0 0 0 0 1 1 0 0 1 1 DUPLEX 0 0 0/10/1 0/1 0/1 on 0/1 M69650 0 0 0 0 1 1 1 SIMPLEX-DIAGNOSTIC 0 0/1 0 0 0/1 0 0 .SIMPLEX-UPDATE 0 0/1 0 0 1/0 1 1 SIMPLH-UPDATE-DIAG.

1 1 1 0 0 1 1 0 0 DUPLEX [/0 I/O I/O /0 I/O I/O MEG-ED I I I I I I I SIMPL EX I I I I 0 0 0 SIMPLE X-DIA GHOST/C l/O I I I/O I I SIMPLEX-UPDATE I/O I I 0/ I O O SIMPLEX-UPDA TE-DIA G Is BUS CONTROLS MID Rzsuuma counaunnnous PATENTED RUB 5 974 SHEET 1 0f 23 FIG: 24

IS BUS CONTROL LEVEL EQUATIONS DEFINITION OF TERMS:

U-CWO DCPAL DCCAF s|sBL SISBIL RISBL RISBIL xEc XECN

SISB L RISBOL SISBIL RISBH.

ISCBF BUS cONTROL FLIP-FLOP OUTPUT ISBBF BUS CONTROL FLIP-FLOP OUTPUT ISTBF BUS cONTROL FLIP-FLOP OUTPUT ISDBF BUS CONTROL FLIP-FLOP OUTPUT DIAGNOST|C CP ACTIViTY LEVEL (DCPAL CPAL v DF) DUAL CYCLE CONTROL A FLIP-FLOP (INPUT LEVEL FROM FCC) sENO |s* BUS O LEVEL SEND 1s* BUS 1 LEVEL RECEIVE |s* BUS O LEVEL RECEIVE 15* BUS 1 LEVEL EXECUTE INSTRUCTION ExEcuTE NON MEMORY INSTRUCTION PATENTEB AUG 51974 SHEET 17 8f 23 kmqoibu SEE Q 1 xQQQ hm mt 312G mH mam Q mam L mam mm x QQEEM MMGI as New

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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3967250 *Feb 6, 1975Jun 29, 1976Kokusai Denshin Denwa Kabushiki KaishaControl system of an electronic exchange
US3996567 *Apr 16, 1975Dec 7, 1976Telefonaktiebolaget L M EricssonApparatus for indicating abnormal program execution in a process controlling computer operating in real time on different priority levels
US4014005 *Jan 5, 1976Mar 22, 1977International Business Machines CorporationConfiguration and control unit for a heterogeneous multi-system
US4023142 *Apr 14, 1975May 10, 1977International Business Machines CorporationCommon diagnostic bus for computer systems to enable testing concurrently with normal system operation
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US7822492Oct 19, 2007Oct 26, 2010Ge Intelligent PlatformsMethods and systems for operating an automated system using a process definition model
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Classifications
U.S. Classification714/10, 714/E11.71
International ClassificationH04Q3/545, G06F11/20
Cooperative ClassificationG06F11/20, H04Q3/54558
European ClassificationG06F11/20, H04Q3/545M2
Legal Events
DateCodeEventDescription
Feb 28, 1989ASAssignment
Owner name: AG COMMUNICATION SYSTEMS CORPORATION, 2500 W. UTOP
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:GTE COMMUNICATION SYSTEMS CORPORATION;REEL/FRAME:005060/0501
Effective date: 19881228