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Publication numberUS3842702 A
Publication typeGrant
Publication dateOct 22, 1974
Filing dateJun 1, 1973
Priority dateJun 3, 1972
Also published asCA976786A1, DE2328851A1, DE2328851B2
Publication numberUS 3842702 A, US 3842702A, US-A-3842702, US3842702 A, US3842702A
InventorsM Tsundoo
Original AssigneeMatsushita Electric Ind Co Ltd
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Electronic musical instrument with variable frequency division
US 3842702 A
Images(8)
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Description  (OCR text may contain errors)

United States Patent 1191 Tsundoo Oct. 22, 1974 ELECTRONIC MUSICAL INSTRUMENT 3,764,721 10/1973 Maynard s t/1.24 WITH VARIABLE FREQUENCY DIVISION 3,801,72! 4/1974 Bunger 84/l.24 X.

[75] Inventor: Masahiko Tsundoo, Osaka-fu, Japan FQREIGN PATENTS 0R APPLICATIONS 3] Assigneez Matsushita Electric Industrial Co. 496,068 9/1950 Belgium 84/l.0l Ltd., Osaka, Japan P E R h d B w lk rtmary xamzner- 10 at 1 mson [22] June 1973 Assistant Examiner-Stanley J. Witkowski [21] App], No,; 366,020 Attorney, Agent, or FirmWenderoth, Lind & Ponack [30] Foreign Application Priority Data [57] ABSTRACT June 3,- 1972 Japan 47-55303 An electronic musical instrument includes a high frequency generator for generating a high frequency [52] [1.8. CI. 84/l.0l, 84/DIG. l1 pulse signal, an encoder for generating logic code [51] Int. Cl. Gl0h 5/06 units corresponding to a tone of a musical scale in re- [58] Field of Search 84/ 1.01, 1.03, 1.23, DIG. ll, sponse to an input musical-scale-control signal applied 84/ 1.22, 1.24 to an input terminal thereof, a variable divider for dividing the frequency of the high frequency pulse signal [56] References Cited generated by the high frequency generator by an in- UNITED STATES PATENTS terger determined by the logic code units applied to 3 236 931 2H9 Freeman 8 4 ll 23 the program terminals thereof, and a memory means 3:590:131 6/1971 Re ers.II II:I:I: 84/l:03 9 memorizing the fnuslcal'scale'comml F 3,6015; 8/1971 Hi" 84mm s1gnal essent1ally equ1valent to the log1c code wh1ch 1s 3,683,096 8/1972 Peterson et al... 84/1.03 X applied to the program terminals of the variable di- 3,696,201 10/1972 Arsem et al. 84/1.0l vider. The signal memorized in the memory is retained 3,743,755 7/ I973 Watson 84/ 1.01 even after the musical-scale-control signal ceases until 3,743,756 7/1973 FI'HI'ISSCII El al 84/l.0l a ucceeding musical control signal is generated 3,760,088 9/1973 Nakada 84/l.03 3,763,305 10/1973 Nakada et al 84/l.03 7 Claims, 11 Drawing Figures C? /6 K /4 f0 O J 32 5 0: 5 g O t!) H1 [11 LU g E Z ENCODER 7 0 gm 6 g l 21 2 x O 2 V P1 Q 1 2 N 3 GATE 9 MEANS W MEMORY EANS M TONE filo ll l2 FILTER MEANS I S PAIENTEB 01.12219 v sum or .8

WGEIQSE mIF OP oom OQNN FATENltuflmzzim 3.842.702

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285 284 I52 TO. RESET TERMINALS R UP THE FLIP- W I T f FROM OUTPUTS OF FLOP CIRCUITS THE FL: FLOP TO 132 282 283 CIRCUITS 121 T0132 ELECTRONIC MUSICAL- INSTRUMENT WITH VARIABLE FREQUENCY DIVISION BACKGROUND OF THE INVENTION This invention relates to an electronic musical instrument, and more particularly to an electronic musical instrument which is capable of producing a tone signal by controlling the dividing factor of a variable divider in accordance with a memorized logic code.

As a result of developments-in digital IC (integrated circuits), there can be produced a variable divider such as a Shift-Register-Counter (Linear-Shift-Register, Maximal-Length-Generator, Maximal-Sequence- Generator, Programmable-Divider or Modulo-N Divider) which is extremely small and available at low cost.

In a conventional electronic musical instrument, a frequency dividing IC device is used which divides an input high frequency, e.g. several mega-hertz, by 12 different factors which are integers so as to generate l2 tone signals of a musical scale in the frequency region of a master oscillator. The dividing factors of such an IC device are fixed andunchangeable.

A tone generator, the dividing factor of which is changeable and .programmable, has been used in the prior art together with a Shift-Register-Counter. In a musical instrument using such a conventional tone generator, a tone signal selected and actuated is cut off soon after releasing of the key for selecting the tone signal, and therefore the tone cannot be sustained and maintained so as to produce a sustain effect and a memory effect.

An electronic musical instrument has been developed, a so called Synthesizer" which can maintain or sustain a selected tone signal. Such a synthesizer is fundamentally composed of a voltage controlled oscillator and a dc. voltage memory. The output signal of the dc. voltage memory controls the voltage controlled oscillator so as to generate a tone signal and so as to sustain the tone signal.

However, such a synthesizer has a fatal defect that the output frequency thereof is unstable and cannot be stabilized in a short time period.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a novel electronic musical instrument which is capable of producing a tone signal which is stable in frequency.

Another object of the invention is to provide a novel and improved electronic musical instrument producing a tone signal. the frequency of which can be stabilized in a very short time period.

A further object of the invention is to provide a novel and improved electronic musical instrument capable of providing a sustain effect and a memory effect by using a memory means for memorizing a signal for controlling a variable divider even after cessation of a control signal and until generation of the next control signal.

These objects are achieved by providing an electronic musical instrument according to the invention, which comprises a high frequency generator for generating a high frequency pulse signal, an encoder for generating a logic code having subsets of bits each corresponding to a tone of a musical scale, the encoder generating a subset in response to an input musicalscalecontrol signal applied to an-input terminal thereof. a variable divider for dividing the frequency of said high frequency pulse signal generated by said high lrcquency generator by an integer determined by said logic code subset applied to the 'program terminals thereof, and a memory means for memorizing said musical-scale-control signal or a signal essentially equivalent to said logic code, subset and which is applied to said program terminals of said variable divider, said signal memorized in said memory means being retained even after said musical-scale-control signal ceases until a succeeding musical-scale-control signal is generated.

BRIEF DESCRIPTION OF THE DRAWINGS Other objects, features and advantages of the invention will be made clear from the following detailed description of embodiments thereof considered together with the accompanying drawings wherein:

FIG. 1 is a schematic block diagram showing a fundamental embodiment of an electronic musical instrument according to the present invention;

FIGS. 2 to 4 are schematic block diagrams of various embodiments of an electronic musical instrument ac cording to FIG. 1;

FIG. 5 is a circuit diagram of an embodiment of con trol means and memory means used in an electronic musical instrument of the invention;

FIG. 6 is a circuit diagram of another embodiment of control means and memory means used in an electronic musical instrument of the invention;

FIG. 7 is a circuit diagram of an embodiment of an encoder used in an electronic musical instrument of the invention;

FIGS. 8 and 9 are diagrams of embodiments of circuit connections of a frequency dividing means, an envelope controlling means, a gating means and a tone filtering means of an electronic musical instrument of the invention and FIGS. 10 and 11 are circuit diagrams of reset and current detector circuits, respectively.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. I, a keyboard designated by a reference numeral 1 comprises a plurality of keys corresponding to notes of a musical scale, each of which controls a control means 2 so as to produce a musicalscale-control signal 14 corresponding to the respective tones of a musical scale. An encoder 4 responds to each of said musical-scale-control signal 14 and generates a logic code subset corresponding to the respective tone of the musical scale. Memory means 3 is coupled to said encoder and memorizes a signal essentially equivalent to said logic code subset. A variable divider 5 such as shift-register-counter, linear-shift-register, maximal-length-generator, programmable-divider or modulo-N divider, divides a high frequency pulse signal provided from a high frequency generator 6 by a factor of an integer N. The factor N is changeable and determined by said logic code subset applied to program terminals P to P of the variable divider 5.

An output tone signal f /N from the variable divider 5 is converted into sound through a gating means 9, a tone filtering means 10, an amplifier 11 and a speaker The memory means 3 may be inserted, as shown in FIG. 2, between the control means 2 and the encoder 4, so as tomemorize the musical-scale-control signal 14 and then feed it to the encoder 4. The memory means 3 may also be inserted, as shown in FIG. 3, between the encoder 4 and the variable divider 5, so as to memorize the encoded musical-scale-control signal 14 and then to feed it to the program terminals P P of the variable divider 5.

FIG. 4 shows an embodiment of an electronic musical instrument according to the present invention, in which the memory means 3 is inserted, the same as shown in FIG. 2, between the control means 2 and the encoder 4. The keyboard 1 comprises a plurality of keys, each of which corresponds to a tone of a musical scale and controls the control means 2. The control means 2 produces the respective musical-scale-control signals 14 in response to actuation of each of said keys. The memory means 3 memorizes output signals from the control means 2. The memorized signal in the memory means 3 is supplied to the encoder 4 and encoded thereby. The encoder 4 produces a logic code subset corresponding to said musical-scale-control signal 14. The logic code subset is applied to the program terminals Pm (m l, 2,3, of the variable divider 5, which can be for example, a shift-register-counter.

In the following embodiment, a shift-register-counter manufactured by National Semiconductor Corp. under the designation of DM75 20/DM352O modulo-n divider can be used as the variable divider 5. The operation and the configuration of a modulo-n divider are clear from application note AN-l7 published Oct. 1968 by National Semiconductor Corp. Therefore, a detailed description of the operation and the configuration of the variable divider 5 will be omitted in the description of the following embodiment. The shift-registercounter 5 can have the in frequency dividing factor N (N l, 2, 3, changed in response to an input signal in the logic code subset supplied to the program terminals thereof. The shift-register-counter 5 divides a high frequency pulse signal f supplied from the high frequency generator 6 by a factor N so as to produce an output tone signal having a frequency f /N. This output tone signal fi,/N is further divided by a dividing means 7 by any desired factor, for example by a factor of 2, 3, or 5, etc, and then is applied to a gate means 9. The output signal of the gate means 9 is converted into a wave form by a tone filtering means 10 so as to produce a signal which will produce a tone having a proper tone character, and then is converted into sound through an amplifier 11 and a loudspeaker 12.

An envelope control means 8 detects the actuation of any key and then produces an envelope signal which controls said gate means 9 so as to control the envelope of the output tone signal of the gate means 9. The high frequency generator 6 is modulated by a vibrato signal from a vibrato oscillator 13.

FIG. 5 shows an embodiment of the control means 2 and the memory means 3. The control means 2 is composed, for example, of a priority circuit. Keyswitches 101 to 120 are single pole, two contact switches and are controlled by the keys of the keyboard 1. The keyswitches 101 to 112 of the first octave are connected in a priority circuit in which the normally close terminal of each keyswitch is connected to the switch arm, or common terminal of the next keyswitch, as shown in FIG. 5. The keyswitches 113 to 116 of the second octave and the keyswitches 117 to 120 of the third octave are also connected in priority circuits, respectively. Normally-open terminals of the keyswitches 101 to 112 of the first octave are connected to set terminals S of Flip-Flop circuits 121 to 132 in the memory means 3. Normally-open terminals of the keyswitches 113 to 116 of the second octave are also connected, through diodes 133 to 136, to the set terminals S of Flip-Flop circuits 121 to 132, respectively. Normally-open terminals of the keyswitches 117 to 120 are also connected, through diodes 137 to 140, to the set terminals S of the Flip-Flop circuits 121 to 132, respectively. The common terminal of the keyswitch 101 is connected, through a current detector 154, to the positive terminal of a power source 360. The common terminal of the keyswitch 113 is also connected, through a control switch 157 which is normally closed and another current detector 155, to the positive terminal of the power source 360. The common terminal of the keyswitch 117 is also connected, through another control switch 158 which is normally closed and another current detector 156, to the positive terminal of the power source 360. The negative terminal of the power source 360 is connected ground.

The control switch 157 which is normally closed is opened every time the current detector 154 detects any current, and thereby cuts off the connection between the keyswitch 113 and the power source 360. The control switch 158 which is normally closed is controlled through an OR circuit 159 connected to the current detectors 154 and and is opened every time either the current detector 154 or 155' detects any current, and thereby cuts off the connection between the keyswitch 117 and the power source 360. Therefore, when two or more keyswitches are operated simultaneously the keyswitches 101 to 112 of the first octave will operate and cancel in the operation prior in the operation to the keyswitches 113 to 116 of the second octave and the keyswitches 113 to 116 of the second octave will operate prior to the keyswitches 117 to 120 of the third octave. Among the keyswitches 101 to 112 of the first octave, when two or more keyswitches are operated simultaneously, the keyswitch 101 will operate prior to any of the other keyswitches 102 to 112, and the order of the priority of operation is the order of the keyswitches from 101 to 112. Among the keyswitches 113 to 116 of the second octave, the keyswitch 113 will operate prior to any other keyswitches 114 to 116, and the order of the priority of operation is the order of keyswitches from 113 to 116. Among the keyswitches 117 to 120 of the third octave, the keyswitch 117 will operate prior to any other keyswitches 118. to 120, and the order of the priority of operation is the order of the keyswitches from 117 to 120. When two or more keyswitches among all the keyswitches 101 to 120 are operated, consequently, the keyswitch 101 will operate prior to any of the other keyswitches 102 to 120, and the order of the priority of operation is the order of the keyswitches from 101 to 120.

Referring to the memory means 3, output signals of the Flip-Flop circuits 121 to 132 for tone memory are applied to input terminals 161 to 172 of the encoder 4, and also applied to reset circuit 153 through resistors 141 to 152. The reset circuit 153 detects current or voltage applied thereto, and then generates a reset voltage when two or more Flip-Flop circuits among the Flip-Flop circuits 121 to 132 are set. The reset voltage is applied to reset terminals R'of the Flip-Flop circuits 121 to 132 so as to reset instantaneously all the Flip- Flop circuits 121 to 132. After that, only one Flip-Flop circuit is set by the corresponding keyswitch selected preferentially through the operation of the control means 2, i.e.-the priority circuit of keyswitches 101 to 120. Output signals from the current detectors 154, 155 and 156 are applied to the set terminals s of the Flip-Flop circuits 181, 182 and 183 for memorizing octave information. Signals memorized in the Flip-Flop circuits 181 to 183 for octave information memory are applied to an input terminal of another reset circuit 184 through respective resistors 186, 187 and 188. The

reset circuit 184 detects current or voltage applied thereto, and then generates a reset voltage when two or three Flip-Flop circuits among the Flip-Flop circuits 181, 182 and 183 are set. The reset voltage is applied to the reset terminals R of the Flip-Flop circuits 181 to 183 so as to reset instantaneously all the Flip-F lop circuits 181 to 183. After that, only one Flip-Flop circuit is set by a signal from a corresponding current detector 154, 155 or 156 through which current is preferentially flowing. Thus, the Flip-Flop circuits 181 to 183 for octave memory memorize which octave selected among the first, second and third octaves has beenselected after the selected keyswitch returns to the initial position.

The reset circuits 153 and 184 are composed of, for example, a dc. amplifier which responds to a current or a voltage larger than a threshold value and produces a step voltage which is able to drive all the reset terminals. FIG. shows an example of the reset circuit 153, which comprises two transistors 28] and 212 and three resistors 283, 284 and 285. The base of the transistor 281 is connected to a negative bias voltage source "V through the resistor 283 and is also connected to the outputs of the Flip-Flop circuits 121 to 132 through resistors 141 to 152. The collector of the transistor 281 is connected to the base of the transistor 282 and also is connected to a positive voltage source +V through the resistor 284. The emitter of the transistor 282 is connected to ground. The collector of the transistor 282 is connected to the reset terminals R of the Flip- Flop circuits 121 to 132 and is also connected to the positive voltage source V through the resistor 285. The emitter of the transistor 281 is also connected to ground. When one or none of the Flip-Flop circuits 121 to 132 is set in the state for memorizing a signal, the potential of the base of the transistor 281 is lower than that of the emitter of the transistor 281. Therefore, the transistor 281 is cut off and the transistor 282 is saturated. Accordingly, no reset voltage appears at the collector of the transistor 282. On the other hand, when two or more of the Flip-Flop circuits 121 to 132 are set in the state for memorizing a signal, the potential of the base of the transistor 281 becomes higher than that of the emitter of the transistor 281. Therefore, the transistor 281 becomes saturated and the transistor 282 is cut off. Accordingly, a positive reset voltage is generated at the collector of the transistor 282 so as to reset instantaneously the Flip-Flop circuits among circuits 121 I to 132 which are set.

The reset circuit 184 has the same configuration and operation as the reset circuit 153. The description of the reset circuit 184 is therefore omitted.

FIG. 6 shows another embodiment of the control means 2 and the memory means 3, in which the elements designated by the same numbers as those of FIG. 5 have the same functions as the elements of FIG. 5. The control means 2 is also composed of a priority circuit similar to that of FIG. 5. The description of the memory means 3 is omitted because the memory means 3 of FIG. 6 is the same as that of FIG. 5.

In the following, there will be described the structure and operation of the priority circuit of the control means 2. Keyswitches 201 to 220 are normally open single pole, single contact type switches and are controlled by keys corresponding to a musical scale on the keyboard 1. The normally-open terminals of the keyswitches 201 to 212 of the first octave are connected to a common conductor 174 which is connected, through the current detector 154, to the positive terminal of the power source 160. The normally-open terminals of the keyswitches 213 to 216 of the second octave are connected to a common conductor 175 which is connected to the positive terminal of the power source 260 through the control switch 157 and the current detector 155. The normally-open terminals 'of keyswitches the 217 to 220 of the third octave are connected to a common conductor 176 which is connected to ground through the control switch 158 and the current detector 156. The power sources 160 and 260 are connected in series in such a way that the positive terminal of the power source 260 is connected to the negative terminal of the power source 160 and the negative terminal of the power source 260 is connected to ground.

The control switch 157, which is normally closed, is opened every time the current detector 154 detects any current, and thereby cuts off the connection between the common conductor and the positive terminal of the power source 260. The control switch 158, which is normally closed, is controlled through an OR circuit 159 connected to current detectors 154 and 159 and is opened every time either the current detector 154 or 155 detects any current, and thereby cuts off the connection between the common conductor 176 and ground. Therefore, when two or more keyswitches are actuated the keyswitches 201 to 212 of the first octave are operated prior to the keyswitches 213 to 216 of the second octave and the keyswitches 213 to 216 of the second octave are operated prior to the keyswitches 217 to 220 of the third octave.

The movable contacts of the keyswitches 201 to 212 of the first octave are connected to the emitters of transistors 221 to 232, respectively. The collectors of the transistor 221 to 232 are connected to the set terminals 5 of the Flip-Flop circuits 121 to 132. Resistors 241 to 252 are connected between the bases and the collectors of the transistor 221 to 232, respectively. Each of these resistors 241 to 252 has the same resistance value r. Resistors 261 to 272 are connected in series and connected between the base of the transistor 232 and the negative terminal of a power source 360. The positive terminal of the power source 360 is connected to ground. Junction points between adjacent resistors in the series of resistors 261 to 272 are connected to the bases of the transistors 221 to 231, respectively. Each of these resistors 261 to 272 has the same resistance R which is equal to or higher than the resistance r. The movable contacts of the keyswitches 213 to 216 of the second octave are connected to the emitters of the transistors 221 to 232 through diodes 133 to 136, re-

spectively. The movable contacts of the keyswitches 217 to 220 of the third octave are connected to the emitters of the transistors 221 to 232 through diodes 137 to 140, respectively. The transistors 221 to 232 are all cut off when all the keyswitches 201 to 220 is opened because there are no current flow between bases and emitters of the transistors 221 to 232.

When any keyswitch among the keyswitches 201 to 220 is closed, the corresponding transistor is switced on so as to set the corresponding Flip-Flop circuit. When two or more keyswitches among the keyswitches 201 to 212 of the first octave are closed, a current flows through only one transistor'which corresponds to the keyswitch nearest to the power source 360 among the keyswitches closed simultaneously, so that only one transistor is switched on and then the corresponding Flip-Flop is set in a state in which the closing of the corresponding keyswitch is memorized. The operation is the same the for the keyswitches 213 to 216 of second octave and also for the keyswitches 217 to 220 of third octave. Among the keyswitches 201 to 212 of the first octave, the keyswitch 201 is operative prior to any other keyswitches 202 to 212, and the order of the priority of operation is the order of keyswitches from 201 to 212. Among the keyswitches 213 to 216 of the second octave, the keyswitch 213 is operative prior to any other keyswitches 214 to 216, and the order of the priority of operation is the order of the keyswitches from 213 to 216. Among the keyswitches 217 to 220 of the third octave, the keyswitch 217 is operative prior to any other keyswitches 218 to 220, and the order of the priority of operation is the order of the keyswitches from 217 to 220. As described before, the order of the priority of operation among the three octaves is the first, second and third octaves. Consequently, the keyswitch 201 is operative prior to any other keyswitches 202 to 220, and the order of the priority of operation is the order of keyswitches from 201 to 220.

The current detectors 154, 155 or 156 and the normally closed control switches 157 and 158 are composed of transistor switch circuits as shown in FIG. 11. The current detector 154, 155 or 156 comprises a transistor 191, a base resistor 192 and a collector resistor 193. The emitter of the transistor 191 is connected to an output terminal 196. The base'of the transistor 191 is connected to a bias terminal 198 through the base resistor 192. The collector of the transistor 191 is connected to the bias terminal 198 through the collector resistor 193 and is also connected to a control output terminal 199.

The normally closed control switch 157 or 158 comprises a transistor 194 and a base resistor 195 which is connected between the base and the collector of the transistor 194. The collector of the transistor 194 is connected to an input terminal 197. The emitter of the transistor 194 is connected to an output terminal 190. The base of the transistor 194 is connected to a control input terminal 189.

The bias terminals 198 of the current detector 154, 155 and 156 are connected to the positive terminal of the power source 360 in case of FIG. 5, and are'connected to the positive terminals of the power source 160 and 260 and to ground, respectively, in case of FIG. 6.

control switch 157 and connected, through the OR gate 159, to the control input terminal 189 of the further control switch 158. The control output terminal 199 of the current detector 155 is connected to the conductor 200 and also connected, through the OR gate 159, to the control input terminal 189 of the control switch 158. The control output terminal 199 of the current detector 156 is connected to the conductor 300. The output terminal 196 of the current detectors 155 and 156 are connected to the input terminals 197 of the corresponding control switches 157 and 158 respectively. The output terminal 196 of the current detector 154 is connected to the common terminal of the keyswitch 101 in case of FIG. 5 or to the common conductor 174 in case of FIG. 6. The output terminal 190 of the control switches 157 and 158 are connected to the common terminal of the keyswitches 113 and 117, respectively, in case of FIG. 5 and are connected to the common conductors 175 and 176 respectively in case of FIG. 6.

In the following, there will be described the operation of the current detector 154 and the control switch 157 of FIG. 11 which are used in case of FIG. 6. When any one of the keyswitches 213 to 216 is closed, the output terminal 190 is provided with a large negative voltage from the power source 360, so that a current flows from the input terminal 198 to the output terminal 190 The control output terminal 199 of the current detector 154 is connected to the conductor 100. It is also connected to the control input terminal 189 of the next through the transistors 191 and 194 and as the transistors 191 and l94are saturated or switched on, the output voltage of the control output terminal 199 becomes negative and approximately equal to the negative voltage of the output terminal 190. The negative output voltage of the control output terminal 199 is fed, through the OR gate 159, to the control input terminal 189 of the next control switch 158, and thereby the control switch 158 is switched off. As the operations of the current detector 154 and 155 and the control switch 158 are the same as those of the current detector 155 and the control switch 157, description thereof is omitted.

The current detectors 154, 155 and 156 and the con- .trol switches 157 and 158 may be electromechanical relays. As these electromechanical relays can be substituted easily for the current detectors 154, 155 and 156 and the control switches 157 and 158 described above, a detailed description there-of is omitted.

FIG. 7 shows an embodiment of the encoder 4 in relation to the shift-register-counter 5, the high frequency generator 6 and the vibrato oscillator 13. The shift-register-counter 5 utilizes, for example, three modulo-n dividers DM7520/8520. Such shift-registercounter 5 has 12 program terminals P to P and can divide input frequency by a factor from 2 to 4094. The output signals of the memory means are supplied to the input terminals 161 to 172 of the encoder 4 so as to be encoded through diode matrix 14. The encoded output signals, ie the subset of bits of the logic code of the diode matrix 14 are supplied to the program terminals P, to P of the shift-register-counter 5 to set the divid ing factor N. An output pulse signal of the high frequency generator 6 is applied to the input terminal of the shift-register-counter 5. The signal from the high frequency generator 6 is modulated with respect to its frequency by the vibrato oscillator 13 which generates a vibrato frequency in the sub-audio range.

There will now be considered the case where the frequency f of the output pulse signal from the high frequency-generator 6 is 7.744 MHz and the program terminals P, to P of the shift-register-counter 5 are sup plied with the input logic code subset as shown in Table 1 when the respective Flip-Flop circuits 121 to 132 are set as the corresponding keys on the keyboard arc actuated. Dividing factor N for the shift register counter 5 is set by a respective code subset to be, for example, 1850, 1960, 2077, 2200, 2331, 2470, 2616, 2772, 2937, 3111, 3296 or 3492 respectively as shown in Table 1. Thus, the shift register counter 5 divides the input frequency f =7.744 MHz by the respective dividing factor N and generates to output tone signal f lN having a frequency 4185.946, 3951.020, 3728.455, 3520.000, 3322.179, 3135.223, 2960.245, 2793.651, 2636.704, 2489.232, 2349.515 or 2217.640Hz for the respective dividing factors. These output tone signals correspond to tones C, B, A ,A, G ,G, F" F, E, D ,D and C of a tempered scale, respectively. Because the memory means 3 effectively memorizes these logic code subsets applied to the program terminals P, to P the dividing factor N continues to be set in the shift register counter units thestate of the memory means 3 is changed by changing the selection of the keyswitches. Therefore, the output tone signal f /N continues to be generated at the output of the shift register counter even after the corresponding keyswitch is opened until another keyswitch is closed. The output tone signal fl,/N is supplied continuously to the dividers 7 in the next stage until the state of the memory means 3 is changed. The memory means 3 may be inserted between the encoder 4 and the shift-register counter 5 while still providing essentially equivalent operation as that described in connection with FIG. 7.

are closed stop operation of the frequency dividers 15 and 16 by bypassing input tone signals to the outputs, respectively. When any of the keyswitches 117 to 120 or 217 to 220 of the third octave is closed, a memorized control signal for the third octave is supplied, through the conductor 300', to the Flip-Flop 183 for third octave memory, and from there through the conductor 300' and an OR-gate 28, to the switch 27. Thus, the switches 26 and 27 which are normally open are closed and the frequency dividers 15 and 16 are bypassed. Consequently, output tone signals f /2N, f /4N and f /8N are produced at the outputs of the frequency dividers 17, 18 and 19, respectively.

When any of the keyswitches 113 to 116 or 213 to 216 of the second octave is closed, a memorized control signal for the second octave is supplied through the conductor 200, Flip-Flop 182 and conductor 200 to the OR-gate 28 and to the switch 27 and the switch 27 is closed and the frequency divider 16 is bypassed. Consequently, output tone signals J's/4N. fu/8N and f /l6N are produced at the outputs of the frequency dividers 17, 18 and 19, respectively.

When any of the keyswitches 101 to 112 or 201 to 212 of the first octave is closed, the frequency dividers l5 and 16 operate normally, because the switches 26 and 27 are maintained in the opened state. Consequently, output-tone signals fi,/8N, f /16N and fl,/32N

are produced at the outputs of the frequency dividers 17, 18 and 19, respectively.

The envelope control means 8 is, for example, composed of an OR-gate 321, a diode 29, resistors 30, 31 and 34, a capacitor 32 and a transistor 33 all connected as shown in FIG. 8. When any keyswitch of the first,

Table 1 LOGIC CODES APPLIED TO PROGRAM TERMINALS N l P2 P11 l PT PM P11 1|) 11 P12 C 1850 4185.946 H- 0 0 1 0 1 1 1 1 0 l 1 l B 1960 3951.020 do. 1 0 1 1 0 0 0 l O 0 0 1 A 2077 3728.455 do. 1 0 1 0 0 0 0 0 l l O 0 A 2200 3520.000 do. 1 1 1 1 1 0 0 l 0 0 0 l G 2331 3322.179 do. 1 l 1 0 l 0 l l 0 0 0 0 G 2470 3135.223 do. 0 l l 0 1 0 l 0 l 0 1 1 F 2616 2960.245 do. 0 1 1 l 1 1 0 0 1 0 0 0 F 2772 2793.651 do. 0 l 0 1 0 0 1 0 l 0 l 1 E 2937 2636.704 do. 1 0 1 l 1 0 1 0 0 l O 0 D 3111 2489.232 do. 0 0 0 0 0 O 0 l 1 0 1 1 D 3296 2349.515 do. 1 1 0 0 1 1 l O 0 0 0 1 C 3492 2217.640 do. 1 0 1 0 1 l 1 0 0 l l 0 FIG. 8 shows 'an embodiment of the dividing means second and third octave is closed, the capacitor 32 is 7, the envelope control means 8, the gate means 9 and the tone filtering means 10. The output tone signal f /N from the shift-register-counter 5 is supplied tothe dividing means 7 in which the frequency of the tone signal fi,/N is divided by a factor 2 in turn through frequency dividers 17, 18 and 19. The output signals from thefrequency dividers 17, 18 and 19 are supplied to gates 20, 21 and 22 of the gate means 9 which is controlled by an output signal from the envelope controlling means 8 through a conductor 500. The outputs of the gates 20, 21 and 22 are supplied to tone filters 23, 24 and 25 of the tone filtering means 10 which converts the waveform of the tone signals. The output signals of the tone filtering means are supplied to the amplifier 11 of the next stage.

Normally open switches 26 and 27 are connected between the inputs and the outputs of the frequency dividers 15 and 16, respectively. The switches 26 and 27 charged with octave control voltage directly from the current detectors 154-156, through the resistor 31, the diode 29, OR gate 321 and the conductor 100, 200 or 300. In this case, the transistor 33 is cut off because no reset pulse is applied from reset circuit 153 and/or 184 to the base thereof through an OR-gate 35 and conductors 400' and/or 400. After the keyswitch which is closed is opened, the octave control voltage disappears and then the charge across the capacitor 32 is gradually discharged through the resistors 30 and 31.

Every time the memory state of the memory means' charged through the collector-emitter of the transistor- 33 at the moment when the reset pulse is applied. After that, the capacitor 32 can be charged by another octave control voltage.

An envelope control signal generated across the capacitor 32 is supplied to the gates 20, -21 and 22 of the gate means 9 through the conductor 500 so as to control the envelope of output signals from these gates 20, 21 and 22. if the resistance of the resistors 30 and 31 is variable, the decay (or sustain) time and/or the rise (or attack) time can be changed in accordance with the players desires. When the resistor 30 is removed or the resistance of the resistor 30 is infinite, then the charge across the capacitor 32 remains even after the octave control voltage disappears, and in effect is memorized until a reset pulse is applied to the base of the transistor 33. In this case, output tone signal is memorized or maintained after the selected keyswitch is opened until the next keyswitch is closed.

The octave control voltages memorized in the memory means 3 are applied to the tone filters 23, 24 and 25 of the tone filtering means through the conductors 100', 200' and 300' and through the conductors 501, 502 and 503, respectively, and control the frequency-response characteristics of the tone filters 23, 24 and 25 so as to fit them to the octave selected in the frequency-response characteristics.

FIG. 9 shows another embodiment of the dividing means 7, the gate means 9 and the tone filtering means 10. The output tone signal f /N of, the shift-registercounter 5 'is supplied to the dividing means 7 in which the frequency of the tone signal f /N is divided successively in each of the frequency dividers to 19 by a factor 2 so as to generate output signals f 2N f /4N, f,,/8N,fl,/16Nandf,,/32N. These output signals are supplied to gates 45 to 49 of the gate means 9, respectively. The output signals of the gates 45 to 49 are surpplied to tone filters 60 to 64, respectively. The output signals of the tone filters 60 to 64 are surpplied to the amplifier 11. The envelope control voltage is is surpplied to switches 54, 55 and 56, which are opened normally, open, from the envelope control means 8 through the conductor 500.

When any of the keyswitches 101 to 112 or 207 to 212 of the first octave is selected, a memorized control signal for the first octave is supplied to the switch 56 from Flip-Flop circuit 181 through the conductors 100' and 501 for the first octave memory, so as to close the switch 56. Then, the envelope control signal is applied 'to the gates 49, 48 and 47 from the envelope control means 8, through the thus closed switch 56 and/or further through diodes 69 and 68 so as to control the envelope of the output signals of the gates 49, 48 and 47.

When any of the keyswitches 113 to 116 or 213 to 216 of the second octave is selected, a memorized control signal for the' second octave is supplied to the switch 55 from Flip-Flop circuit 182 through the conductors 200' and 502 for the second octave memory, so as to close the switch 55. Then, the envelope control signal is supplied to the gates 48, 47 and 46 from the envelope control means 8 through the thus closed switch 55 and further through diodes 53, 67 and 66 so as to control the envelope of the output signals of the gates 48, 47 and 46.

When any of the keyswitches 117 to 120 or 217 to 220 of the third octave is selected, a memorized control signal for the third octave is supplied to the switch 54 from F lip-F lop circuit 183 through the conductors 300' and 503 for the third octave memory, so as to close the switch 54. Then, the envelope control signal is supplied to the gates 47, 46 and 45 from the'envelope control means 8 through the switch 54 and further through diodes 52 and 51, so as to control the envelope of the output signals of the gates 47, 46 and 45.

As described hereinbefore, the electronic musical instrument of the present invention, sustain effect and memory effect can be provided, because the input logic codes to the program terminals of the shift-register-counter 5 are effectively memorized by the memory means 2 even after the finger released from any key, in

other words after opening any keyswitch, until the next key is depressed in other words, until the next keyswitch is closed.

It is further advantageous in that the envelope of the output tone signals can be controlled so as to have various kinds of attack and decay envelope waveform by using the envelope control means 8 in the electronic musical instrument of the present invention.

It is further advantageous in that the frequencies of output tone signals are quite accurate and stable because of the use of only one accurate and'stable high frequency generator 6.

A further advantage is that an electronic musical instrument according to the invention can easily be constructed of ICS, MSls and/or LSls because almost all the systems of the invention can make use of a digital system.

While particular embodiment of the invention is described hereinbefore, it will be apparent that various modifications can be made in the form and construction thereof without departing from the fundamental principles of the invention. it is, therefore, desired by the following claims, to include within the scope of the present invention all similar and modified forms of the apparatus disclosed, and by which the results ofthe invention can be obtained.

What is claimed is:

1. An electronic musical instrument with variable frequency division, comprising:

a high frequency generator for generating high frequency pulse signal;

a variable divider coupled to said generator for dividing the frequency of said high frequency pulse signal generated by said generator by one of a plurality integral number factors according to one of a plurality of logic code subsets containing a plurality of bits applied to program terminals thereof, said logic code subsets corresponding to said number factors for producing tone signals corresponding to tones of a musical scale;

an encoder coupled to said variable divider for generating said logic code and supplying a logic code subset to the program terminals of said variable divider;

control means coupled to said encoder for supplying to said encoder an input musical-scale-control signal for causing said encloder to generate a logic code subset corresponding to the control signal; and

a memory means coupled to said encoder for memorizing the logic code subset which is supplied to said program terminals of said variable divider so as to cause said variable divider to continue to produce a tone signal in response to said musicalscale-control signal, even after said musical-scalecontrol signal ceases and until a succeeding musical-scale-control signal is supplied.

2. An electronic musical instrument as claimed in claim 1, wherein said memory means is coupled between said encoder and said variable divider.

3. An electronic musical instrument as claimed in claim 1, wherein said memory means is coupled between said encoder and said control means.

4. An electronic musical instrument as claimed in claim 1, wherein said control means comprises a keyboard for controlling generation of said musical scale control signals.

5. An electronic musical instrument as claimed in claim 4, wherein said control means further comprises a priority selector circuit for producing a musical-scalecontrol signal corresponding to the key which at the extremity among keys of the keyboard which are depressed simultaneously.

6. An electronic musical instrument as claimed in claim I, wherein said instrument further comprises gate means coupled to said variable divider for gating the output tone signal thereof, tone filtering means coupled to said gate means for filtering the output tone signal thereof, and envelope control means coupled to said gate means for controlling amplitude envelope of the output signal of said gate means, said envelope control means being coupled to said control means and to said memory means and being operated in response to said musical-scale-control signals and also to operation of said memory means.

7. An electronic musical instrument as claimed in claim 6, wherein said envelope control means includes tone characteristic control elements for controlling the characteristics of said tone filters.

' 2350A" I a STATES PATENT OFFICE CERTIFICATE OF CORRECTION m 5; 4 ,70 Dated October 22, 1974 Inventdfls) MASAHIKO TSITNOO- It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

v In the heading under "United States Patent" "Tsuz ido o" should read Tsun'o0---.

I Line [75] 'Tsundoo" should read -Tsunoo-'.

- Signed and sealed this 24th day of December 1974.

(SEAL). Attest: I

MCCOY GIBSON JR. c; MARSHALL DANN Attest pg Officer Commissioner of Patents T222530 UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION .Pateht 3,842,702 g October 22, 1974 Invent flsi MASAHIKO TSUNOO- vIt is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

In the heading under "United States Patent" "Tsundoo" shOul-d read Tsunoo---. I

I Line [75] Ts undoo" Sh 01116. read -Tsunoo--'.

. Signed and. seal ed this 24th day of December 1974.

(SEAL) Attest: r rccoy GIBSON JR. c; MARSHALL DANN Attest ng Officer Comis sioner of Patents I

Referenced by
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Classifications
U.S. Classification84/648, 84/662, 84/DIG.110, 984/381, 84/663, 84/661
International ClassificationH03K23/66, G10H5/00, G10H1/22, G10H5/06
Cooperative ClassificationH03K23/665, Y10S84/11, G10H5/06
European ClassificationH03K23/66P, G10H5/06