US3846625A

US3846625A - Computing device for an interpolation

Info

Publication number: US3846625A
Application number: US00334401A
Authority: US
Inventors: T Sasayama
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 1972-02-21
Filing date: 1973-02-21
Publication date: 1974-11-05
Anticipated expiration: 1991-11-05
Also published as: JPS549257B2; DE2308562C3; GB1413045A; JPS4885927A; DE2308562A1; DE2308562B2

Abstract

A computing device for interpolation of values which is suitable for controlling operation of a car engine includes a digital memory for memorizing the data of selected independent variations of engine parameters and digital adder circuit for adding the value of the data corresponding to the selected variations in a certain method being determined in accordance with the order of the read-out operation of the memory. The first read-out address is a near address to the value corresponding to desired variations in a lower direction and the read-out address is scanned sequentially in the same distance to the distance between said selected variations in every direction of the variations, in order to obtain the volume dependent on the memorized values of the selected variations near to the desired variations.

Description

United States Patent 1 3,846,625 Sasayama [451 Nov. 5, 1974 1 COMPUTING DEVICE FOR AN INTERPOLATION Takao Sasayama, Hitachi, Japan Assignee: Hitachi, Ltd., Tokyo, Japan Filed: Feb. 21, 1973 Appl. N0.: 334,401

Inventor:

Foreign Application Priority Data Feb. 21, 1972 Japan 47-17210 US. Cl. 235/152, 235/150.21 Int. Cl. G061 1/02 Field of Search 235/152, 150.21, 150.2,

References Cited UNITED STATES PATENTS Ingham et al.... 235/l50.53 Leeson 235/197 Ancona 235/1521E Williams et al. 235/150.2l X Hodgson et a1 235/l50.21 X

MEMORY CONTRO.

CK T

Primary ExaminerMalcolm A. Morrison Assistant Examiner-James F. Gottman Attorney, Agent, or Firm-Craig & Antonelli [57] ABSTRACT The first read-out address is a near address to the value corresponding to desired variations in a lower direction and the read-out address is scanned sequentially in the same distance to the distance between said selected variations in every direction of the variations, in order to obtain the volume dependent on the memorized values of the selected variations near to the desired variations.

16 Claims, 8 Drawing Figures Sam w s PATENTEDMUV 51974 1 COMPUTING DEVICE FOR AN INTERPOLATION BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a computing device for interpolation and more particularly to a computing device which is suitable for determining the quantity of fuel injection or for advancing the angle of ignition of an engine.

2. Description of the Prior Art One of our most serious ecological problems results from the emission of impurious components included in exhaust gas from a car engine, the impurious components having a baneful influence upon mankind, animals and plants. As a result, it has become an ever more urgent requirement to decrease the impurious components which are issued from the exhaust gas of the engine, for example, by developing a device which is suitable for decreasing those components.

There are various difficult problems which must be solved, in order to decrease undesirable exhaust components. One problem is to determine precisely the quantity of injection fuel or the degree of advancing of the angle of ignition to produce minimum exhaust.

A computing device for calculating the quantity of fuel injection or the advancing angle of engine ignition is needed. The conventional fuel injection control system like the conventional ignition advancing control system is of the analogue type and therefore cannot de termine precisely the quantity of the fuel or the advancing angle of ignition required for efficient operation. For example, when the quantity of fuel injection is determined by the condition of the engine, the discharge characteristic of a capacitor is used as a measure and the value of the resistor forming part of the discharge circuit including the capacitor is controlled by the suction of the intake manifold so as to change the discharge time of the capacitor in response to the suction. The fuel quantity is determined in response to the discharge time. However, with this technique, the determined fuel quantity is not an accurate value which is the most suitable value to that engine condition.

Additionally, the analogue type control device, or analogue type calculating device, has a significant disadvantage. The controlled value or the calculated value is dependent upon circumferential conditions, particular temperatures, etc. For the same engine condition, the calculated value in winter is different from that in summer. Therefore, a digital type calculating device is more desirable in such cases.

In the digital type calculating device, in order to regulate the fuel quantity or the advancing ignition angle of the engine, it is required to memorize the needed data which is used for determining that quantity or the ignition angle. Namely, the memory stores the values, each value being determined by each engine condition or each value of the engine speed and the suction of the intake manifold. The engine condition is continuously measured, and the fuel quantity or the advancing angle of ignition is determined by the stored value which corresponds to that engine condition. The memory cannot memorize all values corresponding to all engine conditions and therefore the memorized value is discontinuous. The price of the memory increases in response to the volume of the memorized value. Therefore, it is necessary to develop a calculating machine for interpolation in order to decrease the cost of the device.

SUMMARY OF THE INVENTION 1. Object of the Invention The primary object of this invention is to provide an economical computing device for interpolation of values.

Another object of this invention is to provide a computing device which is suitable for determining the quantity of fuel injection or the advance angle of ignition of the engine to produce efficient operation.

A further object of this invention is to provide a computing device for interpolation of values which is independent of circumferential temperature.

2. Statement of the Invention The present invention includes an adder circuit for calculating the volume and an interpolation. The value of that volume corresponds to each value of the interpolation or each value of the fuel injection.

The present invention includes memory means for memorizing basic values which correspond to each engine condition or any other condition relating to the needed purpose. The value of the interpolation can be calculated by adding these basic values in a predetermined order.

Therefore, the computing device of the present invention is very simple and of low price.

If the basic values correspond to the engine condition, viz, engine speed, the suction of the intake manifold, the air temperature in the intake manifold, the recycle quantity of the exhaust gas, the calculated value corresponds to the value of the fuel injection quantity or the advancing angle of ignition. Therefore, the present invention is very suitable for a control device of a car engine or other engine.

The memory means and the adder means of the present invention are of the digital type so as to be independent of circumferential temperatures. If the memorized data is changed, it can be used for other purposes or as a controlling device of other kinds of car engines without any regulation. The controlling devices for various kinds of car engines are provided in one kind of continuous design and continuous manufacturing process.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a diagram of a surface of a group of values determined by independent variations x x x and yr yz y..-

FIG. 2 is a partially enlarged view of desired values of independent variations of FIG. 1.

FIG. 3 is a partially enlarged view of desired values of FIG. 1 for graphical solution of an interpolation process.

FIG. 4 is a partially enlarged view of desired values of FIG. 1 for an electrical solution of an interpolation process.

FIG. 5 is a schematic block diagram of an electrical computing device for calculating an interpolation of values.

FIG. 6 is a schematic circuit diagram of an embodiment of the control circuit of the computing device of FIG. 5.

FIG. 7 is a schematic circuit diagram of another em bodiment of the computing device for calculating an interpolation.

FIG. 8 is a schematic circuit diagram of another embodiment of the control circuit of the computing device of FIG. 7.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a needed value 2 is a function of two independent variables x and y.

z =f( y) The needed value x is obtained by an experiment or an experience and has a surface as shown in FIG. 1. Setting values on the X-coordinate and the Y- coordinate, we can find the desired value 2 on the surface. If the x value is x,, and the y value is y,,, the desired value z has the value of point P. All of the values which are determined by the two independent variables x and y are found on this surface, as shown in FIG. 1, if it is assumed that all of the conditions being determined by the independent variables x and y are tested. But in practice, it is impossible to test all of the conditions. Thus, it is necessary to select basic values of the independent variables x and y with a certain distance along the X- and Y-coordinates via, x x x,, and y,, y

The conditions dependent upon the basic values of the independent variables x and y have been tested and only the resulting values memorized. In this case, the value of point P must be obtained by calculation, since x and y are not selected values.

The calculating methodof the present invention is explained using FIGS. 2, 3, and 4. It is assumed that the distances between the selected values on the X- and Y coordinate axes are 6x and 8y, respectively. The value of P, which is the number 2, on the Z-axis obtained by dropping a perpendicular to the Z-axis from the point P, is obtained by approximation within the plane from the values z 2 z,-,- and 2 The values 2 z z,-,- and z are memorized by the memory.

The increment K of the line L,- between points Zij and z,-,- is, as seen from FIG. 1:

and the increment K of line L,- between points z and z,-,- is:

If a line L, is extended parallel to lines L, and L, and passes through the point P, it is assumed that the values of points z,-,, and z of the intersection of line L,, and lines between points z and z and between point z and points z.-,- are 2 and 2, respectively.

The increment K of line L is obtained by the increments K 1 and K as follows where a (y,I yfllfiy. The perpendicular value 2 to the Z-axis at the point Z; IS

where ,B (x,, x,)/5x. Since coefficients a, B are given by a (yp yi)/ y the distance '(y y,) and the distance (x x,-) are ypyi= y (I0 where In 'fi n (17) The following new equations (l8) to (21) are obtained by multiplying the equations (14) to (17) by a coefficient 6x'8y.

11= y'qii '1 5X Zn ii y'qu yB u (21) Referring to FIG. 3, the equations (18) to (21) represent volumes V V V;,, V

Namely, the volume V is obtained by multiplying an area defined y Points p yp), i yr) 1 yp) d i, y;) by the value 2 of point (x y;); the volume V is obtained by multiplying an area defined by point (x,,, y,-),- (x y,), A and A; by the value of point (x y,); the volume V is obtained by multiplying an area defined by points (x y,,), (A A;,), (x,, y by the value of point (x y and the volume V is obtained by multiplying an area defined by point (x,, y,), A A and A by the value of point (x y Equation (7) is given by the total of the volumes V,-,-, V,,-, V,, and V But in reality, the equation (7) is given by the value which is obtained by dividing the total of the volumes by the area defined by 8x'8y. Since the certain area 6x'8y is multiplied by any point as a coefficient, the coefficient is taken into account by regulating the memorized value. The calculating method of the total of the volumes is determined in an electrical way.

Referring to FIG. 4, the values of points (x,-, y,-), (x,, y,), (x;, y,), (x,, y,-) are memorized in a memory means. Namely, the selected values of independent variations x x x,, and y,, y y correspond to the addresses of the memory means. The distance between two selected values of independent variations x and y are also divided into the many increments Ax Ax Ax and Ay Ay Ay,,. When the independent variations x and y are the values x,, and y,,, at first the value of point (x,, y,) is read out from the memory and the read out point is scanned from the first position of point p(x,,, y,,) to a point A, or a point A through a small area defined by Ax,, Ax Ax,,, Ay Ay Ay,,. When the read out point is located at a small area (Ax Ay the value of point (x,-, y,) is added by the adder means and when the read out point is shifted to the next small area (Ax Ay the value of point (x;, y,) is also added. When the read out point goes over the point (x-,,, y,-), the value of the point (x,-, y;) is read out and then the value of point (x,-, y,) is added by the adder means. When the read out point p is located at any small area in the domain of points (x,,, y,,), (x,,, y,-), (x,, y,-) and (x,-, y,,), the memorized value of the address corresponding to point (x,, y,) is read out; when the read out point is located at any small area in the domain of points (x,,, y (x,, y;), A and A the memorized value of the address corresponding to point (x,, y is read out; when the read out point is located at any small area in the domain of points (x x A A and (x,, y,), the memorized value of the address corresponding to point (x,-, y,) is read out; and when the read out point is located at any small area in the domain of points A A A (x y,-), the memorized value of the address corresponding to point (.r y,) is read out.

Referring to FIG. 5 the independent variations, for example, the rotational speed of the car engine and the suction value of an intake manifold, are converted to digital signals by

sensors

1, 2 and are set in counters 10, 11 through AND

gates

3, 4 and OR

gates

5, 6, the operation of said AND

gates

3, 4 is controlled by signals from a terminal T of a control circuit 7.

The independent variations (x,,, y,,) being set into said counters 10, ll designate point (x,,, y,,) of FIG. 4. The counters and 11 consist of an upper counter and a lower counter. The outputs of the upper counters are used for selecting an address of a memory 12 having two selecting input terminals T and T The lower outputs of counters l0 and 11 count a small divided increment Ax Ax Ax Ay1.Ay Ay,. between the selected variation x x x,,, y,, y y,,. Therefore, the address corresponding to point (x,, y;) is selected by the upper counters of counters l0 and 11. The output terminal T of the control circuit 7 starts the transfer of pulses into a counter 8 and input terminal T of counter 11. When a scanning (read out) point is located at (x,,,

y,) is read out into register 13 from the memory 12.

The value z of the point (x;, y,) is applied to a terminal T of an adder circuit 14 and the value of a register 15 is also applied to a terminal 15 of the adder circuit 14. At first the value of the register 15 is zero, the value z of the point (x,-, y is stored in the register 15 as the output of the adder circuit 14. The counters 8 and 11 are advanced one count by the pulse from the terminal T of the control circuit 7, so that the scanning (read out) point is advanced to point (x,,, y The read out address of the memory is not changed because the upper counters connected to the address inputs T and T of the memory are not advanced. The same value 2 of the point (X1, y,) is read out for adding with the value in the register 15. The resulting value calculated by adder circuit 14 is stored in the register as a new value. When the scanning (read out) point is moved to a point (x,,, Ay the upper counter of the counter 11 is advanced one count by the output of the lower counter of the counter 11. As a result, the memorized value 2,; of the point (x,, y,) is read out from the memory 12 to register 13. The value z of the register 13 is added with the value of the register 15 and then stored in the register 15 as a new value. When the scanning (read out) point reaches a point (x,,, Ay,,), the counter 8 counts a full count and then it is reset and counters 9 and 10 are advanced one count. Since an output from a terminal T of a counter 9 also is applied to the terminal T of the counter 11, the counter 11 abates one count by one pulse from the control circuit 7. When the scanning point is located between the points (Ax,, Ay,,), (Ax y,,), the counter abates the count by pulses from the control circuit, since the output from the terminal T is applied to the terminal T of the counter 11. When the scanning point reaches point (Ax Ay from the point (Ax Ay the count of the upper counter of counter 11 is abated one count, and after that the address of (x,-, y,) is read out. When the scanning point reaches point (Ax,, y the counter 8 counts a full count and then the

counters

9 and 10 are advanced one count. As a result, the output from the terminal T of the counter 9 is stopped, so that the counter 11 advances again.

When the scanning point reaches the point A (x,-, Ay the upper counter of the counter 10 is advanced one count, by the next pulse from the counter 8, because the lower counter of the counter 10 is at a full count. The address of the x side is advanced one count, whereby the address corresponding to the point (.r,, y is read out. in this way the scanning point reaches the point A, and the volume indicated by the total of equations (18) to (21) is calculated.

The comparator 16 and the register 17 are shown as an auxiliary circuit. Namely, if the output of this computing device indicates the advancing angle, an instantaneous position of an engine piston is set into the re gister instantaneously. When the value in the register coincides with the value of the register 15, the comparator 16 derives an output, by which the ignition is triggered. A counter can be used instead of the register 17 in order to obtain the instantaneous position of the piston by counting pulses generated in response to the position of the piston.

If the output of this computing device indicates a quantity of injection fuel, the instantaneous injecting quantity of the fuel is obtained by counting pulses, the

generation of said pulses being started by opening the fuel injection valve. The output of the comparator is caused by coincidence of the value of the counter or register 17 and applied to a control device for the fuel injection valve so that the fuel injection is stopped.

The control circuit 7 is shown in FIG. 6 in detail. A pulse is applied to a terminal ST, or ST by another circuit or an operator for setting a flip-flop FF The output of flip-flop FF, is used for clearing the

counters

8, 9, l and 11 and the

registers

13 and 15. Next pulse from an oscillator 70 sets a flip-flop FF whereby the pulses from the oscillator 70 are applied to the counter 8 and the OR gate 6 until the output from the counter 9 is applied to an input of an AND gate 69 through the terminal T Digital signals are set into counters 10 or 10' and 11 in FIG. 7 from

sensors

1 or 1' and 2, respectively. When an output from the terminal T of the control circuit 7 is transmitted to AND

gates

3 and 3, the AND gate 3 is opened by a pulse from a terminal T of the control circuit 7, while the output of the terminal T is in the off stage, the AND gate 3' is opened by output from the terminal T Assume that the output of the terminal T is continuously transmitted. The digital signals are set in the counters 10 and 11 respectively through the AND

gates

3 and 4 and OR

gates

5 and 6. Pulses for shifting the scanning point are applied to the counter and a counter 8 from a terminal T of the control circuit 7.

In the way explained above in connection with FIG. 5, the value of the address determined by the counting values of counters l0 and 11 is transmitted to the input terminal of the adder 14 from the memory 12 through the register 13 in order to add to the value in the register 15. Namely, the adder circuit 14 accumulates the output data from the memory 12 in response to the signal of the control circuit 7. When the counter 9 is advanced to a full count, the desired calculation is completed and the calculated value is stored in the register 15. The comparators l6 and 16' and registers 17 and 17' operate in the same way as shown in FIG. 5. Counters can be also used instead of the

registers

17 and 17.

In the computing device of HG. 7, it is assumed that the sensor 1 measures the suction of the intake manifold of the engine, the sensor 1' measures the throttle opening of the engine and the sensor 2 measures the rotating speed of the engine. At first the injecting fuel quantity is calculated from the measured values of sensor l and sensor 2. In the next cycle, the advancing angle is calculated from the measured values of sensor 1 and sensor 2.

F l0. 8 shows an embodiment of the control circuit of F IG. 1. A pulse is applied to a terminal ST or ST and a flip-flop F F is set. The output of the flip-flop FF, is transmitted to set flip-flops F F, and FF and to clear the

counters

8, 9, 10, 10' and 11 and the

registers

13 and 15. The output of flip-flop FF, is transmitted to the AND

gates

3, 3, 20 and 20'. The output of the flip-flop F F is transmitted to the AND

gates

3, 3', and 4 through a terminal T The pulses of the oscillator 70 are derived from a terminal T of an AND gate 69 by setting a flip-flop FF The AND gate 69 is closed by the output from the counter 9 of FIG. 7.

The foregoing disclosure relates to the interpolation of two independent variations. If the independent variations are three or four, at first, the interpolation is caused between two independent variations of these variations in the above explained way, and the interpolation is caused between the resultant value and next variations. The desired result is obtained by repeat of this operation.

What is claimed is:

1. A computing device for interpolation of values comprising digital memory means for memorizing data corresponding to selected values (x x x,,, y,, y y,,) of variations of the values (x, y), address control means connected to said digital memory means for reading out needed data from said memory means, input means connected to said address control means for setting certain values of said variations of (x, y) into said address control means, adder circuit means connected to said memory means for accumulating said output data of said memory means, and control circuit means for controlling said input means, said address control means and said adder circuit means, whereby at first certain values along said variations being set into said address control means and then said needed data to be accumulated are read out and the read out address of said memory means is shifted continuously by operation of said address control means, wherein said address control means comprises a plurality of address counters providing counted values which define said read out address, each of said address counters providing each of said certain values of said variations (x, y) from said input means, and wherein each of said address counters has an upper counter means connected to said memory means and a lower counter means connected to said upper counter means for counting increments of (Ax Ax Ax Ay,, Ay Ayn) between each of said selected values (x,, x x,,, y y y,,) of each variation of (x, y).

2. A computing device for interpolation of values in accordance with claim 1, wherein said computing device includes second counter means for determining the shifted area of said read out address of said memory means.

3. A computing device for interpolation of values in accordance with claim 2, wherein said input means includes sensor means responsive to selected operating conditions for providing corresponding digital values representing said variations of (x, y) and gating means responsive to said control circuit means for applying said digital values to said address control means.

i 4. A computing device for interpolation of values in accordance with claim 3, wherein said adder circuit means includes an adder circuit connected to the output of said memory means and a register connected to the output of said adder circuit, the output of said register being connected back to the input of said adder circuit.

5. A computing device for interpolation of values comprising digital memory means for memorizing data corresponding to selected values of two kinds of variables (x, y), first counting means for selecting the read out address of said memory in response to a certain value y, of said first variable (y), second counting means for selecting the read out address of said memory in response to a second certain value x of said second variable (x), input means for setting said first and second certain values (x,,, y,,) into said first and second counting means, respectively, adder means for accumulating the output of said memory, third counter means for providing a signal defining the shifted distance of the read out address along said first variable (y), fourth counter means for providing a signal defining the shifted distance of the read out address along said second variable (x), and control means for providing pulse signals for operating said input means and for shifting said read out address.

6. A computing device for interpolation of values according to claim 5, wherein said first and second counting means include upper counting means and lower counting means, respectively, said upper counting means being connected to said memory means, and said lower counting means being connected to said upper counter means for counting increments between said selected values of said variations.

7. A computing device for interpolation of values according to claim 6, including means for applying pulses for shifting said read out address to said first counting means and said third counting means from said control means and the output of said third counting means is applied to said second counting means and said fourth counting means.

8. A computing device for interpolation of values in accordance with claim 7, wherein said input means includes sensor means responsive to selected operating conditions for providing corresponding digital values representing said variables of (x, y) and gating means responsive to said control circuit means for applying said digital values to said address control means.

9. A computing device for interpolation of values according to claim 5, wherein said first and second counting means include upper and lower counting means respectively, said read out address being selected in accordance with the counting values of said upper counting means, when the advance of said lower counting means for counting increments between said selected values of the variations reaches a predetermined value, the upper counting means being advanced by a unit count.

10. A computing device for interpolation of variables comprising input means for receiving the variables,

digital memory means having a plurality of storage locations designated by respective addresses for memorizing data corresponding to selected values of the variables,

address control means for selecting an address of said memory means in response to the output from said input means and for reading out needed data from the storage location designated by said selected address of the memory.

digital adder means for summing the output data from said memory means;

first counting means for counting increments of the variables between the selected values of the variables, and

control means for advancing said first counting means in synchronization with the summing timing of said digital adder means and for controlling said address control means to shift the readout address of said memory means when the counting values of the first counting means reaches the predetermined values.

11. A computing device for interpolation of variables in accordance with claim 10, wherein said address control means comprises a plurality of second counters providing counted values which define said read out address.

12. A computing device for interpolation of variables in accordance with claim 11, wherein said adder means includes an adder circuit having two inputs and summing two digital values receiving from said two input 5 means, a register for storing the output of the adder circuit and feed means for feeding the stored digital value of the register to the first input of the adder circuit, the output data from the digital memory being applied to the second input of the adder circuit.

13. A computing device for interpolation of two kinds of variables (x, y), each of said variables being divided into a plurality of selected values (x x x or y y y,,) and each of said selected values being divided into a predetermined number of increments (x x x,, or y,, y y,,), said interpolation computing device comprising digital memory means having a plurality of storage locations designated by respective addresses for memorizing data, each said address being defined by two kinds of said selected value (x x x )ryz,'-'yn), input means for providing first and second digital signals,

address control means including two counting means for receiving the first and second digital signals from said input means, each of said counting means including upper counting means and lower counting means, each unit advance of said upper and lower counting means corresponding to each selected value and each increment of the variables respectively, said upper and lower counting means being connected so that when the lower counting means is advanced to a predetermined count the upper counting means is advanced according to the counting value of the upper counting means,

adder means for accumulating the output data from said memory means in synchronization with said lower counting means, and

control means for controlling said input means, said address control means and said adder means.

14. A computing device for interpolation of variables in accordance with claim 13, wherein said computing device includes a means for determining the shifted values of each of said counting means of the address control means, whereby at first certain values of each variables from the input means being set into each of said counting means of the address control means, said counting means being shifted in synchronization with the accumulating timing of the adder means until the shifted value of the counting means reaches said determined shifted values of said shifted values determining means.

15. A computing device for interpolation of variables in accordance with claim 14, wherein said input means includes sensor means responsive to operating conditions for providing corresponding digital values representing said variables (x, y) and gating means responsive to said control means for applying said digital values to said address control means.

16. A computing device for interpolation of variables in accordance with claim 15, wherein said adder means includes an adder circuit, a register for storing the output from said adder circuit and feedback means for feeding back the output of the register to the input of the adder circuit which sums the output from the memory means and the register.

Claims

1. A computing device for interpolation of values comprising digital memory means for memorizing data corresponding to selected values (x1, x2, - - - xn, y1, y2, - - - yn) of variations of the values (x, y), address control means connected to said digital memory means for reading out needed data from said memory means, input means connected to said address control means for setting certain values of said variations of (x, y) into said address control means, adder circuit means connected to said memory means for accumulating said output data of said memory means, and control circuit means for controlling said input means, said address control means and said adder circuit means, whereby at first certain values along said variations being set into said address control means and then said needed data to be accumulated are read out and the read out address of said memory means is shifted continuously by operation of said address control means, wherein said address control means comprises a plurality of address counters providing counted values which define said read out address, each of said address counters providing each of said certain values of said variations (x, y) from said input means, and wherein each of said address counters has an upper counter means connected to said memory means and a lower counter means connected to said upper counter means for counting increments of ( Delta x1, Delta x2 - - Delta xn, Delta y1, Delta y2 - - - Delta yn) between each of said selected values (x1, x2 - - - xn, y1, y2 - - - yn) of each variation of (x, y).

4. A computing device for interpolation of values in accordance with claim 3, wherein said adder circuit means includes an adder circuit connected to the output of said memory means and a register connected to the output of said adder circuit, the output of said register being connected back to the input of said adder circuit.

5. A computing device for interpolation of values comprising digital memory means for memorizing data corresponding to selected values of two kinds of variables (x, y), first counting means for selecting the read out address of said memory in response to a certain value yp of said first variable (y), second counting means for selecting the read out address of said memory in response to a second certain value xp of said second variable (x), input meanS for setting said first and second certain values (xp, yp) into said first and second counting means, respectively, adder means for accumulating the output of said memory, third counter means for providing a signal defining the shifted distance of the read out address along said first variable (y), fourth counter means for providing a signal defining the shifted distance of the read out address along said second variable (x), and control means for providing pulse signals for operating said input means and for shifting said read out address.

10. A computing device for interpolation of variables comprising input means for receiving the variables, digital memory means having a plurality of storage locations designated by respective addresses for memorizing data corresponding to selected values of the variables, address control means for selecting an address of said memory means in response to the output from said input means and for reading out needed data from the storage location designated by said selected address of the memory. digital adder means for summing the output data from said memory means; first counting means for counting increments of the variables between the selected values of the variables, and control means for advancing said first counting means in synchronization with the summing timing of said digital adder means and for controlling said address control means to shift the readout address of said memory means when the counting values of the first counting means reaches the predetermined values.

12. A computing device for interpolation of variables in accordance with claim 11, wherein said adder means includes an adder circuit having two inputs and summing two digital values receiving from said two input means, a register for storing the output of the adder circuit and feed means for feeding the stored digital value of the register to the first input of the adder circuit, the output data from the digital memory being applied to the second input of the adder circuit.

13. A computing device for interpolation of two kinds of variables (x, y), each of said variables being divided intO a plurality of selected values (x1, x2, - - - , xn or y1, y2, - - -, yn) and each of said selected values being divided into a predetermined number of increments (x1, x2, - - - xn or y1, y2, -- - yn), said interpolation computing device comprising digital memory means having a plurality of storage locations designated by respective addresses for memorizing data, each said address being defined by two kinds of said selected value (x1, x2, - - - xn, y1, y2, - - - yn), input means for providing first and second digital signals, address control means including two counting means for receiving the first and second digital signals from said input means, each of said counting means including upper counting means and lower counting means, each unit advance of said upper and lower counting means corresponding to each selected value and each increment of the variables respectively, said upper and lower counting means being connected so that when the lower counting means is advanced to a predetermined count the upper counting means is advanced according to the counting value of the upper counting means, adder means for accumulating the output data from said memory means in synchronization with said lower counting means, and control means for controlling said input means, said address control means and said adder means.