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Publication numberUS3851212 A
Publication typeGrant
Publication dateNov 26, 1974
Filing dateJun 28, 1973
Priority dateJun 30, 1972
Also published asDE2332949A1, DE2332949B2, DE2332949C3
Publication numberUS 3851212 A, US 3851212A, US-A-3851212, US3851212 A, US3851212A
InventorsH Furuta, H Goto, H Ishizaki, T Toba, S Umeda
Original AssigneeBm Us, Fujitsu Ltd
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Plasma display panel induction preventing system
US 3851212 A
Abstract
A plasma display panel induction preventing system in which when a write or erasing pulse is impressed to a selected one of electrodes of a plasma display panel, those electrodes adjoining the selected electrode are clamped at a predetermined potential or an induced voltage canselling pulse opposite in polarity to the write or erasing pulse is impressed to the adjoining electrodes, thereby preventing undesired effects resulting from an induced voltage.
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Description  (OCR text may contain errors)

States Patent [191 Ilmea et al,

PLASMA DISPLAY PANEL INDUCTION PREVENTING SYSTEM Inventors: Shnzo Ilmeda, Kakogawa; Hiroslhi lFuruta, Akashi; 'Ieruo Tuba, Akashi; Hiroshi Goto, Akashi; IIiroyuki Ishizaki, Akashi, all of Japan Assignee: Fujitsu Limited, Kawasaki, Japan Filed: June 28, 1973 Appl. No.: 374,622

Foreign Application Priority Data June 30, i972 Japan 47-65743 US. Cl. 315/169 TV, 315/169 R Int. Cl. HOSb 37/00 Field of Search 315/169 TV, 169 R References Cited UNITED STATES PATENTS ll/l965 Sack 315/169 TV Nov. 26, 1974 3,573,542 4/l97l Mayer et al 315/169 R Primary ExaminerHerman Karl Saalbach Assistant Examiner-Lawrence J. Dahl Attorney, Agent, or Firm--Staas, Halsey & Gable [5 7] ABSTRACT A plasma display panel induction preventing system in which when a write or erasing pulse is impressed to a selected one of electrodes of a plasma display panel, those electrodes adjoining the selected electrode are clamped at a predetermined potential or an induced voltage canselling pulse opposite in polarity t0 the write or erasing pulse is impressed to the adjoining electrodes, thereby preventing undesired effects resulting from an induced voltage.

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PLAS l DISPLAY PANEL INDUCTION PREVENTING SYSTEM BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a system for preventing an induced voltage in a plasma display panel, and more particularly to a system for the prevention of undesired effects resulting from a voltage which is induced in those electrodes adjacent to a selected electrode supplied with an address signal.

2. Description of the Prior Art In a plasma display panel, an alternating sustain voltage is previously impressed to electrodes and an address voltage such as a write, erasing, read voltage or the like is impressed to a selected one of the electrodes to produce or erase a discharge spot in a discharge cell at an intersecting point of the electrodes. With the impression of such an address voltage, a voltage is induced in electrodes adjacent to the selected electrode due to the inter-electrode capacity or the like. For example, in FIG. 1, by impressing erasing pulses EX and EY shown in FIG. 2 to electrodes X3 and Y3, a voltage identified by VA is impressed to a discharge cell A at the intersecting point of the electrodes X3 and Y3 and results in an erasing pulse EP which exceeds an erasing level EL, thereby to erase the discharge spot at that intersecting point. In such a case, if the inter-electrode capacitance is taken as C1, if the earth capacity is taken as C2 and if the voltage impressed to the electrodes X3 and Y3 is taken as V], a voltage V2 given by the following equation is induced in electrodes adjacent to the electrodes X3 and Y3:

V2 (Cl/Cl C2)VI The voltage V2 is usually about Vl/S to Vl/lO. Consequently, in some cases, a pulse EIX such as indicated by VXB in FIG. 2 which is induced by the erasing pulse EX is impressed to the electrodes X2 and X4 adjacent to the electrode X3 and a voltage indicated by VB is applied to a half-selected cell B. Namely, a pulse EB above the erasing level EL is impressed to the halfselected cell B due to the induced pulse EIX and the erasing pulse EY applied to the electrode Y3. Such a pulse EB exceeding the erasing level EL causes an erroneous erasure. This imposes a severe limitation on the range of the erasing pulses Ex and EY, and hence results in the reduction of the operational margin. The same is true of other half-selected cells C, D and E and the impression of the write, read or like pulse also presents the same problem as described above.

Further, such induction as mentioned above similarly occurs in electrode terminal plates of the plasma display panel. This will hereinbelow be described with reference to FIG. 3.

FIG. 3 shows associated structures of leads of X electrodes arranged on a plasma display panel 10. Reference numerals 11A and 11B designate terminal plates having a plurality of leads arranged on a flexible thin plate or the like, and reference characters X1, X2, X3, indicate electrodes. Leads a1, a3, a5, of the terminal plate 11A are connected to odd-number electrodes X1, X3, X5, respectively and leads b2, b4, of the terminal plate 11B are connected to evennumber electrodes X2, X4, respectively. Where the electrodes are closely spaced apart from adjacent ones, all the electrodes are connected to the leads of one terminal plate. With such an arrangement, the impression of the address voltage such as a write, erasing, read or like voltage to a selected one of the electrodes induces a voltage in each of the adjoining electrodes due to the inter-electrode capacitance including the capacitance between adjacent leads.

FIG. 4 illustrates an equivalent circuit regarding the electrodes X1 to X4. Reference character C1 identifies the capacitance between adjacent ones of the electrodes, C2 the earth capacitance and C0 the capacitance between adjacent ones of the oddor evennumber electrodes. For example, if a voltage V1 is impressed to the electrode X1, a voltage V2 expressed by the following equation is induced in the electrode X2 adjacent to that X1:

and a voltage V3 given by the following equation is induced in the electrode X3:

Since the ratioof C1 to C2 is usually about l:(3 to 10), the voltage V2 is about 16 to 1/10]V1, and since C0 E 0.5C1, the voltage V3 is about [Vs to l/20]Vl. Accordingly, the discharge cells on the electrode X2, especially the discharge cell at the intersecting point of the electrodes X2 and X3, that is, the so-called halfselected cell, is likely to perform an erroneous operation due to the induced voltage. [in the electrode X3, the induced voltage is about one-half of that in the electrode X2, and hence it does not present such a problem. Such an induced voltage restricts the write, erasing, read and like operations within narrow limits to reduce the operational margin.

Incidently, an increase in the number of electrodes of the plasma display panel causes an increase in the number of drivers included in peripheral circuits for driving, so that it is the practice in the art to build up a matrix circuit with drivers and mixers to thereby minimize the increase in the number of the drivers with an increase in that of the electrodes. For driving the plasma display panel according to a diode-resistance matrix system, use is made of such a construction as depicted in FIG. 5. Of electrodes 0, 1, 2, the electrode, for example, 0, is selected by turning on a transistor Q11; off-transistors Q12 to Q18 and Q21; and on transistors Q22 to Q28. The electrodes 1 to 7, 9 to 15, are clamped by the transistors 022 to Q28 at the ground potential and the electrodes 8, l6, exhibit high impedance. The eletrodes 8, 16, which exhibit high impedance at this time, are arranged every eighth ones of the electrodes, so that an induced voltage therein is very small and negligible. A similar, modified circuit is in a form such as shown in FIG. 6. However, such a circuit necessitates the use of discrete parts as individual diodes. In order to employ a diode array of integrated construction for the diodes, it is necessary to arrange the electrodes in the order of parenthesized numbers in FIG. 5 and interconnect the diodes at one end. A modified form of the circuit in this case is illustrated in FIG. 7. With this circuit construction, where the electrode 0 has been selected, the transistor Q21 is held in its off state and the adjoining electrodes 1, 2, 3, are not grounded and consequently exhibit high impedance, presenting the problem of the induced voltage.

A system of addressing with a matrix circuit employing charge storage diodes has an advantage in that power dissipation is small as compared with the aforesaid diode-resistor matrix system but a disadvantage in that those electrodes adjacent to a selected one exhibit high impedance at the time of the addressvoltage impression, whereby the problem of the induced voltage is introduced.

SUMMARY OF THE INVENTION This invention is to provide a novel system for preventing an induced voltage in a plasma display panel which is free from the aforesaid defects encountered in the prior art and which avoids troubles resulting from a voltage induced in electrodes adjoining an electrode impressed with an address signal voltage.

Briefly stated, this invention is featured in the following points:

I. When an address voltage is impressed to a selected one of the electrodes of the plasma display panel, at least those electrodes adjacent to the selected one are clamped by a diode to a predetermined potential.

2. When an address voltage is impressed to a selected one of the electrodes of the plasma display panel, a group of electrodes including the selected one is clamped by an impedance element at a predetermined potential.

3. Oddand even-number electrodes of the plasma display panel are connected to leads of different terminal plates respectively. When any of the oddor evennumber electrodes is selected, the evenor oddnumber electrodes, respectively, are clamped at a predetermined potential.

4. Oddand even-number electrodes of the plasma display panel are connected to leads of different terminal plates respectively. Conductors connected to the even-number electrodes are each arranged to extend between adjacent ones of the leads of the terminal plate for the odd-number electrodes and, in a similar manner, conductors connected to the odd-number electrodes are each arranged to extend between adjacent ones of the leads of the terminal plate for the evennumber electrodes. When any of the oddor evennumber electrodes has been selected, the evenor oddnumber electrodes, respectively, are clamped at a predetermined potential together with the conductors connected thereto.

5. A voltage opposite in polarity to an address voltage for the impression to a selected one of the electrodes is impressed to those electrodes adjacent the selected electrode simultaneously with the impression of the former voltage.

The objects and advantages of this invention will become more apparent from the following description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an electrode arrangement diagram, for explaining a selected cell and half-selected cells;

FIG. 2 shows a series of waveforms, for explaining an erasing operation and an induced voltage trouble;

FIG. 3 is a diagram, for explaining the relation between electrodes and terminal plates of a plasma display panel;

FIG. 4 is an equivalent circuit diagram;

FIG. 5 is a circuit diagram illustrating the principal part of a diode-resistor matrix driving circuit of the prior art;

FIG. 6 is a circuit diagram of one part of the circuit diagram depicted in FIG. 5;

FIG. 7 is a circuit diagram of the principal part of a circuit in which electrodes in the circuit of FIG. 5 are connected in the order of parenthesized numbers in FIG. 5;

FIGS. 8 and 9 are circuit diagrams of the principal parts of examples of this invention in which electrodes adjoining a selected one are clamped at a predetermined potential;

FIGS. 10 to 12 are diagrams illustrating other examples of this invention in which oddand even-number electrodes are clamped together;

FIG. 13 is a circuit diagram showing another example of this invention in which electrodes are clamped by an impedance element at a predetermined potential at the time of addressing;

FIGS. 14 to 16 are circuit diagrams of the principal parts of other examples of this invention which prevents an induced voltage in a state including tenninal plates;

FIGS. 17A and 17B are cross-sectional views taken on the line AA in FIG. 16; and

FIG. 18 is a circuit diagram of the principal part of another example of this invention in which a voltage erasing an induced voltage is impressed.

DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 8, there is depicted a circuit diagram of the principal part of one example of this invention, which is a drive circuit employing charge storage diodes CSD. A decoder 20A is supplied with address signals 2", 2 and 2 and a decoder 20B is supplied with address signals 2 2 and 2 For example, an electrode 0 is selected by turning on a transistor Q11, off transistors O12, O13, and Q31 and on transistors O32, O33, Reference numerals 21A and 21B designate inverters, and 22 indicates AND gates. The output 1 from the AND gates 22 turn on the transistors O21, O22, Accordingly, upon application of an inverted address signal 1 and a timing pulse T? to the two inputs of the AND gate 22, the transistor Q21 is turned on to permit flowing of a current in a circuit of the transistor Q11, a diode DP, a charge storage diode CSD and the transistor Q21 from a power source Va. At an instant when the timing pulse TP has become 0, a transistor O4 is turned on to flow a current for a backward recovery time of the diode CSD, thereby impressing an address voltage such as a write, erasing, read or like voltage from power source V to the electrode 0. At this time, since the transistors O32, O33, are in the on state due to the signal 1 from the decoder 20A, electrodes 1 to 7, 9 to 15, are grounded through clamping diodes DN to thereby prevent induced voltage generation. Electrodes 8, l6, are not grounded but they are distant from the electrode 0, and hence do not offer any problem.

FIG. 9 is a circuit diagram of the principal part of another example of this invention which is adapted for the impression of positive and negative voltages and which is characterized in that diodes D1 and D2 are utilized for the clamping operation. In the case of selecting the electrode 0, transistors GP] and QP2 are turned on to flow a current in a charge storage diode CSD2 from a power source l-va and then a positive address voltage is impressed to the electrode 0 from a power source +V. At this time, a transistor QN is turned on, by which nonselected electrodes including an adjoining elec trode l are grounded through the diodes D2. In a like manner, in the case of impressing a negative address voltage, transistors QNl and QN2 are turned on to flow a current in charge storage diodes CSDL towards a power source Va and then the negative address voltage is impressed from a power source -V. At this time, the nonselected electrodes including the adjoining electrode l are clamped at the ground potential by turning on a transistor QP4, Where the address voltage has thus been impressed to the selected electrode, the nonselected electrodes adjacent to the selected one are grounded, so that the induced voltage problem can be avoided.

FIG. illustrates another example of this invention in which oddand even-number electrodes are connected to flexible terminal plates 31A and 31B, respectively, at opposite sides of a plasma display panel 30. At the time of addressing, a transistor Q5 is turned on and any one of transistors Q71 to Q74 and Q91 to Q94 is selectively turned on to flow a current in the charge storage diode CSD from the power source Va and then an address voltage is impressed from a power source (not shown) by utilizing the backward recovery time of the diode CSD. For example, where the electrode 4 has been selected, a transistor Q63 is in the off state but transistors Q61, Q62 and Q64 for for the even-number electrodes, or at least transistors Q62 and Q64 adjacent thereto, are turned on and transistors Q81 to Q84 for the odd-number electrodes, or at least transistors Q82 and Q83 connected to electrodes 3 and 5 adjacent to the electrode 4, are turned on. Consequently, since at least the electrodes 2, 3, 5 and 6 adjacent to the selected electrode 4 are grounded through the diodes DN, an induced voltage due to the address voltage is not established. Further, also in the terminal plates 31A and 31B, leads on both sides of that connected to the selected electrode are grounded to provide the shielding effect, so that where the leads are very long, the problem of inducing a voltage in the terminal plates is thereby overcome.

A matrix drive circuit by means of which three electrodes on both sides of the selected electrode are grounded is shown in a schematic form in FIG. 11. In FIG. 11, addressing and clamping diodes are left out and decoders 40A and 40B are shown as including the inverters 21A and 213, the AND gate 22 and the transistors depicted in FIG. 8 and the charge storage diodes for the respective electrodes are omitted. Unlike in the case of FIG. 8, the decoder 40A is supplied with address signals 2, 2 and 2 and decoder 40B is supplied with address signals 2 2 and 2. Numerals at the intersecting points indicate electrodes connected thereto. For example, where the electrode 4 has been selected, only the electrodes 0, 8, 12, are not clamped but the other electrodes are clamped. Namely, as is apparent from the electrode arrangement diagram shown in DN are disposed adjacent to each other, so that a diode array construction can be adopted.

In the foregoing examples, at least electrodes adjoining the selected electrode are clamped through diodes at the ground potential or a predetermined potential which cancels the induced voltage, thereby preventing the trouble resulting from a voltage which is induced where the address voltage such as the write, erasing read or like voltage is impressed to the selected electrode. A sustain voltage is usually impressed to all of the electrodes but the induced voltage trouble preventing means, described in the foregoing with regard to the examples, is also applicable to the case of the selective impression of the sustain voltage or temporary use of only one part of the plasma display panel for the purpose of overcoming halfselection troubles. Further, the foregoing examples have been described in connection with only one of the opposing electrodes but it is apparent that the same means as described above are employed for the other of the opposing electrodes.

Referring now to FIG. 13, another example of this invention will be described. FIG. 13 illustrates an address circuit employing charge storage diodes CSD for the one electrode group of a plasma display panel. The electrode groups are represented by four X electrodes X1, X2, X3 and X4. The electrodes. X1, X2, X3 and X4 are respectively connected to selecting points of a matrix circuit comprising charge storage diodes CSDl, CSD2, CSD4 and diodes Dal, Da2, Da4 and Dbl, Db2, Db4, and the electrodes are selected by drivers Adl, and A112 and Adll, Adl2 respectively.

The above construction is substantially identical with that of conventional address circuit and positive and negative rectangular sustain voltage pulse trains of Vs are alternately applied to the electrodes from terminals l and 2. In order to select the electrode, for example, X1 in the address operation within the time intervals of these sustain voltage pulse trains, transistors Q1 and Q11 making up the address drivers Adl and Adll are turned on by the outputs from a decoder 3, flowing a forward current in the charge storage diode CSDl through the diode Dal from the power source Va. As a result of this, charge is stored in the charge storage diode CSDl to permit it to conduct in backward direction only in its recovery time. Accordingly, if a transistor Qw or Qe, respectively, of a write driver 4 or an erasing driver 5 is further held in its: on state, a write address voltage Vw or an erasing address voltage Ve is applied to the electrode X1 only for the backward conduction time of the charge storage diode CSDI to perform desired writing or erasing, coupled with the corresponding address operation on the side of the Y electrodes (not shown).

The address circuit employing the charge storage diodes CSD is advantageous in that power dissipation for addressing is small but, on the other hand, the electrodes other than the selected one are all connected to high impedance circuits formed by transistors held in their off state at the time of addressing, so that the aforementioned induced voltage trouble due to the capacitance between adjacent ones of the electrodes adjoining the selected electrode is unavoidable. If the foregoing example were adapted for eliminating the induced voltage trouble, the circuit for clamping the adjoining electrodes in accordance with the selected electrode is appreciably complicated and expensive.

Referring again to FIG. 13, the illustrated example will be described. The selecting points of the matrix circuit, that is, the connection points to the electrodes X1, X2, X4, have connected thereto resistors R1, R2, R4 at one end respectively. The other ends of the resistors R1, R2, R4 are all interconnected and connected through a diode Dc to the collector of a clamping transistor Qc. The emitter of the transistor Qc is connected to a clamping power source Vc which is at ground potential in this case. The base of this transistor is supplied with an address signal from a control circuit (not shown) for turning on the transistor Qc only at the time of addressing, as is the case with the write and erasing drivers 4 and 5.

With the addition of such a circuit construction as described above, it is possible that, by turning on the clamping transistor Qc at the time of addressing the selected electrode, all the electrodes are held to be grounded through the resistors and the diodes, in other words, connected to an appreciably low impedance. As a result of this, even if the address voltage Vw or Ve is impressed to the electrode, a high induced voltage does not appear in the adjoining electrodes. Namely, the resistors R1, R2, R4 cannot completely reduce the induced voltage to zero but can lower it to such an extent as not to cause misaddressing.

Of course, in this case, one portion of the address voltage Vw or Ve applied to the selected electrode is also consumed by the resistor at its selecting point, so that it is necessary to set the address voltage in anticipation of the added consumption by the resistor. However, this invention has advantages that the clamping circuit can be constructed at low cost, as compared with the system of clamping the adjoining electrodes in accordance with the selected electrode, and that the induced voltage trouble can be effectively avoided.

FIG. 14 is a circuit diagram of the principal part of another example of this invention, illustrating some of the X electrodes. A terminal plate 51A has formed thereon leads a1, a3, a5, connected to the oddnumber electrodes X1, X3, X5, of a plasma display panel 50 and conductors ax2, ax4, connected to the even-number electrodes X2, X4, of the panel 50. In a similar manner, a terminal plate 518 has also formed thereon leads b2, b4, connected to the evennumber electrodes and conductors bxl, bx3, connected to the odd-number electrodes. These leads a1, a3, and b2, b4, have connected thereto drivers 52 respectively to impress the address voltage to the selected electrode. The diodes DP and DN are mixing diodes and the electrodes are connected to clamping circuits 53A and 538 through the diodes DP and DN. (Only the circuits connected to the terminal plate 51B are shown, but the terminal plate 51A is identical therewith.) The clamping circuits 53A and 53B are provided for clamping the evenor odd-number electrodes at a predetermined potential in the case where any of the oddor even-number electrodes has been selected. Transistors QLl and L3 are to clamp the electrodes at Vc and +Vc respectively and transistors 0L2 and 0L4 are to clamp the electrodes at the ground potential.

For example, when the electrode X3 has been selected and supplied with the address voltage inducing positive potentials in the adjacent electrodes X and X the transistor QLZ is turned on, thereby clamping the adjacent electrodes X2 and X4 to ground potential through the diodes DN and the conducting transistor 0L2. In this case, in the terminal plate 51A, the conductors ax2 and ax4, connected to the even-number electrodes x 2 and x4 and disposed on opposite sides of the lead a3, are also grounded and, in the terminal plate 51B, the leads b2 and b4 on opposite sides of the conductor bx3 are also similarly grounded, so that the induced voltage problem as to the electrodes X2 and X4 on opposite sides of the electrode X3 and the corresponding conductors of both terminal plates can be completely prevented by the shielding efiects of these conductors. The electrodes X1 and X5 are not grounded but those X2 and X4 adjacent them and the selected electrode X3 respectively are grounded, so that the resulting induced voltages become very low and there is substantially no possibility that the induced voltage problem occurs. Where the voltages induced in the adjoining electrodes X2 and X4 are negative, the transistor QL4 of the clamping circuit 538 is turned on. Further, where the induced voltages are required to be clamped at a predetermined potential, the transistor QLl or QL3 is appropriately turned on.

The above description has been given with regard to the case where the odd-number electrode X3 has been selected but also in the case where any of the evennumber electrodes X2, X4, has been selected, the odd-number electrodes X1, X3, are clamped at a predetermined potential such as the ground potential or the like by the clamping circuit 53A connected to the leads a1, a3, of the terminal plate 51A. During the impression of the sustain voltage except at the time of addressing, the clamping circuits 53A and 53B are not operative. Also on the side of the Y electrodes, the induced voltage problem is prevented in the same manner as that described above.

FIG. 15 illustrates another example of this invention, in which shielding conductors ax2, 0x4, each disposed between adjacent ones of the leads on a terminal plate 61, are not connected to the electrodes of a plasma display panel 60 but instead are connected together to a clamping circuit 62. The clamping circuit 62 is identical in construction with that depicted in FIG. 14 and the leads a1, a3, are shielded by the shielding conductors (1x2, ax4, from each other at the time of impressing an address voltage such as for writing, erasing, reading or the like. Accordingly, it is possible to prevent the induced voltage problem from occuring on the terminal plate 61.

FIG. 16 shows another example of this invention. The cross-section of a terminal plate 71 connected with the electrodes of a plasma display panel 70, taken along the line AA in FIG. 16, is shown in FIG. 17A. In FIG. 17A, reference numeral 81 indicates insulating layers, 82 shielding conductive layers and 83 insulating layers interposed between leads 84 and the conductive layers 82. A clamping circuit 72 is connected to the conductive layers 82, by which if an odd-number electrode is selected at the time of impressing an address voltage such as for writing, erasing or reading, the conductive layers 82 of the terminal plate for the leads of the evennumber electrodes are clamped at a predetermined potential such, for example, as the ground potential.

FIG. 178 shows, in section, a modified form of the terminal plate, in which leads 94 are each surrounded by an insulating layer 93 and are thereby insulated from each other and embedded in a conductor layer 92. Reference numeral 91 designates insulating layers. This construction provides for further enhanced shielding effect, as compared with that of FIG. 17A.

As has been described in the foregoing, in the examples of FIGS. 14 to 17, the leads of the terminal plates are divided into those connected to the odd-number electrodes and those to the even-number electrodes and connected accordingly, and the conductors disposed near the leads are clamped at a predetermined potential such as the ground potential or the like. When either one of the odd-or even-number electrodes has been selected by the impression of the address voltage such as for writing, erasing or reading the conductors disposed adjacent to the leads on the terminal plate having connected thereto the other electrodes are clamped, so that an increase in capacitance due to the adjoining conductors does not offer any problem during usual sustain voltage impression and, at the time of impressing the address voltage, the adjoining conductors are clamped by the clamping circuit at the ground potential or at such a potential as cancelling the induced voltage, thus enabling prevention of the induced voltage problem in the adjoining electrodes. This pro vides for enlarged operational margin for the writing, erasing and reading operations.

FIG. 18 is a circuit diagram of the principal part of still another example of this invention which is suitable for preventing the induced voltage problem which occurs in the reading operation of the plasma display panel. FIG. 18 shows only the side of electrodes Y1 to Y4. Sustain voltages +Vs and Vs are alternately applied to all of the electrodes from sustain voltage circuits 100A and 1008 at all times. In the case of reading the state of cells on the electrode, for example, Y2, a read pulse of a voltage V is impressed by turning on a transistor 0102 to the electrode Y2 in the time intervals of sustain voltage pulses and, at the same time, a voltage -V is applied by turning on a transistor Ql to the electrodes Y1 and Y3 adjacent to that Y2. If the voltage -V is not impressed, erroneous erasure or writing in cells on the adjoining electrodes is caused by voltages which are induced in the adjoining electrodes at the time of the impression of the read pulse V Namely, the operation becomes unstable. The voltage V is selected at a value which cancels the influence exerted on the adjoining electrodes by the voltage V,,. Though different in accordance with the electrode intervals, the impression voltage or the like, the voltage -V is selected to be, for example, about one-third of the voltage V As is the case with the foregoing examples, where the read pulse of the voltage V has been impressed to the electrode Y3 by turning on a transistor Q104, a transistor 0103 is turned on to apply the voltage -V to the electrodes Y2 and Y4. Since the read pulse serving an an address voltage is positive, the voltage -V opposite in polarity thereto is impressed to those electrodes adjacent the selected one but where the read pulse is negative, a voltage +V opposite in polarity thereto is ap plied to the adjacent electrodes.

As in the examples described in the foregoing, also in the case where a write pulse or an erasing pulse has been impressed, a voltage opposite in polarity thereto is impressed to cancel the electric field acting on the adjacent electrodes, thereby to remove the undesired influence such as a change in a wall voltage or the like. The present example has been described in relation to the Y electrodes only but exactly the same measures as This invention is not limited specifically to the foregoing examples but many modifications and variations may be effected within the scope defined by the appended claims.

What is claimed is:

1. A system for preventing undesired effects from voltages induced in a plasma display comprising first and second sets of plural electrodes disposed to intersect each other and define at each such intersection a discharge cell, and wherein circuit means are provided for supplying an alternating sustain voltage to said cells, the amplitude of which is sufficient only to maintain an existing discharge, and wherein an addressing voltage applied to a selected electrode of each said first and second sets serves to establish an address voltage at a corresponding selected cell which exceeds the firing voltage of the cell and establishes a discharge therein, and system comprising:

means for applying an addressing voltage to a selected one of the electrodes of at least one of said first and second sets of electrodes, including, for each electrode,

a first diode having a relatively short charge storage time and a second diode having a relatively long charge storage time connected in series to said first diode at a junction and commonly poled for conduction, said junction being connected to the electrode, and

means for applying a forward current to said diodes associated with a selected electrode, and means for supplying an addressing voltage to the cathode of said second diode, selectively as to each selected electrode, thereby to apply the addressing voltage to the selected electrode by reverse conduction of said second diode in accordance with the pre-stored charge therein, and means operative simultaneously with said addressing voltage means for coupling at least those electrodes disposed immediately adjacent: a selected electrode to a potential of a level selected with respect to that of said addressing voltage to suppress voltages induced in said adjacent electrodes when an addressing voltage is applied to a selected electrode. 2. The system as claimed in claim 1, wherein said coupling means couples a potential to said adjacent electrodes which is opposite in polarity to that of said address potential.

3. The system as claimed in claim 1, wherein said second diode comprises a charge storage diode.

4. The system as claimed in claim 1, wherein said coupling means couples a group of electrodes including said selected electrode through impedance elements to said selected potential.

5. A system for retarding undesired signals from being induced into a plasma display panel comprising first and second sets of plural electrodes disposed to intersect each other and define at each such intersection a discharge cell, at least said first set of electrodes including a first plurality of electrodes spaced from each other and a second plurality of electrodes interposed between said electrodes of said first plurality, said system comprising:

means for applying an addressing voltage to a selected electrode of one of said first and second pluralities of electrodes, including, for each electrode,

a first diode having a relatively short charge storage time and a second diode having a relatively long charge storage time connected in series to said first diode at a junction and commonly poled for conduction, said junction being connected to the electrode, and

means for applying a forward current to said diodes associated with a selected electrode, and

means for supplying an addressing voltage to the cathode of said second diode, selectively as to each selected electrode, thereby to apply the addressing voltage to the selected electrode by reverse conduction of said second diode in accordance with the pre-stored charge therein, and

coupling means operative in a first mode when said addressing voltage is applied to a selected electrode of said first plurality for coupling said electrodes of said second plurality of the same said set to a potential of a level selected with respect to that of said addressing voltage to suppress voltages induced in said electrodes of said second plurality, and operative in a second mode when an addressing voltage is applied to a selected electrode of said second plurality for coupling said electrodes of said first plurality to said potential of said selected level.

6. The system as claimed in claim 5, wherein there are included first and second terminal plates having corresponding first and second pluralities of leads connected to corresponding ones of said respective first and second pluralities of electrodes.

7. The system as claimed in claim 6, wherein there are further provided first and second pluralities of conductors respectively connected to corresponding electrodes of said first and second pluralities, and disposed individually between said leads of said second and first tenninal plates, respectively, said coupling means in said first mode of operation further coupling said second plurality of leads to said selected potential and in said second mode of operation coupling said first pluralityof leads to said selected potential.

8. The system as recited in claim 1 wherein the addressing voltage applying means further includes, for each electrode,

a series connection of a third and a fourth diode of the types of said first and second diodes, respectively, and poled for common conduction in a reverse sense to said first and second diodes, and further addressing means for applying addressing voltages of opposite polarity, relative to said first named addressing voltages, to the cathode of said fourth diode and further coupling means for coupling at least the said adjacent electrodes to said selected potential for suppressing the voltages induced therein.

9. The system as recited in claim 1 wherein said coupling means includes a unidirectionally conducting element for applying said selected potential to said adjacent electrodes.

10. The system as recited in claim 1 wherein said coupling means includes impedance elements for applying said selected potential to a group of said electrodes including a selected electrode.

11. The system as recited in claim 5 wherein said coupling means includes means for selective connection to at least the electrodes adjacent a selected electrode of one of said pluralities and at least the electrodes of the other of said pluralities adjacent the selected electrode of the one said plurality.

12. A system for suppressing undesired signals from being induced into a plasma display panel comprising pluralities of row and column electrodes disposed on at least one of the inner walls of an envelope to intersect each other thereby to define at the intersections a corresponding plurality of discharge points across an ionizable gas sealed in the envelope, the pluralities of row and column electrodes being covered with dielectric layers having surfaces in direct contact with the ionizable gas, said system comprising:

means connected with said pluralities of row and column electrodes for supplying each of said plurality of discharge points with analternating sustain voltage, the level of which is insufficient to produce a discharge by itself but sufficient to maintain a discharge once produced;

means connected with said pluralities of row and column electrodes for selectively supplying said plurality of discharge points with an address voltage, the level of which is in excess of that of the firing voltage for a discharge point, said address voltage selective supply means including as to each said electrode a first diode having a relatively short charge storage time, a second diode connected in series therewith at a common junction and poled for conduction in the same direction and having a relatively long charge storage time, means for connecting said common junction of said diodes to the said electrode, means for selectively applying a forward current to said diodes, and means for selectively connecting an address voltage source to the cathodeof said second diode, the address voltage being applied to said selected discharge point by reverse conduction of said second diode in accordance with charges pre-stored therein; and means for selectively connecting at least the electrodes adjacent to an electrode associated with a selected one of said plurality of discharge points to a potential source of such a polarity as to by-pass voltages induced in said adjacent electrodes when an address voltage is applied to said selected discharge point, said connecting means being energized simultaneously with the application of said address voltage, thereby to prevent undesirable effects of the voltages induced in those electrodes adjacent to the selected electrode.

- UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent Dated November26, 1974 Inventor) Shozo Umeda; Hiroshi Furuta; Teruo Toba; Hiroshi Goto &

Hiroyuki Shizaki It is certified that error appears in the above-identifiedpatent and that said Letters Patent are hereby corrected as shown below:

Column 1, line 155, Equation (1) should read: I l

W c1'/(c1 c2 v1 Column 2, line 19, should read:

I v2 =[C1"/ (C1'+ c 2') v1 Column 2, 1ine'2-2, Equatiou (2 sho uld read: v3 c0/(co+c2 v1 Column 9,, li ue 30, should read:

Y4. Sustain voltages +Vs and Vs are alternately applied Signed and sealed this 4th day of February 'i l975 (SEAL) Attest:

McCOY M. GIBSON JR. C. MARSHALL DANN Attesting Officer Commissioner of Patents

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
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US3573542 *Mar 28, 1968Apr 6, 1971Control Data CorpGaseous display control
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3967157 *Jan 20, 1975Jun 29, 1976Nippon Electric Company, Ltd.Driving circuit for a gas discharge display panel
US4027196 *Nov 12, 1975May 31, 1977International Business Machines CorporationBilateral selective burst erase system
US4077033 *Sep 13, 1976Feb 28, 1978Control Data CorporationPlasma display drive circuit and method
US4099097 *Jul 2, 1976Jul 4, 1978Owens-Illinois, Inc.Driving and addressing circuitry for gas discharge display/memory panels
US4485380 *Jun 8, 1982Nov 27, 1984Sony CorporationLiquid crystal matrix display device
DE2630618A1 *Jul 7, 1976Feb 3, 1977Nippon Electric CoSteuerschaltung fuer eine gasentladungs-anzeigetafel
DE3221972A1 *Jun 11, 1982Jan 5, 1983Sony CorpMatrixfoermige fluessigkristall-anzeigeeinrichtung
DE3221972C2 *Jun 11, 1982Aug 22, 1991Sony Corp., Tokio/Tokyo, JpTitle not available
Classifications
U.S. Classification345/58, 345/208, 345/69
International ClassificationG09G3/28, G09G3/288
Cooperative ClassificationG09G2320/0209, G09G2300/088, G09G3/296
European ClassificationG09G3/296