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Publication numberUS3866022 A
Publication typeGrant
Publication dateFeb 11, 1975
Filing dateDec 26, 1972
Priority dateDec 26, 1972
Publication numberUS 3866022 A, US 3866022A, US-A-3866022, US3866022 A, US3866022A
InventorsFletcher James C Administrator, Messner Alan, Perlman Marvin, Rousey William J
Original AssigneeMessner Alan, Nasa, Perlman Marvin, Rousey William J
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
System for generating timing and control signals
US 3866022 A
Abstract
A system capable of generating every possible data frame subperiod and delayed subperiod of a data frame of length of M clock pulse intervals (CPIs) comprises parallel modulo-mi counters. Each mi is a prime power divisor of M. Each mi=pi alpha i is a cascade of alpha i identical modulo-pi counters, where mi p = pi < alpha > . The modulo-pi counters are feedback shift registers which cycle through pi distinct states. By this organization, every possible nontrivial data frame subperiod (in terms of clock pulse intervals) and delayed subperiod may be derived. Also, a specific CPI in the data frame may be detected. The number of clock pulses required to bring every (or a subset of all) modulo-pi counter to a respective designated state or count is determined by The Chinese Remainder Theorem. This corresponds to the solution of simultaneous congruences over relatively prime moduli.
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United States Patent Fletcher et a1.

[ Feb. 11, 1975 1 SYSTEM FOR GENERATING TIMING AND 3.548.175 12/1970 Tomlin 235/92 DM CONTROL SIGNALS I [161 Jame of izztzzzf stiszizgszit is; N l Aefonauucs & Space Attorney, Agent, or Firm-Monte F. Mott; Paul F.

ministration in respect to an Mccaul' John R Mannin invention by; Marvin Perlman, g Granada Hills; William J. Rousey, Tujunga; Alan Messner, Monrovia, [57] ABSTRACT all of Calif. A system capable of generating every possible data frame subperiod and delayed subperiod of a data [22] 1972 frame of length of M clock pulse intervals (CH5) [2]] Appl. No.: 319,150 comprises parallel modulo-m counters. Each m is a prime power divisor of M. Each m1- is a cascade of at identical modulo-p counters, Where m =p,-i. The [52] 235/92 x 1; mania-matter; are feedba ck shift registers which [51] Int Cl H03k 21/36 cycle through p distinct states. By this organization, I every possible nontrivial data frame subperiod (in [58] Field of g gkggs gg 5g kg terms of clock pulse intervals) and delayed subperiod may be derived. Also, a specific CPl in the data frame [56] Reierences Cited may be detected. The number of clock pulses required to bring every (or a subset of all) modulo-p counter to UNITED STATES PATENTS a respective designated state or count is determined 2,602,140 7/1952 Fink 235/92 DM by The Chinese Remainder Theorem. This corre- Mlehle ponds to the olution of Simultaneous congruences 3,019,975 2/1962 Williams i i 235/92 CP Over relatively prime moduli. 3,283 l31 11/1966 Carbrey 235/92 DM $443,070 5/1969 Derby 235/92 DM 9 Claims, 18 Drawing Figures 200 20f 201: 020!) ""2ou"'2ou 20- T T I 2o|:l cm suBPERlOD J 2| 20g MODULOP| MODULO-P| I 25 I cgu igsn cogr rgn 2ob I l 12 1 J 02m, 4cm sua emon MASTER O l (M -l) '2 CLOCK 1 T 2 2| 2' 20a 2cPr SUBPERIOD 2 "2 2| 3 CPI SUBPERIOD COUNTER 2| P2 s 0200 27 ATENTEDFEBJ 1 I97 SHEET 1 [1F 7 ooooo F14 Korma C C C cczzcccdccz o m m w w v m N o 2&0: O

20040 mmPm E PATEHTEU FEB 1 1 I975 SHEET 5 BF 7 FIG?- CPI 5 in M mm -2o 0 0m vMB 2 N C OH M4 IA] mu D om MA 3 4A m m 4 0M0 0| A 0 D0 2 0 C C 0 m0 8 W0 W0 4 0 3 A A M0 N0 no |OOO22 OO'O PATENTEUFEBI 1 197a 3. 866.022

SHEET 6 OF 7 0 '0 o o o o 0 CLOCK FIG.90

V FIGIOb 'Flcaloa CLOCK SYSTEM FOR GENERATING TIMING AND CONTROL SIGNALS ORIGIN OF INVENTION The invention described herein was made in the performance of work under a NASA contract and is subject to the provisions of Section 305 of the National Aeronautics and Space Act of 1958, Public Law 85-568 (72 Stat. 435; 42 USC 2457).

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is generally related to a system for generating timing and control signals and, more particularly, to a system for generating timing and control signals during each fixed length serial data frame which is repetitive.

2. Description of the Prior Art There are many applications in which it is necessary to provide different timing and control signals for controlling different experiments or operations, yet insure that all of the signals are synchronized to a master clock. Assuming that all the experiments occur at different subperiods of a master data frame of length which is equal to a fixed number of intervals, defined as M, of clock pulses from the master clock in theory a modulo-M counter which is clocked by the master clock can be used. As the counter is sequenced through its M states, selected ones of the states may be used to produce specific timing signals from the start of the frame as well as define specific subperiods of the frame. However. if M is very large and the clocking frequency is high, severe propagation delays and ripple problems are encountered. These can only be overcome by-a large amount of logic circuits which greatly increases the complexity and cost of the system. Thus, a need exists for a new system to generate timing or control signals which define subperiods or delayed subperiods of a master data frame of clock pulse length M.

OBJECTS AND SUMMARY OF THE INVENTION It is a primary object of the present invention to provide a new system for generating synchronized timing and control signals.

Another object of the invention is to provide a new system for generating selected subperiods and/or delayed subperiods of a master data frame of a fixed number of clock pulses.

A further object of the invention is to provide a system of minimum complexity which is capable of providing all subperiods and delayed subperiods of a relatively long fixed-length data frame.

These and other objects ofthe invention are achieved for a data frame of length M by providing a plurality of modulo-m.- counters which are clocked in parallel by a master clock. Each m, is a prime power divisor of M, other than I and M. Each modulo-m; counter is a cascade of at, identical modulo-p,- counters where m, p Each p, is a distinct prime of M, and each a, is an integer not less than 1. Each of the modulo-P,-

counter cycles through p,- distinct states. By detecting The novel features of the invention are set forth with particularity in the appended claims.

The invention will best be understood from the following description when read in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a multiline clock pulse waveform diagram;

FIG. 2 is a block diagram of a prior art arrangement;

FIG. 3 is a block diagram 'useful in explaining one example of an embodiment of the present invention;

FIG. 4 is a state table of the counters shown in FIG. 3;

FIG. 5 is a diagram of the embodiment shown in FIG. 3 and implemented with ring counters;

FIGS. 6 and 6a are diagrams useful in explaining another embodiment of the invention;

FIG. 7 is a state table of the counters shown in FIG.

FIG. 8 is a diagram of counter D shown in FIG. 6 as a ring counter;

FIGS. 9a, 9b and 9c are diagrams of a 2-stage modulo-3 FSR, its state cycle and decision logic;

FIGS. 10a and 10b are diagrams ofa l-stage modulo- 2 FSR and its state cycle;

FIGS. 1 1a and 11b are diagrams of a 3-stage modulo- 5 FSR and its state cycle; and

FIGS. 12a and 12b are diagrams ofa 3-stage modulo- 7 FSR and its state cycle.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention may best be described in connection with two specific examples and thereafter generalized for the most general cases.

Attention is first directed to FIG. 1 wherein in line a, a succession of clock pulses each of a fixed clock pulse interval (CPI) is diagrammed. Let it be assumed that the period of a data frame is defined by M CPIs, which in line a is assumed to be 12. The 12 CPIs are designated 0-1 I. Let it further be assumed that during the data frame various experiments are conducted which require control signals at different subperiods of the data frame, such as subperiods of 2, 3, 4 and 6 CPIs in length. Such subperiods are diagrammed in lines b through e, respectively.

It is clear to those familiar with the art that such subperiods may be defined by a modulo-M counter where M=l2 which is clocked by the master clock and which advances through 12 states, 0-1 1. With the addition of decision logic, the subperiod of 2 CPIs can be defined by generating a pulse when the counter is in states 0, 2, 4, 6, 8, l0, 0 etc., while the subperiod of 3 CPIs can be generated by producing a pulse each time the counter is in states 0, 3, 6, 9, 0 etc.

One way of generating such subperiods is to employ a l2-stage ring counter, in which all stages store a binary 0 except one stage which stores a binary I, so that as the counter is clocked the binary l shifts from one stage to the next. By connecting stages 0, 2, 4, 6, 8 and 10 to one OR gate, this gate would provide a true out put which represents a pulse each time any of these stages stores the binary 1 thereby defining the start of each subperiod of 2 CPIs (line b). Similarly, the other subperiods can be defined in a similar way. Such an arrangement is shown in FIG. 2 wherein the l2-stage ring counter is designated by numeral 10, the master clock by numeral 12 and the four gates which produce output pulses which define subperiods of 2, 3, 4 and 6 CPIs by numerals l3-l6, respectively. The ring counter is shown in state 0.

It should be obvious that even in this simple example 12 memory stages or units of counter are needed. Clearly as M increases, which in many practical applications may be equal to several millions, an extremely large number of memory units is needed. This greatly increases the cost and complexity of the system needed to generate the subperiods. The number of memory units may be reduced by replacing the ring counter with a minimum stage feedback shift register (FSR) at the cost of increased decision complexity. For example, a 4-stage FSR may be used and operated to cycle only through l2 states rather than through 2 =16 states. However, decision logic would be required to define each of the 12 states in terms of the binary states of the 4 stages.

The present invention provides a completely new approach to generating such subperiods and delayed subperiods as will be described hereafter. In accordance with the present invention, any modulo-M counter of clock pulses is decomposed into parallel modulo-m,- counters, where each m, is a prime power divisor (or factor) of M. Each m, counter is implementable as a cascade of 0:, identical modulo-p,- counters, where m,- pf" p,- is one of the distinct primes of M, and a, is an integer at least equal to one. Each modulo-p,- counter cycles through p,- distinct states. The combination of the states of the a,- identical modulo-p,- counters cycle through m,- states. In a system, comprising such an organization, every possible non-trivial data frame subperiod in terms of CPIs and delayed subperiods may be derived.

The principles of the invention will now be described assuming M l2. Unique factorization except for order gives:

Let

where The arrangement of m, factors is arbitrary as long as pair-wise relative primeness holds. This is guaranteed by the unique factorization into products of powers of distinct primes, where each distinct prime power corresponds to an m,. Furthermore, prime power factoriza tion enables one to enumerate all divisors of M. It is clear that m, 4 and m 3 are the prime power factors of M 12 and that 2 and 3 are the two distinct primes of M 12.

Let

p =2andp =3 The following polynomial factors, when multipled, yield terms which correspond to every divisor of M.

(l p p (l +p The number of terms in the resulting polynomial is Thus, there are six divisors of M, four of which are proper, with l and M being the improper divisors. It is clear that the four proper divisors of M 12 are 2, 3, 4 and 6.

In accordance with the present invention for M 12, two parallel modulo-m,- counters are provided. One counter is a modulo-m counter and the other is a modulo-m counter. Since m, 4 and m 3, the counters area of modulo-4 and modulo-3. Such an arrangement is shown in FIG. 3 in which the two counters are designated by numerals 20 and 21, respectively.

As previously pointed out, each m, counter is decomposed into a, modulo-p, counters, where Ira-=12? In the case of m,, since m p, 2 it is decomposed into 2 modulo-p, 2 counters, which in FIG. 3 are designated as 20a and 20b. However, since m p 3 it is represented by a single modulo-3 counter 21.

Each counter is shown with a plurality of output lines each of which is assumed to be true or high hereafter also referred to as being at a 1 level when the counter is at the state corresponding to the line designation. It is obvious that each of counters 20a and 20b being a modulo-2 counter, cycles through 2 states 0 and I, while counter 21 being a modulo-3 counter cycles through 3 states 0, l and 2. The counters 20 and 21 are synchronously clocked by master clock 12. In counter 20, the leftmost counter 20a is clocked directly from clock 12. However, the next counter 20b is clocked only when counter 20a changes from its highest state which is l to its lowest state which is O. This is achieved by incorporating a logic element represented by gate Z. Basically, it permits counter 20b to be clocked by a clock pulse from master clock 12 only when line 1 changes from high to low which occurs only when counter 20a changes from state I to state 0. Assuming that all the counters are at state 0 at the first CPI of the data frame which is designated as n 0, the states of the counters at the other 11 CPIs is as shown in the state table of FIG. 4.

In accordance with the present invention, any subperiod of M 12 can be derived from these three counters. For example, to obtain a subperiod of 6, since 6 23, the start of each subperiod is provided by detecting the instance when both counters 20a, which is a mod-2 counter and counter 21 which is a mod-3 counter are at the 0 state. This can easily be accomplished by means of an AND gate 25 which is connected to lines 0 and 0 as shown in FIG. 3. It is clear from FIG. 4 that both of these counters are at state 0 only at n 0 and n 6. To obtain a subperiod of 3, all that is necessary is to detect a high level at line 0 which occurs only every third CPI. To obtain a subperiod of 4 CPIs, since modulo-4 counter 20 is decomposed into 2 counters 20a and 20b, the outputs of both of these counters need be detected. This is easily achieved by ANDing the output lines 0 and 0 in an AND gate 26.

As seen from FIG. 4, even though each of counters 20a and 20b cycles through only states 0 and 1, their combined outputs 00, 10, 01 and 11 represent the four states 0, l, 2 and 3 respectively, of counter 20, as shown in the second column from'the right in FIG. 4. It is thus seen that the arrangement shown in FIG. 3 is capable of providing any subperiod of M 12.

Defining the subperiod by M any subperiod may be delayed .from the start of the frame by up through M'- l CPIs. For example, let it be assumed that it is desired to provide a subperiod of 4 CH5 which starts 2 CPls after the start of the data frame, i.e., at n 2 as diagrammed in linefof FIG. 1.

2 2mod4 Consequently, state 2 of the mod-4 counter has to be detected. This state is represented by the combined states of and l counters 20a and 2012, respectively. Thus, by ANDing lines 0 0,, and 120,, by gate 27, as shown in FIG. 3, a pulse is produced at n 2 which indicates the start of the first 4-CPI subperiod and thereafter every 4 CPIs such as at n 6 and n 10. This is shown in FIG. 4.

Assuming that a subperiod of 6 CPIs is desired which is delayed by 4 CPIs, since 4 i 0 mod 2 4 i 1 mod 3 Thus, by ANDing output lines 0 of modulo-2 counter 20a which is high at state 0 with line 1 which is high at state I of mod-3 counter 21 a first pulse is produced at n 4, and thereafter every 6th CPI such as at n 10.

It is thus seen that with the present system any delayed subperiod may be generated. As will be pointed out hereafter, the system may be used to detect a particular CPI in the data frame. However, this point may better be highlighted later with an example in which M is very large and the system includes a large number of parallel modulo-m, counters.

FIG. to which reference is now made is a block diagram of the arrangement of FIG. 3 implemented with simple ring counters all of which are shown in state 0. As seen, counter 21 which is a mod-3 counter, is implemented by a three-stage ring counter, while each of counters a and 20b is implemented by a two-stage ring counter. It is thus seen that only 3 2 2 7 memory stages are required for M 12 as compared with the requirement of a I2-stage ring counter as shown in FIG. 2.

The advantages of the invention becomes more apparent when M is large. Let

M 75,600 Unique factorization except for order gives m, 1 It is obvious that -1 are the distinct primes and m, m, are the prime power factors of M. It can be shown that the number of proper divisors of M is The number of terms in the resulting polynomial is +3)( l+2)(l+l) 120 Thus, the total number of divisors is I20, I I8 of which are proper.

To obtain all possible I I8 subperiods of M four modulo-m, counters are clocked in parallel. One

Counter is of modulo-m, modulo-l6. Another counter is of modulo-m modulo-27. The third counter is of modulo-m modulo-25 and the fourth counter is of modulo-m modulo-7. Since m, =12,

2, the modulo-m counter is decomposed into a (2215- cade of 4 modulo-2 counters. Likewise, since m p 3 the modulo-m counter is decomposed into a cascade of 3 modulo-3 counters. Following the same process since m =p 5 the modulo-m counter is decomposed into a cascade of 2 modulo-5 counters. As to the last counter since m =p 7 it is represented by a single modulo-7 counter. Such an arrangement is shown in FIG. 6 wherein the four counters are designated as A, B, C and D. Counter A, which is the modulo-m, counter is shown comprising of four counters Al-A4 each of modulo-2, counter B which is the modulo-m counter is shown comprising 3 counters Bl-B3 each of modulo-3 and counter C which is the modulo-m counter is shown comprising 2 counters Cl and C2, each of modulo-5.

It is apparent to those familiar with the art that counters of modulo-2, modulo-3, modulo-5 and modulo-7, cycle through 2, 3, 5 and 7 states hereafter designated 01, 012, 0, l, 2, 3, 4 and 0, 1, 2, 3, 4, 5 and 6 respectively. As in the arrangement shown in FIG. 3, the leftmost counter of each of counters AD in FIG. 6, is closed in synchronism, thereby changing state by each clock pulse. However, each succeeding counter in a chain, such as counter A2 of counter A or counter B2 of counter B is clocked only when the preceding counter in the chain, such as Al or B1 changes from its highest state such as l or 2 to its lowest state 0. This is achieved by the inclusion of gates Z.

In operation, all the counters are reset to their 0 states when the first CPI of the frame, i.e., CPI n 0 is received. It is obvious that different means may be used to reset all counters to their 0 state. Thereafter the counters cycle through their different states as they are clocked by the master clock 12. Their states during CPI n 0 through n 33 are listed in FIG. 7. It is clear that the combined states of A1 and A2 form a 4-state sequence, the combined states of A1, A2 and A3 form a 8-state sequence and the combined states of A1, A2, A3 and A4 form the l6-state sequence of counter A. Also, the combined states of B1 and B2 form a 9-state sequence and they together with B3 form the 27-state sequence of counter B. Likewise, the states of counters Cl and C2 form the 25-state sequence of counter C. These sequences are also listed in FIG. 7.

Several of the following examples will indicate that any of the l 18 subperiods ofM may be obtained by the arrangement of FIG. 6.

EXAMPLE I Let it be assumed that CPIx O 40 for k O, l

is to be generated. That is, M is to be divided into equal subframes of length 40. Let the subperiod of 40 be designated by M. Thus Thus, the outputs of a mod-2 counter and a mod-5 counter need be combined. In the present invention, a mod-2 counter is represented by combining the outputs of the leftmost 3 counter A1-A3 of counter A. The single mod-5 counter is represented by the leftmost counter CI of counter C. Thus, when all of these counters are at the 0 state, a pulse should be produced.

This can be easily achieved by ANDing the output lines 0, 0, 0, and O in an AND gate 30 shown in FIG. 6a. This gate will provide a true output representing a pulse for every 40 pulses of the master clock.

The first output pulse of a subperiod of 40 may be delayed by up to 40 l 39 pulses. Assume that the first pulse is to be delayed by 15 CPIs.

l5 7 mod 2 7 mod 8 mod As seen from FIG. 7 at n state 7 of the mod-8 counter is represented by an all 1 state in each of counters A1, A2 and A3 while the mod-5 counter represented by counter Cl is at state 0. Thus, to delay the subperiod of 40 by 15 CPIs, output lines 1, 1, 1, and 0 are ANDed by an AND gate 32 (see FIG. 6a). It would provide the first pulse at n 15 and thereafter every 40 CPIs.

In the above expression let the states of 7 and 0 in the mod-8 and mod-5 counter be designated by a, and a respectively. It can generally be stated that the subperiod M can be delayed by up to M l CPIs by detecting a particular nonzero combination ofa 19 in the modulo-8 and modulo-5 counters, respectively. In the above example, it is 7, 0. However, other combinations of nonzero states will be present for different delays of the subperiod of 40. The maximum delay is 40 l 39 CPIs.

EXAMPLE 2 n 7? III III III III l2 5 4 mod 8 and 12 i 2 mod 5 Thus, the first time that the states 4 and 2 will appear in the mod-2 and mod-5 counters is n 12. That this indeed is the case in the present invention is apparent from FIG. 7. As seen at n I2, the states of Al, A2, A3 are 001 which represent state 4 in the mod-2 counter and the mod-5 counter Cl at n 12 is at state EXAMPLE 3 Let it he assumed that CPI 30 must be identified as M 75,600. Since M=2" 3" 5 7'=l6-27-25-7 30 I I4 mod I6 I 3 mod 27 5 mod 25 2 mod 7 Thus, CPI 30 occurs when counters A, B, C, and D are in states 14, 3, 5 and 2, respectively. That this is indeed the case is seen from FIG. 7. At n 30, state 14 of counter A is represented by 0111 of counters A1 A4. State 3 of counter B is represented by states 010 of counters B1 B3, and state 5 of counter C is represented by states 01 of counters C1 and C2. Counter D is at state 2. Thus, by ANDing output lines 0 1 1 1, 0, 1 0 O 1 and 2,, in gate 35 as shown in FIG 6a, this gate will provide a true output only at n 30 of each frame.

EXAMPLE 4 Assume that CPI 2000 of M 75,600 is to be identified. Since M=-l6 27 25 7 2000 I 0 mod 16 E 2 mod 27 g 0 mod 25 i 5 mod 7 Thus,-CPI 2000 occurs when counters A, B, C and D are at states 0, 2, 0 and 5 respectively. These states are represented by state 0000 of Al A4, state 200 of B1 B3, state 00 of Cl and C2 and state 5 of D. Thus, CPI can be detected by ANDing lines 0, 0, 0,, 0 2, 0 0 0 0 and 5 in an appropriate AND gate (not shown).

From the foregoing, it is thus seen that the arrangement of FIG. 6 for M 75,600 is capable of providing any of 118 subperiods of M as well as any delayed subperiod. It is further capable of being used to identify any particular CPI in the frame. Furthermore, based on the states of the counters A, B, C and D, the CPI at which such states occur can be determined by the Chinese Remainder Theorem. It should be apparent that any of the counters A D can be implemented with ring counters. CounterA requires 4 Z-stage ring counters, counter B requires 3 3-stage ring counters and counter C requires 2 5-stage ring counters. Counter D is a single 7-stage ring counter. Thus, a total of 34 stages are needed.' This compares with 75,600 stages that would be required in the prior art if it were implemented by a 75,600-stage ring counter. Also, with the present invention, a minimum amount of decision logic is needed. The largest AND gate necessary is one with 10 inputs. In the prior art, to obtain a subperiod of 2 CPIs from a ring counter of 75,600 stages, a gate with 37,800 inputs is needed.

It should be apparent that any of the counters shown in FIG. 6 may be implemented as a multistage ring counter. For example, counter D may be implemented by a 7-stage ring counter, designated by numeral 40 in FIG. 8. It is shown in state 0 since a binary 1 is shown stored in the leftmost stage and all the other stages store binary 0s. As the counter is clocked, the 1 ad vances from stage to stage thereby cycling the counter through its states.

Conventionally, the output of the last stage is fed back to the first stage. Preferably, however, the assertion outputs of all the stages except the last are connected to a NOR gate 42, whose output is connected to the input of the first stage. This insures proper setting of the counter after not more than one complete cycle. As long as any of the first five stages holds a 1, a0 is stored in the first stage. Only when all the first five stages store 0's is a l stored in the first stage at the next clock period.

I In the present invention, when the system is turned on, all the ring counters are reset to their 0 states by storing ls in the first stages of the various counters. Thereafter, the shifting of the ls in the counter is accomplished by clocking the counters with the pulses from the master clocks. If during turn on, any stage except the first stage is inadvertently set to binary l state, the error will be eliminated after the first complete cycle by means of NOR gate 42. If the negation outputs of all the stages, except the last, are used, NOR gate 42 is replaced by a AND gate.

As previously pointed out, the modulo-p counters shown in FIG. 6 need not be limited to ring counters. They may be implemented by minimum stage feedback shift registers (FSRs). This may result in fewer memory cells at the price of more complex decision logic. For example, each of the counters B1, B2 and B3 which is a modulo-3 counter may be implemented by a 2-stage FSR, interconnected to cycle through 3 states. The unused state is always driven into the desired cycle of states.

FIG. 9a is a block diagram ofa 2-stage FSR which cycles through 3 states, as shown in FIG. 9b. It is assumed to represent counter B1. The two stages of the FSR are designated by S1 and S2. Each is a l-enable JK flip flop whose characteristic equation is Q J,,' K where J and K are l-enable inputs, q and Q are the present and next state, respectively and the designates complementation.

As seen from FIG. 9b, the combined states of S1 and S2 of 00, and 01 represent states 0, l and 2 of the FSR acting as a modulo-3 counter. The combined state of II for S1 and S2 is inhibited from occurring. It is generally referred to as an unused state. It is clear that to derive these states, decision logic is necessary. This is represented by the logic circuitry shown in FIG. 9c. The inputs of AND gate 51 are connected to the negation outputs b and b of S1 and S2, respectively. Its output is directly connected to counter output terminal 0, Only when both S1 and S2 are in the 0 state is a true output provided by the gate 51, thereby indicating that the counter is in state 0. The assertion output b of S1 is connected to counter output terminal 1 It is true only when S1 is at a 1 state, indicating that the counter is in state 1. Similarly, the assertion output of S2 is connected to counter output terminal 2 It is true only when S1 is in state 1, indicating that the counter is -in state 2.

It is thus seen that the modulo-3 counter, Bl, can be implemented by either a 3-stage ring counter or a 2- stage FSR. The ring counter of 3 memory stages does not require decision logic such as gates 51-53, to determine the state of the counter. However, the 2-stage FSR. which requires one memory stage less than the ring counter, requires such logic. Thus, the trade off is between less memory stages at the price of more decision logic.

In order to complete the description of the implementation of the counters shown in FIG. 6 with minimum stage FSRs, FIGS. 10a, 11a and 12a are included herewith. They represent diagramsof FSRs which cycle through 2, 5 and 7 states, respectively, as shown in FIG. 10b, 11b and 11c. Thus, the FSR of FIG. 1011 can be used for each of the modulo-2 counters of counter A. It does not require decision logic since its outputs b and b respectively, represent the O and 1 states of its single stage S1. The FSR shown in FIG. 11a can be used together with decision logic (not shown) as any of the counters forming counter C, and the FSR shown in FIG. 12a can be used together with decision logic as counter D.

As previously pointed out, the implementation of the system shown in FIG. 6 with ring counters requires 34 storage stages. When implemented with FSRs, such as those shown in FIGS. 9a-l2a, it requires only 3+3+3+2+2+2+l+l+l+l=19 storage stages. However, the reduction of 15 storage stages is achieved at the price of decision logic, which is needed to decode the combined states of the stages of the FSRs into the discrete states of the counters. Thus, the present invention may be implemented with either ring counters or FSRs, depending on the designers choice. Indeed the present invention may be implemented with any circuit design technique which provides modulo-p, counters where p, is any distinct prime of a number, M.

Summarizing the foregoing description in accordance with the present invention, any nontrivial subperiod or delayed subperiod of a data frame whose length is equal to M clock pulse intervals can be derived by providing parallel modulo-m, counters, where each m is a prime power factor (or divisor) ofM. In the last described example, i= 1, 2, 3 and 4 where m 2, m 3 m 5 and m 7. Thus, four parallel counters are provided of moduli numbers of 2 16, 3 27, 5 25, and 7 7. Each modulo-m,- counter is decomposed into a cascade of or, identical modulo-p,- counters, where m, p The term p,- is a distinct prime of M and a, is the power to which p,- is raised to equal m,-. Thus, the modulo-2* counter (counter A) is decomposed into a cascade of 4 modulo-2 counters, (A1-A4), the modulo-3 counter (counter B) is decomposed into 3 modulo-3 counters (B1B3), and the modulo-5 counter (counter C) is decomposed into 2 modulo-5 counters (C1 and C2). The modulo-7 counter (counter D) is a cascade of a single modulo-7 counter. All the modulo-m,- counters are clocked synchronously by the clock pulses from a master clock. However, as pointed out herebefore in each cascaded modulo-m counter each of its modulo-p counters except for the first is clocked only when the preceding modulo-p, counter in the cascade changes from its highest state of a cycle to the first state in the cycle. Thus, for example, in counter A, counter A2 is clocked only when counter A1 changes from state I to state 0. Similarly, counter B2 of counter B is clocked only when counter B1 changes from state 2 to a state 0.

It should be appreciated that the present invention is not limited to the values ofM herebefore used as examples. As is known, the Fundamental Theorem of Arithmetic states that every number can be factored as a product of powers of primes, unique except for order. Therefore, as long as M is not a prime, any number M can be factored and implemented as herebefore described. Thus, a modulo-M counter can be decomposed as taught herein. For example, for M 14,817,600 since it can be decomposed by an arrangement just like that shown in FIG. 6 except that counter A would consist of a cascade of 6, rather than 4, modulo-2 counters and counter D would consist of a cascade of 3 modulo- 7 counters rather than the single modulo-7 counter shown in FIG. 6.

Herebefore reference was made to the Chinese Remainder Theorem which was used in one example to determine the number of CPIs from the start of the data frame needed to produce a particular combination of states of the various counters. This theorem is well known by mathematicians. One reference to it is made in Topics in Number Theory, Volume l by W. J. Le- Veque, published in 1956 by Addison-Wesley Publishing Company, Reading, Mass. However, for purposes of completeness, the theorem will be discussed herein.

The Chinese Remainder Theorem guarantees a unique solution for simultaneous congruences over moduli which are relatively prime by pairs. The theorem may be stated as follows:

Every system of linear congruences in which the moduli are relatively prime in pairs is solvable, the solution being unique modulo, the product of the moduli. Given the simultaneous congruences mod m mod m .r 11,, mod m,,

Since (M,, m,-) l, a unique solution exists for y,

in the linear congruence M 1: l mod m, for all i There is one and only one solution for x, which is determined as follows:

i a y M mod M Note that, as expressed in the above expression, x is a solution of each congruence in the expression x a,, modulo m,,.

a y M i a,- mod m,-

E mod m,-, wherej i The latterresults since m, is a factor of M The value ofx is such that 0 s X M.

As an example let it be assumed that M 20, M 15, M 12 y 1 mod 3 l5y l mod 4 l2y E 1 mod 5 Unique solutions for y y and y are 2, 3 and 3, respectively.

.r 5 (a a 36:2 mod 60 .r (4O-l+45-2+36-3)mod60 .r E 58 mod 60 Check 58 i 1 mod 3 58 2 mod 4 58 3 mod 5 A modulo-3, a modulo 4, and a modulo-5 counter would be in state 1 2 3 (i.e., a 1, a

2 and a 3) for n 58 +k6O CPI, where k 0,1, 2, State 1 2 3 repeats every 60 CPls.

Although particular embodiments of the invention have been described and illustrated herein, it is recognized that modifications and variations may readily occur to those skilled in the art and consequently it is intended that the claims be interpreted to cover such modifications and equivalents.

What is claimed is:

l. A system comprising:

clock means for providing a succession of clock pulses of equal clock pulse intervals, each sequence of M clock pulse intervals defining a data frame, M being an integer other than a distinct prime and not less than one thousand;

a plurality of modulo-m, multistage counters where each m, is a different prime power divisor of M, each modulo-m, counter comprising a different cascade of a modulo-p,- counters, where p, in each cascade is the same and is a different distinct prime of M and a,- in each cascade is an integer not less than 1, with at least one a, being greater than 1 and each m,-=p,-

means for coupling said counters to said clock means for clocking said modulo-m counters in parallel with said clock pulses, with the first counter in each cascade being clocked directly with each clock pulse and each succeeding counter in a cascade is clocked by a clock pulse only when the preceding counter in a cascade changes from a last state in its state cycle to a first state in its cycle whereby each modulo-p,- counter cycles through a cycle of p, states and the combined states of the a; counters forming each modulo-m,- counter represent different states of a state cycle of m,- states; and

logic means coupled to selected ones of said counters for providing a plurality of subperiods of said data frame as a function of the states of the counters to which it is coupled, each subperiod being a sequence of output pulses, each with an output pulse interval which is equal to the clock pulse interval times a different factor definable as X,, where X, is an integer and a factor of M and wherein the smallest value of X, is equal to the smallest distinct prime of M, said subperiods including one delayed subperiod whose first output pulse is delayed by an in terval from the start of said data frame, which is not less than one clock pulse interval and not greater than Y clock pulse intervals, where l S X,- l.

2. A system as described in claim 1 wherein M includes at least two prime power divisors definable as m and m wherein m; p, p being a distinct prime ofM and a, is an integer greater than 1 and saidplurality of counters includes a modulo-m counter and a modulo-m counter, said modulo-m counter comprises a cascade of at, identical modulo-p counters, each of said modulo-p counters cycling through a cycle of p, states.

3. A system as described in claim 2 wherein m p where p is a distinct prime of M other than p, and a is an integer greater than 1, said modulo-2 counter comprises a cascade of a modulo-p counters each cycling through a cycle of p states.

4. A system as described in claim 3 wherein said modulo-m counter includes logic means for controlling each of said modulo-p counters except for the first in said cascade of a, counters to be clocked only when a clock pulse is received from said clock means and the preceding modulo-p counter in the cascade changes from the highest state in its p state cycle to the first state of the state cycle, and said modulo-m counter includes logic means for controlling each of said modulop counters except the first in said cascade of a counters to be clocked only when a clock pulse is received from said clock means and the preceding modulo-p counter in the cascade changes from the highest state in its p -state cycle to the first state of the state cycle.

5. A modulo-M counter, where M is an integer other than a distinct prime and is not less than one thousand, comprising:

a plurality of parallel modulo-m,- multistage counters, each m,- being a prime power divisor of M, i=1 through n where n is not less than two, each m,- counter including a cascade of or,- identical modulop, counters where m,- p where each p is a different distinct prime of M and is the same in each cascade and each a,- is an integer not less than 1, at least one a, is not less than 2 with the total number of stages of all of said counters being not greater than the sum of am,- of all the cascades, and is less than M;

means for clocking in parallel said plurality of modulo-m, counters with each clock pulse in a sequence of clock pulses of equal intervals, with the first counter in each cascade being clocked directly by each clock pulse and each succeeding counter in a cascade being clocked by a clock pulse only when the preceding counter in the cascade changes from a last state in its cycle to a first state in its cycle, whereby each modulo-p; counter cycles through a state cycle of p, states and the combined states of a,- counters forming each modulo-m,- counter represent different states of a state cycle of m,- states; and

output means coupled to selected stages of selected counters of said plurality of counters for providing at least one output when said selected stages of said selected counters are in preselected states, said one output being a sequence of output pulses at an interval which is equal to the clock pulse interval times a factor X where X is a factor of M and the first output pulse occurring at a delay interval from a time when all of said counters are at their first states, said delay interval being equal to the clock pulse interval times a factor Y where l Y X-I, both Y and X being integers.

6. A modulo-M counter as described in claim 5 wherein M is equal to the product of at least two prime power divisors, definable as m, and m m, p where p is a distinct prime and a, is an integer greater than 1, and m p where p is a distinct prime other than p, and a is an integer not less than I, said modulo-M counter including a first cascade of a modulo-p counters each modulo-p counter cycling through a cycle of p, states, with the combined states of said a, modulo-p counters representing a cycle of m states, and a second cascade of a modulo-p counters, each modulo-p counter cycling through a cycle of p states, and logic means coupled to at least a plurality of the counters in the group including said modulo-p and modulo-p counters for providing an output for every M'th clock pulse where M is less than M and is equal to p za p 4 where a is an integer not less than 1 and a, is an integer not less than 1.

7. A modulo-M counter as described in claim 6 wherein each of said modulo-p counters is a p -stage ring counter.

8. A method for producing a selected output pulse related to a data frame represented by M clock pulse intervals of a succession of M equal interval clock pulses, M being an integer not less than one thousand and other than a distinct prime and is equal to the product of n prime power factors definable as m, through m,,, where n is at least equal to 2, the steps comprising:

providing a first cascade of a, modulo-p counters where m p t p being a distinct prime and being the same in each counter of said first cascade and a, is an integer greater than 1;

providing at least a second cascade of a modulo-p counters where m;, 12 p being a distinct prime different from p, and the same in each counter of said second cascade and a is an integer greater than I;

clocking said first and second cascades of counters with equal interval clock pulses, with the first counter in each cascade being clocked directly by each clock pulse and each preceding counter in a cascade being clocked by a clock pulse only when the preceding counter in the cascade changes from the last state in its state cycle to the first state in its cycle, whereby each modulo-p counter cycles through a cycle of p states, with the combined states of said a, modulo-p counters representing a cycle of m states, and each modulo-p counter cycles through a cycle of 1 states with the combined states of said 01 modulo-p counters representing a cycle of m states; and

utilizing the states of selected stages of all of said counters to provide a selected output pulse during each data frame, at a time from the start of said data frame which is an integer multiple of said clock pulse interval.

9. A modulo-M counter, where M is an integer other than a distinct prime and is not less than one thousand, comprising:

a plurality of parallel modulo-m, multistage counters, each m,- being a prime power divisor of M, i=1 through n where n is not less than two, each m,- counter including a cascade of or, identical modulop,- counters, where m,- p where each p is a different distinct prime of M and is the same in each cascade and each a,- is an integernot less than I, at least one a, is not less than 2 with the total number of stages of all of said counters being not greater than the sum of mp of all the cascades, and is less than M,-

means for clocking in parallel said plurality of modulo-m, counters with each clock pulse in a sequence of clock pulses of equal intervals, with the first counter in each cascade being clocked directly by each clock pulse and eachsucceeding counter in a cascade being clocked by a clock pulse only when the preceding counter in the cascade changes from a last state in its cycle to a first state in its cycle, whereby each modulo-p, counter cycles through a state cycle of p, states and the combined states of the a,- counters forming each modulo-m,- counter represent different states of a state cycle of m, states; and

output means coupled to a selected stage of each of said counters for providing a single output pulse which is delayed by X clock pulse intervals from an interval when all of said counters are in their first state, X being an integer where X a! a modulo m 5: a, modulo m,

a a,, modulo m,

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Classifications
U.S. Classification377/44, 377/108, 377/52
International ClassificationH03K5/15, G06F1/04
Cooperative ClassificationH03K5/15093, G06F1/04
European ClassificationG06F1/04, H03K5/15D6S