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Publication numberUS3866175 A
Publication typeGrant
Publication dateFeb 11, 1975
Filing dateApr 24, 1974
Priority dateApr 24, 1974
Also published asDE2517831A1, DE2517831B2, DE2517831C3
Publication numberUS 3866175 A, US 3866175A, US-A-3866175, US3866175 A, US3866175A
InventorsJr Joel H Hinrichs, Jr Lloyd R Seifert
Original AssigneeNcr Co
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Data communication system between a central computer and a plurality of data terminals
US 3866175 A
Abstract
A system for communicating data between a central processor and a plurality of remote interactive data terminals over a single channel. A controller coupled to the channel generates each poll message to a designated terminal by selectively utilizing the output of an address generator. A recirculating shift register whose output signifies whether a terminal is active or inactive is synchronized with the operation of the address generator to allow the controller to poll only those terminals which are active. Each terminal will test the address portion of each poll message to determine for what terminal the message is intended. The polled terminal is required to respond within a predetermined time frame before the next active terminal is polled. In exchanging data with a terminal, the controller will include in the output message a sub-address format indicating to what functional area of the terminal the message is intended.
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Description  (OCR text may contain errors)

United States Patent Seifert, J r. et al.

[ Feb. 11, 1975 DATA COMMUNICATION SYSTEM BETWEEN A CENTRAL COMPUTER AND A PLURALITY OF DATA TERMINALS Inventors: Lloyd R. Seifert, Jr., Cambridge;

Joel H. Hinrichs, Jr., Pleasant City, both of Ohio Assignee: NCR Corporation, Dayton, Ohio Filed: Apr. 24, 1974 Appl. No.: 463,627

US. Cl. 340/152 R, 340/151 Int. Cl. H04q 5/00 Field of Search 340/151, 152 R, 147 LP,

340/149 A; 179/2 DP, 2 CA References Cited UNITED STATES PATENTS /1971 McNaughton 340/152 R Primary Exanzirier-J-Iarold I. Pitts Attorney, Agent, or Firm-J. T. Cavender; Wilbert Hawk, Jr.; Richard W. Lavin [57] ABSTRACT A system for communicating data between a central processor and a plurality of remote interactive data terminals over a single channel. A controller coupled to the channel generates each poll message to a designated terminal by selectively utilizing the output of an address generator. A recirculating shift register whose output signifies whether a terminal is active or inactive is synchronized with the operation of the address generator to allow the controller to poll only those terminals which are active. Each terminal will test the address portion of each poll message to determine for what terminal the message is intended. The polled terminal is required to respond within a predetermined time frame before the next active terminal is polled. ln exchanging data with a terminal, the controller will include in the output message a sub-address format indicating to what functional area of the terminal the message is intended.

Claims, 11 Drawing Figures 3 27 66 I e5 l TERMINAL TERMINAL 355652 USEIDTA I KEY BOARD MODULES LOGIC 5 I64 3Av 36 8 1 I75 70 l 49 48 MODULE BIT-/ I l I 47 GENERATOR 6O 33 n: g l TRANSMIT/ I l 4 I; E INMODE SEND-RECEIVE DATA 1 CPU ROM 9 INMODE iREeIsTER 7 LOGC 4O I as n: I52 I53 --34 a: 150 I 58 72 l I3 32 43 l MODULO I T SYNC CRC Io BIT BUSY E L HAND DETECTOR G'EN \COMP CHECKER I I5 TOTAL o v 54 SMHZ CLOCK c REGISTER T42 i 154 s? IeI T l GENERATOR C2 4 CLOCK cc N- ERRoR BUSY Y TROL LOGIC 3 DETECT BATTERY Elsa BUSY M CONTROL SEQUENCE I71 GENERAL I70 l66 CONTROL GDRESP I FIG. 4

[8 BIT I8 BlT l 3BIT 4BIT f ORG DATA [sue-ml ID FUNCTION cu 1 DATA COMMUNICATION SYSTEM BETWEEN A CENTRAL COMPUTER AND A PLURALITY OF DATA TERMINALS BACKGROUND OF THE INVENTION The present invention is directed to high speed data processing systems and more particularly to a high speed communication system to effect the transfer of data between a plurality of data handling devices and a data processor wherein the data handling devices are connected to a common bus for transmitting and receiving information. In systems of this type, a plurality of data terminals or other types of I/O devices are connected to a central computer by communication lines. The central computer will poll each of the terminals asking for information. The terminal, when polled, will respond by transmitting information generated at the data terminal or by a response indicating that it has no information to send. The terminal may not respond at all if it has been disconnected from the system or is disabled.

Most data terminals will store the information generated until the terminal receives a poll message. In reply to this poll message, the terminal will transmit the stored information to the central processor. In order to reduce the cost of systems of this type, data terminals of the interactive type have been developed. The interactive terminal depends on the central processor for all of its application orientated functions. One drawback to this arrangement is the need ofa large capacity central processor to accommodate the servicing of the terminals. In order to soften this effect on the cost of the system, controllers have been developed to share the polling operation with the central processor. But all of these systems require the processor to control which terminals are to be polled prior to each polling sequence. There is still a need for a device which controls the polling of the terminals which is simple in construction, low in cost and allows the central processor to perform its assigned operations without being concerned with the direct polling operation of the data terminals. It is therefore a principal object of this invention to provide a communication system for polling a plurality of remote data terminals which reduces the involvement of a central processor in the polling procedure to a minimum. It is a further object of this invention to provide a communication system for polling a large number of terminal devices which is relatively simple in operation and construction and therefore low in cost. Another object of this invention is to provide a communication system in which only those terminal devices which are capable of responding to a poll signal will be polled, thus reducing the time of a polling sequence to a minimum. It is a further object of this invention to provide a communication system in which data can be transferred between terminals and a central processor in a minimum amount of time.

SUMMARY OF THE INVENTION In accordance with these objects of the invention, there is provided a communication system which includes a controller device for generating polling messages to a plurality of addressable data terminals. The controller device includes means for storing a table of addresses of all of the terminals that are in the system. Means are provided in the controller device to select only those addresses of the terminals which are to be polled and in the order in which they are to be polled. The selecting means is constantly updated by a Central Processor as to what terminals are active in the system at the time of a polling operation. The communication system requires the terminal to answer a poll message. Upon failure of the terminal to answer a number of poll messages, the selecting means will be updated by the Central Processor as to what terminals are active. In answering a poll message, the terminal may transmit a data message which includes message identifiers which identify from what functional areas of the terminal the data is generated. In transferring data to the terminal, these same message identifiers allow the data to be transferred directly to the functional area of the terminal to which the data is intended.

The foregoing and other objects, features and advantages of the invention will be apparent from the following illustrated in the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is an oblique view of the terminal used in the system.

FIG. 2 is a block diagram of the data processing system showing the major elements of the system.

FIG. 3 is a diagram of the connecting block used to connect a terminal device into the communication system.

FIG. 4 is a diagram of the message format used in the communication system.

FIGS. 5a, 5b, and 5c taken together form a more detailed block diagram of the system showing a terminal and the controller.

FIG. 6 is a more detailed block diagram of the presence register and the ID counter.

FIG. 7 shows the waveform of several clock pulses utilized in the present invention.

FIG. 8 is a flow diagram showing the sequence of events which occurs in the communication adapter during a poll operation.

FIG. 9 is a flow diagram showing the sequence of events which occur in the terminal during a poll operation.

DESCRIPTION OF THE PREFERRED EMBODIMENT GENERAL ARRANGEMENT OF THE SYSTEM Referring to FIG. 2, there is shown a block diagram of the data processing system of the present embodiment. The system includes a controller 21 in which is located a central processor (CPU) 22, and up to ten communication adapters 23 that interface the CPU with the I/O devices. Connected to each communication adapter (CA) 23 by means of a 4 wire twisted pair cable 24 are a number of I/O devices 25. In the present configuration, each communication adapter can handle up to sixteen I/O devices. The majority of these devices are interactive data terminals in which data is entered and transmitted to the CPU which processes and updates the data.

The processing of the data in the controller is under the control of software located in the controller. The software consists of executive programs, input/output control routines and application programs. The executive programs control the overall operation of the system. These programs determine the sequence in which application programs and I/O routines are executed and monitor the overall status of the system. The input- /output control routines act as the interface between the terminals, I/O devices, and the application programs. The 1/0 routines monitor the input line to controller for input activity. Any input data is buffered and the I/O routines signal the application programs that data is present. The 1/0 routines are also responsible for routing data from the application programs to the appropriate terminal or I/O devices. The application programs are responsible for handling data from the terminals to the controller in a manner that satisfies the users requirements. For example, the application programs ensure that a transaction item is added to the proper itemizers, department totals, checker totals, etc. These programs also control the operation of terminal print and display modules.

In the system of the present embodiment where the I/O devices are data terminals of the type shown in FIG. 1, the processed data will be transmitted from the CPU to a designated terminal where it will be incorporated into the various functional areas of the terminal, i.e., display, printer, mode, etc. Each terminal is connected into the 4 wire cable system by means of connecting blocks 26 (FIG. 2), thus facilitating the installing and the removal of each terminal from the system. In addition to data terminals, other I/O devices that may be installed into the system include device controllers to which may be connected such devices as Slot Scanners, Automatic Scales and Magnetic Credit Card Readers. To each data terminal may be connected Stamp and Coin dispensers and Remote Display devices.

Communications between the controller 21 and any data terminal 25 are performed over cable 24 (FIG. 2). As shown in FIG. 3, each terminal 25 is connected by means of screws into the connecting block 26 over wires 11. The twisted 4 wire cable 24 is seen from FIG. 3 as being continuous through each terminal of the system. The terminals are tapped into the wire system over connector 12. Any message transmitted by the controller 21 is addressed to a particular terminal 25 although the message is sampled by every terminal connected to the cable 24. Accordingly, only the addressed terminal accepts and responds to the controller message. All data exchanges are initiated on a characterby-character basis by and under the control of the controller. If a terminal has data to transmit, it must store the data until requested by the controller. Communications between the controller and the terminals are digital using single message front. A message from the controller requires a response from the terminal in the same message format. Although the message format does not change, the purpose of a message may be different. A message from the controller can be categorized as a Poll, Repoll, Exchange or Re-exchange. A response to a message from the controller from the terminal is either a Data or No-data message.

A poll message from the controller indicates that it is requesting data from the terminal. This message requires a Data or No-data response message from the terminal. A repoll message from the controllerindicates that the terminal response for the previous poll or repoll message was late, invalid or nonexistent due to a transmission error from the terminal to the controller. The repoll message also requires a terminal Data or No-data response. An exchange message from the controller indicates that the message contains an instruction for the terminal to perform. The terminal must respond to the exchange message with a Data or No-data response message. A re-exchange message indicates that the terminals response to the previous exchange or re-exchange message was late or invalid for the reasons stated above. Again, the terminal must respond with a Data or No-data response message.

A Data response message from the terminal indicates that the message contains one of three types of data characters, a keyboard data character, a status data character or a hard total character. A No-data response indicates that the terminal has no data to send.

The message format is shown in FIG. 4. This message format is the same in both directions as between the terminal and the controller. The entire message is 34 bits in length and includes 8 sync bits, I modulo bit, 2 function bits, 4 terminal identification bits, 3 subidentification bits, 8 data bits and a cyclic redundancy check character. The sync bits are premessage identitiers and are an alternating 1 and 0 pattern. The modulo bit is a message number and alternates between 1 and 0 for each exchange message transmitted by the controller and each data response message transmitted by the terminal. If successive data messages are received with the same modulo number, the terminal or controller rejects the second message as being invalid. The controller does not transmit an alternating modulo bit on poll messages, while the terminal does not transmit an alternating modulo bit on No-data messages.

The function bit defines the type of message being transmitted by or to the controller in accordance with Table I.

The ID bits identify-the terminal that the controller message is intended for. Response messages transmitted from a terminal contain the ID of that terminal. The Sub-ID bits perform two functions. In exchange messages from the controller, the Sub-ID bits are used to identify the terminal module (printer, display, change and stamp dispenser, etc.) which is to act on the 8-bit data character in the message. In messages transmitted by the terminal, the Sub-ID bits are used to identify the type of data in the message (keyboard data, status data or hard total data). In an exchange message, the data character may contain data to be printed or displayed, or it may contain functional tasks for a module of the terminal to perform. The Sub-ID and the data character portions are the data carrying portion of the message with the SubID being employed as a routing control value meaningful to the modules of the terminal and to the software in the controller. The CRC character is added by both the controller and the terminal for testing the correctness of the message in a manner well known in the art.

Referring now to FIGS. 5a, 5b and 5c taken together, there is shown a block diagram of the components forming the communication system between a data terminal and the controller. FIG. 5a and a portion of 5b is directed to the data terminal, while the remaining portion of FIG. 5b and FIG. 50 is directed to a communication adapter 23 located in the controller 21. The terminal 25 (FIG. 1) is of conventional design having a 52 key keyboard 27 consisting of numeric and 42 function keys, a printer 28, a l6-LED status display 30 and an S-digit numeric display 31. The terminal can opcrate in both an on-line and off-line mode. In the offline mode, all entries made in the keyboard will acid into a hard total 42 (FIG. 5a) which is maintained by a small battery 44.

In the following description of FIGS. 5a, 5b, and 5c, the block diagrams represent circuitry that may be constructed with well known principles and dataprocessing techniques. For example, the usual decode eircuits comprise a conventional interconnection of logic elements such as AND, NAND, OR, or NOR gates. When certain conditions exist, the outputs from these gates are applied to still further AND, NAND, OR or NOR gates to yield an ouput signal indicating the logical conditions that exist at the input to the decode circuit. Similarly, shift registers, counters, and compare logic circuits are well known in the art. Examples of these circuits may be found in such standard texts as Digital Computer Components and Circuits by R. K. Richards, Digital Computer Design Fundamentals by Y. Chu, Planning a Computer System by W. Buchholz, Digital Computer and Control Engineering by Robert S. Ledley and Analog and Digital Computer Technology by R. N. Scott. In addition, reference may be had to U.S. Pat. No. 3,789,364 issued to D. 1. Moses on Jan. 29, 1974 and assigned to the assignee of the present invention for a description of the flip-flops, latches and multivibrators which are disclosed in the present invention.

As shown in FIG. 5a, each terminal contains a microprocessor 32 which is coupled to the keyboard 27 of the terminal. The micro-processor 32 is a selfcontained 4-bit general purpose computer that is composed of a central processing unit (CPU), an array of ROMs 33 for storing program data, data tables and instructions and an array of RAMs 34 for storing general data. The micro-processor is operated by clock pulses in a manner well known in the art over line 13 from a 5 Mhz Clock-generator 14. The Clock generator 14 also produces l.25 Mhz clock pulses (C over line and 2.5 Mhz clock pulses (C over line 16 for use in transmitting a terminal message to the controller and for receiving messages from the controller as will be explained more fully hereinafter.

The micro-processor 32 is coupled over a plurality of input lines represented by line 38 to an 8-bit Parallel to Serial Pre-data shift register 40 for storing data from the keyboard. Also coupled to the Pre-data register 40 over lines 41 is a Hard Total register 42 which is capable of storing eight 4-bit characters. In the event of a power failure, or for any other reason where communication is lost with the controller, the terminal has limited keyboard and total storage capability. When the terminal goes off-line, the micro-processor 32 will assume the function of the controller and will transmit positive totals generated by operation of certain numeric and function keys on the keyboard 27 to the hard total register 42 over line 43. The hard total register 42 is powered by a battery 44 during the time power is off to the system. The battery can hold a charge for up to 10 days and is rechargeable under software control in the controller. The hard total register 42 is a storage register only and functions solely in the terminal offline mode.

During the off-line mode, the micro-processor 32 performs all hard total calculations and stores the results in the RAMs 34. As part of this latter operation, the micro-processor will read out the existing hard totals from the Hard Total register 42 over line 41, through the Pre-data register and over line to the micro-processor 32. Thereafter, all positive off-line item entries from the keyboard 27 are added to the hard total stored in the micro-processor. When the transaction is totalized, the updated hard total is transferred over line 43 to the Hard Total register 42. After power has been restored, the hard total in the register 42 is transmitted to the Pre-data register 40 over line 41 and then to the controller for updating. During this transmission, the hard total is recirculated over line 46 back to the Hard Total register 42 so that the hard total is not lost during the latter operation.

The Pre-data register 40 is coupled over line 47 through AND gate 48 to a 20 bit Send-receive shift register which stores data received from the Pre-data register 40. During transmission of this data to the register 50, the data is recirculated over line 49 back to the Pre-data register 40 for storage in case the data is lost in transmission to the controller. It is also in the Send- Receive register 50 that the Response message from the terminal is assembled. As will be described more fully hereinafter, the register 50 functions to store poll or exchange messages from the controller. As part of this latter operation, there is associated with the register 50 a Sync detector 51 for detecting the first eight bits of the poll or exchange message from the controller that is loaded into the register 50. Detecting the proper sync bits of the controller message allows a clock control 52 to provide a 1.25 Mhz clock signal to turn on a Program Sequence counter and control 53. The sequence counter 53 allows the terminal to receive a poll or exchange message from the controller and to format a terminal response message to the controller message in an orderly and logical manner. Operation of the sequence counter 53 will be described hereinafter.

All communications between each terminal and the controller is initiated by the controller by the sending of a poll or exchange messsage. The controller message is sent to each terminal and will be loaded into the Send-Receive register 50 resulting in the operation of the Sequence Counter 53 as described above. Continued clocking of the Send-Receive register 50 by the Sequence counter 53 loads the remainder of the received message from the controller 21 into the register 50 minus the CRC character. Coupled to the Send- Receive register 50 is an ID comparator 54 which compares the terminal ID with the message ID to determine if the message is for this particular terminal. If there is no comparison, indicating that the controller message is not intended for this terminal, the comparator 54 generates a signal over line 161 to an error detector 55 which sets a General reset latch 56 resetting the terminal logic.

In addition to the Send-Receive register 50, the received message is loaded into a CRC generator 57 for formulating a CRC character based on the received message. Subsequently the CRC character contained in the received message is shifted into the CRC generator 57 from the register 50 over line 156 for comparison with the CRC character formulated by the generator.

If the CRC characters do not compare, the CRC generator will generate a signal over line 157 to the error detector 55, thereby resetting the terminal logic.

In the case of terminal response messages, the CRC generator 57 will generate a CRC character over line 58 to a Transmit Data control logic 60. This transmission occurs after the remainder of the terminal response message including sync bits from the Transmit Data logic 60 and the data bits have been shifted from the Send-Receive register 50 over line 61 through the Transmit Data control logic 60 to a Split Phase Manchester Encoder 62 and then to a transmitter 63. The Manchester Encoder 62 receives the 2.5 Mhz clock pulses (C from Mhz clock generator 14 (FIG. 5a) for use in transmitting the response message from the terminal 21 to the communication adapter 23. The Manchester Encoder 62 also generates a l.25 Mhz (C clock pulse for use in entering data received from the controller 21 into the terminal 25. The CRC character will then be transmitted to the Manchester Encoder 62 where the binary digital data is converted into a Manchester encoded format for transmission to the controller through the transmitter 63 over cable 24 (FIG. 1). For a more complete disclosure on Manchester Encoding, reference should be made to the text Digital Magnetic Tape Recording Principles and Computer Applications" by B. B. Bycer, published by the Hayden Book Company, 1965.

In the case of an exchange message from the controller, as the exchange message is loaded into the Send- Receive register 50, the Sequence counter 53 will clock the Sub-ID bits of the message over line 64 to a Sub-ID decode logic 65 which decodes the Sub-ID bits and supplies C clock pulses over one of a number of lines represented by line 66, each line 66 being connected to a module of the terminal. Only that module of the terminal designated by the Sub-ID bits of the exchange message will receive the clock pulses over line 66. The received data in the Send-Receive register 50 is then shifted over line 67 to all modules of the terminal but only that module previously designated by the Sub-ID decoder will act on the data. In the case where a terminal response message is being formulated in the Send- Receive register 50, the micro-processor 32 will insert the proper Sub-ID bits and the proper function bits into the terminal message over line 68. Also coupled to the Send-Receive register 50 is a Modulo bit generator 70 for generating a modulo number for insertion into the terminal response message. The terminal ID is wired over line 71 for automatic insertion of the ID bits into each terminal response message and also to the ID compare 54 so that the poll or exchange message from the controller can be identified as directed to this terminal.

With respect to controller messages, a modulo bit check logic 72 (FIG. 5a) is coupled to the Send- Receive register 50 over line 167 for checking the modulo bit of the exchange message. If there is an error in the modulo bit of the exchange message, a signal is generated over line 73 to the Error detect logic 55 which controls the General Reset latch 56 for resetting the terminal which in effect rejects the message.

The terminal response message is transmitted from the terminal transmitter 63 over cable 24 (FIG. 5b) to a receiver 74 (FIG. 5b) in an associated communication adapter 23 (FIG. 2) in the controller 21. The response message is clocked from the receiver 74 to a Manchester decoder 75 which decodes the response message into binary form characterized as received data. The decoder 75 also generates a Received clock (RC) (FIG. 7) of 1.25 Mhz o'ver line 134 which is used to clock the received data into the controller. The received data is transferred over line 76 to an Input control logic 77 and is then clocked by the received clock to an Input buffer 78 over line 80 and to a CRC generator 81 over line 82.

The CRC generator 81 will generate a CRC character on the received data being clocked into the input buffer 78 and compares this generated character with the CRC character of the received data which was clocked into the CRC register by the received clock over line 82. If an error is detected, an error signal will be generated in an Error detect logic 83 (FIG. 5b) which will be sent over line 84 to a Sequence control logic 85 (FIG. 50). As will be described more fully hereinafter, the activity of the controller in formatting a poll, repoll, exchange, or re-exchange message for transmission to the designated terminal and in receiving the response message from the polled terminal is under the control of a Sequence control counter 86.

The Sequence control logic 85 (FIG. 50) provides the proper control signals for stepping the sequence counter 86 (FIG. 5b) to the next sequence upon the fulfillment of the required pre-condition. With respect to this latter operation, the Sequence control logic 85 includes two 8-input multiplexers wired serially so that their combined inputs reflect the 16 possible states of the sequence counter 86. Each input is wired to the various control blocks in the communication adapter for sensing the signals generated within the block. These signals are preconditions which must occur in sequential order. When a selected input becomes active, the output of the multiplexer also becomes active, allowing the sequence counter 86 to advance. Incrementing the counter 86 selects the next input which in turn also allows the counter to advance when it becomes active, until an entire communications sequence has occured. In the present example, an error signal from the Error detect logic 83 (.FIG. 5b) to the sequence control logic 85 (FIG. 50) will reset the sequence counter 86 and condition the controller so that a repoll message will be sent to the terminal from the communication adapter indicating that the previous terminal response message was not a proper response. This operation will be explained more fully hereinafter.

Upon the shifting of the received data into the Input Buffer 78 (FIG. 5b), the sync bits of the received data are gated over line 87 to a Sync detector 88 which will raise the signal SYNDET for transmission to the Sequence control logic 85 (FIG. 5c) over line 90 when there is a correct configuration of sync bits in the Input Buffer 78. If the sync and the CRC characters of the received data are found valid, the Sequence counter 86 will gate the ID bits in the input buffer 78 to an ID comparator 91 over line 92 which has received the proper ID bits, from an ID register 93, of the terminal that was required to respond to the message from the communication adapter. If the ID bits are equal, the received data is transferred from the Input buffer 78 in serial form to a Data multiplexer 94 which transfers the received data in parallel form over a plurality of lines represented by line 96 to a Central Processing Unit (CPU) 95 (FIG. 50) for processing. The CPU 95 will process the data under control of the application program set up in the processor. After the CPU has processed the data, the CPU may put the communication adapter into an exchange mode as will be described hereinafter, whereby an exchange message will be sent to the terminal containing data for use by the terminal. This data may include display, print or mode instructions.

The CPU 95 controls the operation of each communication adapter by generating one of a plurality of control signals over three lines represented by line 99 to a Command Decode logic 97 (FIG. 5c) located in the communication adapter which decodes and interprets the control signal to put the adapter in a mode to perform one of eight commands that the communication adapter is capable of performing. Included in these commands is the requirement that the communication adapter enter into a poll mode, repoll mode, exchange mode, re-exchange mode, and an idle and configure presence register and clear ID counter mode. This last command will be described more fully hereinafter.

After the received data has been shifted into the CPU 95, the communication adapter will normally go into a poll mode as a result of a poll command signal being sent over line 99 to the Command decode logic 97 from the CPU. The Command Decode logic 97 (FIG. 50) includes a plurality of latches which are used in formatting a message to the terminal. Included is a poll latch 142 used to indicate when the communication adapter is in a poll mode. Also included in the Command Decode logic 97 are a Exchange latch 176 and a Retry latch 177 which are used to insert the proper function bits in the output message to the terminal. The Exchange latch 176 output is connected over line 178 to the Output buffer 113 (FIG. 50) to supply the function hit F (Table I) while the Retry latch 177 is connected over line 180 to the Output buffer 113 to supply the function F; (Table I).

When the CPU 95 transmits a command signal over line 99 for the communication adapter to go into a poll mode, the Output of the Latches 176, 177 will be 0. If an Exchange or Re-exchange is to occur, the latch 176 will have an Output of I. If a Repoll or Re-exchange is to occur, the Output of latch 177 will be 1. This operation is carried through for all the function bits shown in Table I. Upon decoding this poll command signal, the Decode logic 97 will generate a signal over line 98 to the Sequence control logic 85 which, by means of a control signal over line 100, initiates operation of the Sequence Counter 86. The Sequence Counter 86 is programmed for 16 counts of operation. The first two counts of the counter will sense whether a command signal from the Command Decode logic 97 to enter an idle mode or an exchange mode has been received by the Sequence Control Logic 85 since the start of a poll operation. At count 3, the Sequence Control 85 checks to see if an active ID is present in a presence register 101.

Referring to FIG. 6, there is shown a more detailed block diagram of the Presence register 101 and an ID counter 102. The presence register 101 consists of two 23-bit parallel to serial shift registers 103, 104 wired in series while the ID counter 102 is a 4-bit binary counter whose binary output is configured to the l6 different terminal or I/O device IDs that are connected to this communication adapter. Both the registers 103, 104 and the ID counter are clocked by a 1.25 Mhz data clock (DC.N) (FIG. 7) over line 133 when enabled. As shown in FIG. b, located in the controller is a 5 Mhz oscillator 17 which transmits a 2.5 Mhz clock over line 18 to a Manchester Encoder 124 which in turn divides the clock to produce a data clock (DC.N) of 1.25 Mhz over line 133 which is used in formatting an output message to the terminal. A second clock of 1.25 Mhz is used to transmit the output message from the communication adapter to the terminals.

Connected to the parallel load inputs of the registers 103, 104 (FIG. 6) are 16 parallel send data lines 106 (FIG. 50) which are connected to the CPU 95. The CPU 95 provides for the proper bit configuration on the lines 106 according to whether the terminal ID is active or inactive. If the bit is a one, the terminal ID is active. If the bit is zero, the terminal ID is inactive.

The output bit of the shift registers 103, 104 will appear on line 107 (FIG. 6) which is sensed by the Sequence Control logic in the form of the signal PR.F. This output bit is recirculated over line 109 back to register 103. If the signal PR.F is zero, indicating that the next terminal is inactive the Sequence Control logic 85 will generate the signal PCNT.GA over line 108 (FIG. 6) to the presence register 101 and the signal PCNT.G over line 110 to the ID counter 102. Signal PCNT.GA will allow a clock pulse over line 133 to shift the registers 103, 104 one position while the signal PCNT.G will allow the clock pulse to step the counter 102 to produce on its output lines 111 the ID of the next terminal or I/O device in binary form. The Sequence Control logic 85 will then reset the Sequence Counter 86 (FIG. 5b) over line 100. The Sequence Counter will then repeat counts 0, l and 2 to count 3 where again the presence register will be sensed over line 108.

If the next terminal ID is inactive as determined by the zero state of the term PR.F, this sequence will be repeated until the term PR.F becomes high indicating an active terminal ID. When this occurs, the Sequence Control logic 85 will generate a signal PLOD.Y over line 112 to the parallel to serial Output Buffer 113 (FIG. 50) enabling the buffer to be loaded with the ID bits from the ID counter 102. The loading of the ID bits occurs over line 111 through an ID Code Select logic 114 and over line 115 to the Output Buffer 113.

The ID Select logic 114 includes a multiplexer having one set of parallel inputs from the CPU represented by bus line 116 and another set of parallel inputs over line 111 from the ID counter 102. During a normal poll sequence, the ID bits from the ID counter 102 will be loaded through the ID Code Select logic 114 into the Output buffer 113 as described above. If the sequence was an exchange, the ID bits from the CPU 95 would be loaded into the Output buffer 113 over line 116, the ID Select logic 114, and line 115. In either case, the ID bits would also be loaded over line 117 into the ID register 93 to be used with the ID comparator 91 so that the message received and the message sent will be identified with the same terminal to insure that the correct terminal responded.

The signal PLOD.Y generated by the Control logic 85 over line 112 will also trigger over line 109 a usec. timer (FIG. 50). As will be described more fully hereinafter, the timer functions to set the time interval the terminal is required to respond to the controller message. The sensing of the term PR.F when in a high state also allows the Sequence Control logic 85 to increment the Sequence Counter 86 to count 4. The counter 86 is wired to immediately step to count 5. But

during count 4, a Transmit Counter 118 (FIG. b) is enabled. The transmit counter 118 includes serial to parallel shift registers which serve to count the message bits that are being transmitted or received by the communication adapter and to signal the Sequence control logic 85 over line 120 when a predetermined number of bits have been counted.

Enabling of the Transmit Counter 118 will generate a signal SYNCO.L over line 122 to an Output Control Logic 121 (FIG. 5b). The Output Control Logic 121 comprises a flip-flop and causes each portion of the output message from the Communication Adapter to be gated to an Output transmitter 123 through the Manchester Encoder 124 over line 125. Thus during count 4, the signal SYNCO.L over line 122 will toggle the Control Logic 121 with the DC.N clock over line 133 so that eight bits of sync will be shifted to the Manchester encoder 124 which in turn encodes the binary bits into the split phase Manchester code for transmission over the cable 24 to each of the terminals.

During count 5 time, the Transmit counter 118 is constantly being sampled by the Control Logic 85 over line 121 to determine when 8 bits of sync have been transmitted to the polled terminal. Upon completion of the sending of the 8 bits of sync, the Control logic 85 will disable the sync out logic of the Transmit counter 118, and raise the signal DATAO.L over line 126, from the Transmit Counter 118 to the Output Control logic 121 and over line 129 to the Output Buffer 113. If the Communication Adapter was in a Poll mode, the raising of the term DATAO.L would enable the Output Buffer 113 to send data over line 127 to the Output Control Logic 121, the data consisting of the terminal ID bits and the two function bits indicating that the message is a poll. The ID bits were received from the ID counter 102 through the ID Select logic 114 while the two function bits were received over lines 178, 180 from the latches 176, 177 located in the Command Decode Logic 97 which are set in accordance with the Poll command signal from the CPU 95 over line 99 as previously explained.

If the Communication Adapter was put into an Exchange Mode by the CPU 95, the Sequence counter 86 would step through the same counts as in a poll operation except it would skip count 3 since the terminal ID would be supplied by the CPU 95 together with the exchange data including the Sub-ID bits which are loaded into the Output buffer 113 (FIG. 50) over lines 116 and 119. During count 5, the term DATAO.L will enable the Output Buffer 113 to shift the data to the Output Control Logic 121 (FIG. 5b) under DC.N clock control. The data will also be shifted over line 128 to the CRC generator 81 for the generation of a CRC character. During this operation, the Sequence Control Logic 85 will step the counter to count 6.

During count 6, after 18 bits of data have been transmitted to the polled terminal, the Sequence Control Logic 85 will raise the term TCRC.Y over line 130 to the CRC generator 81 which causes the CRC character that was generated during the transmission of data from the Output Buffer 113, to be shifted over line 131 to the Output Control logic 121 and then to the addressed terminal for error checking. The TCRC.Y term from I the Control logic 85 will also reset the Input buffer 73 (FIG. 5b) over line 132 in anticipation of the response from the terminal. Also the counter steps to count 7.

During count 7, after 8 bits of CRC have been shifted out to the polled terminal, the Sequence Control logic will transmit a signal to the Sequence Control 86 over line which causes the sequence counter clock (CLK) to be transferred from the data clock (DC.N) over line 133 to the received clock (R.C.) over line 134. The signal also steps the counter to step 8 and disables the Transmit counter 118.

Step 8 of the Sequence Counter 86 conditions the communication adapter to receive a response from the polled terminal to the poll message just transmitted. As described previously, the response message will be transferred from the receiver 74 (FIG. 5b) of the communication adapter to the Input buffer 78 after the CRC character of the message has been checked by the CRC generator 81. During count 8, the Sync Detector 88 will generate the signal SYNDETGA over line 90 to the Sequence Control logic 85 indicating that the message from the polled terminal is being shifted into the Input buffer 78 and that the sync bits of the receiver data are in the correct configuration. When this occurs, the Control logic 85 will generate a signal over line to the CRC generator 81 and line 100 to the sequence counter 86 and the Transmit counter 118 enabling the CRC generator 81 and the Transmit counter 118 and advancing the Sequence counter 86 to count 9.

During count 9, the Transmit counter 118 (FIG. 5b) will count 18 bits of the received data of the response message that is being loaded into the Input buffer 73. At the end of count 9, a signal from the Transmit counter 1 18 over line will disable the Input buffer 78 and count the first two CRC bits of the Input message as they are clocked into the CRC generator 81 over line 82 from the Input Control logic 77. After this has occurred, the Sequence Counter 86 is stepped to count 10.

During count 10, the last 6 CRC bits are clocked into the CRC generator 81 for future error checking. The Transmit counter 118 is disabled and the Sequence counter 86 enables the Data Clock (DC.N) over line 133. The counter 86 is then stepped to count 11.

During count 11, the CRC generator 81 will check the validity of the CRC character of the response message. If the CRC character is bad, the Error Detect logic 83 will generate an error signal over line 84 to the Sequence Control logic 85 which resets the Sequence counter 86 to the 0 count and generates a program interrupt signal over line 136 to the CPU 95 indicating that the communication adapter has received an invalid response. Normally the software in the CPU 95 will cause it to respond with a command signal over line 99 to the Command decode logic 97 to put the communication adapter in a repoll mode. If the output message was an exchange, the communication adapter would be normally put into a re-exchange mode. If the CRC character of the response message is valid, the CRC generator 81 will generate a signal over line 137 to the Sequence Control logic 85 which steps the counter 86 to count 12.

During count 12, the ID Compare logic 91 (FIG. 5b) will compare the ID bits of the response message in the Input buffer 78 with the ID bits located in the ID register 93 that was sent out in the poll message to see if they compare. If they do not compare, a first signal is generated over line 138 to the Sequence Control logic 85 which duplicates the sequence of operations resulting from a CRC error described above. If the lDs do compare, a second signal is generated over line 138 to the Control logic 85 resulting in the stepping of the sequence count of the counter to count 13, during which count the message is tested to see if the message returned by the terminal contains data for the CPU.

As described previously, the classification of the message is determined by the function bits in the message. In the event the message is a data response as determined by the function bits in the input message from the terminal, a high signal in the F position in accordance with Table I will be present over line 140 from the Input buffer 78 to the Sequence control logic 85 which will reset the Sequence counter 86 and generate an Input Data interrupt signal over line 141 to the CPU. This interrupt signal is also sent to the Input buffer 78 on line 132 enabling the Input buffer 78 to transmit serially the data stored in the Input buffer through the Data multiplexer 94 to the CPU 95 in parallel form over input lines 96. If the message is a no-data response, the signal over line 140 to the control logic 85 will be low (Table I) and will result in the Sequence counter 86 being stepped to count 14.

During count 14 a test is made to determine if the communication adapter is in the poll mode or the exchange mode by sensing the condition of the Poll latch 142 (FIG. c) in the Command Decode logic 97. As described previously, the Poll latch 142 is set whenever the communication adapter is put in a poll mode by a command signal over line 99 from the CPU. The latch 142 is not set when the communication adapter is put in an exchange mode. If the Poll latch 142 is set at this time and the message is a no-data response, a signal over line 143 indicating a poll-no-data-response condition is sent to the Sequence Control logic 85 which resets the Sequence counter 86 and increments a poll count to find the next active ID in the presence register 101. This latter operation includes the sending of the term PCNT.G (FIG. 6) over line 110 to the ID counter 102 and the term PCNT.GA over line 108 to the presence register 101 in the manner described previously. Thus the communication adapter generates a new poll message. If the Poll latch 142 is set and the message is a poll message, a signal will be sent over line 143 to the Sequence Control logic 85 indicating a poll-dataresponse condition which resets the Sequence Counter 86 only. During count 3 of the next Sequence counter operation, the Presence register 101 will be sensed by the Sequence Control logic 85 and a second poll message will be transmitted to the same terminal, since the Presence register has not been shifted since the last Poll message.

if the Poll latch 142 is not set indicating an exchangeno-data-response condition, the signal over line 143 will cause the Control logic 85 to raise an Output Data Interrupt signal over line 144 to the CPU 95. This signal causes the next data character in the CPU 95 to be sent to the output buffer 113 in the communication adapter over lines 119 which is to be exchanged with the polled terminal. If the CPU has no data character to send, it will put the communication adapter into a poll mode by sending the appropriate signal over line 99 to the Command Decode logic 97 in the manner described previously. This signal will also step the sequence counter to count which is wired to reset the Sequence counter to 0 in which state the adapter starts a poll operation. Thus the communication adapter is set to carry out a new poll operation or an exchange operation.

As disclosed previously, a timer 105 (FIG. 50) comprises a dual one-shot multivibrator for checking the complete response from a terminal within a specified time limit from the start of a poll or exchange message transmission in the controller to a terminal. Once triggered, the timer 105 is set for 100 usec. The time of a polling or exchange transmission is approximately 27 usec. and the response message is approximately 27 usec. If the multivibrator times out before the response message is completed, a signal will be transmitted to the Control logic over line 79 which will function in the same manner as a bad CRC character signal in count 11 or a bad ID check in count 12 of the sequence counter described previously. If no response is received from the polled terminal or there is a bad CRC character or ID bits, the CPU will initiate normally a repoll or re-exchange operation of the communication adapter by sending the proper command signals to the command decode logic 97. If there is still a lack of response, this procedure will be repeated three times at which point the software in the CPU 95 will determine that the terminal is inactive and will so indicate this condition by generating a reconfigure presence register and clear ID counter command over line 99 to the command decode logic 97 which will generate the SET 2 G signal over line (FIG. 6) to the Presence register 101 to condition the presence register for reloading. The CPU 95 will then load the new configuration of zero and one bits into the registers 103 and 104 representing the latest arrangement of active and inactive terminals over lines 106. The SET 2 G signal over line 145 will also reset the ID counter 102 to zero. The CPU will then generate a poll command signal over line 99 to the Command Diode logic 97 to initiate a poll operation.

Referring to FIG. 5b, the poll message from the transmitter 123 located in the communication adapter will be transmitted over cables 24 to each of the terminals connected to the communication adapter. The poll message is received by each receiver 146 in each terminal and is decoded from Manchester code to binary code in a Manchester decoder 147. The receiver 146 also generates a receive clock (RC) of 1.25 Mhz which is transferred over line 148 to the Clock Timing control logic 52. The Clock Timing control logic 52 also receives the L25 Mhz clock (C from the Manchester Encoder 62. Upon receiving the clock from the Receiver 146, the Timing Control logic 52 will generate 8 clock pulses over line 150 to the Send-Receive register 50 to load the sync bits of the poll message over line 151 from the Manchester Encoder 147 through an AND gate 152 to the Send-Receive register 50 and to the Sync Detector 51 over line 153 which checks for the correct sequence of sync bits in the poll message. If the pattern is correct, the Sync Detector 51 will generate a signal over line 154 to the Clock Control logic 52 which will generate sufficient clock pulses over line 155 to operate the Sequence Counter and control 53. The Sequence counter 53 will operate through eleven program counts, nine of which are used for normal message processing in the on-line and off-line mode. The last two counts are required in the off-line mode to complete the hard total shifting sequence.

Upon operation of the Sequence Counter 53, the first 18 bits of the input message following the sync bits will .be loaded into the Send-Receive register 50 from the Manchester Decoder 147 over line 151 and through AND gate 152 and to the CRC Check and Generator 57 over line 156 during counts zero and one of the counter 53. During count 2, the received CRC character is loaded into the CRC generator 57 and checked against a CRC character generated on the input message as it was loaded into the Send-Receive register 50. If the CRC characters do not compare, an error signal will be sent over line 157 to the Error detect logic 55 which signals the General Reset logic 56 over line 158 to reset the terminal to the idle state. Also, at this time, the ID bits of the input message will be loaded into the ID comparator 54 over line 160 to see if the message is intended for this particular terminal. Again, if the IDs do not compare, a signal will be sent to the Error detect logic 55 over line 161 which signals the General Reset logic 56 to reset the terminal with the terminal returning to an idle state.

If both the CRC characters and the ID bits are good, a signal is generated from the Error Detector logic 55 (FIG. a) over line 162 to an lnmode latch 163 (FIG. 5b). The output terms INMODE, INMODE of the latch 163 are switched as a result of receiving the signal from the Error logic 55. The switching of the term INMODE will disable the AND gate 152 (FIG. 5a), thereby preventing any transmission of data from the Manchester decoder 147 to the register 50. The switching of the term INMODE enables the AND gate 48 (FIG. 5a), thus conditioning the loading of data from the Pre-data register 40 to the Send-Receive register 50. Also during count three, the first part of a response message is started by the generation of eight pre-sync one bits by the Transmit Data logic 60 over the cable 24.

During count three, the modulo bit and the function bits of the input message are shifted from the Send- Receive register 50 (FIG. 5a) over line 167 and checked in the Modulo Bit checker logic 72. If the message was an exchange, both the modulo bit and the function bits are checked. If the message is a poll, the function bits are checked, the modulo bit is ignored. If it is an exchange message and the modulo bit is good, a signal USEIDTA indicating to the terminal to use the input data is generated over line 164 to the Sub ID decode logic 65, while a second signal GDRESP indicating a good response is sent over line 165 to a control logic 166. If it was a poll message, only the signal GDRESP would be raised.

If the micro-processor 32 in the terminal had any keyboard or status data to send in the response message, a signal BUSY E is raised indicating same and would have been sent over line 168 to the control logic 166 raising the term BUSY over line 175 (FIG. 5a) to the micro-processor 32. The BUSY signal prevents the micro-processor from loading a new data character into the Pre-data register 40. This sets up the condition that the data character now stored in the Pre-data register 40 and which was sent out on the previous recontroller. The Modulo Bit generator under the control of the BUSY M signal will generate a modulo bit and two function bits. Referring to Table I, it will be seen that the function bits for a Data, No Data response is determined by a 1 or 0 respectfully in the F bit position. Thus the bit configuration of the BUSY M signal would reflect both conditions, that is, if BUSY M is high, the micro-processor 32 has a data character to send and the terminal response would be a Data response. If BUSY M is low, there is no data in the microprocessor to send to the controller and the terminal would respond with a no-data response. These bits together with the terminal ID bits over line 71 and the sub-ID bits from the micro-processor 32 over line 68 are parallel loaded into the Send-Receive register 50. Also the data character from the Pre-data register 40 is loaded into the register 50 over line 47 through AND gate 48 which has been enabled by the signal IN- MODE.

The combination of the count 4 clock signals and the USEIDTA signal over line 164 from the Modulo Bit checker 72 (FIG. 5a) described previously allows the Sub ID decode logic 65 to decode the exchange message Sub ID bits to generate clock pulses over one of the lines 66 to the particular module in the terminal designated so that the exchanged data stored in the register 50 can be clocked over line 67 to the designated module allowing it to be activated in accordance with the data received. The timing sequence of the Send- Receive register 50 allows the terminal response message to be loaded into the register 50 over line 47 as the exchange message is shifted out of the register 50 over line 67 as described above. Once a module has been activated, that module perform its function without regard to what is happening in the Send-Receive logic.

During count 5, the first eight bits of the response message is shifted out of the register 50 to the Transmit Data control logic 60 over line 61 and the CRC generator 57 over line 156. The Transmit Data logic 60 then shifts the data to the Manchester encoder 62 and the transmitter 63 for transmission to the controller.

During count 6, the remaining 1 bits of the response message is shifted to the Transmit Data logic 62 and the CRC generator 57. During count 7, the 8 bit CRC character is clocked over line 58 through the Transmit Data logic 60 to the transmitter 63. This completes the transmission of the response message.

During count 8, a signal from the Sequence counter 53 over line 171 to the General Reset logic 56 will reset the terminal to idle mode. The transmission of a response message with data from the terminal requires the controller to answer with another poll or exchange message. The communication logic in the terminal is hung up until the term GDRESP is raised indicating that a new message from the communication adapter is either a poll or exchange, because the terminal data character is being stored in the Pre-data register 40 for possible retransmission in the event an error has been sensed by the controller and it has returned a repoll or re-exchange message.

The micro-processor 32 in the terminal is programmed so that the next terminal response message following the data response message will be a no-data response. This is because of the speed of reception of the next poll or exchange message from the controller. If a new data character has been generated, it will be transmitted in the response message to the second poll or exchange message from the controller.

Referring to FIG. 8, there is shown a flow diagram of the events that occur in a poll operation of the Communication adapter 23. Upon entering a poll operation, the Poll latch 142 (FIG. c) in the Command decode logic 97 (FIG. 5c) is set raising the term SPOLL G (block 183) which signals the Sequence Control logic 85 (FIG. 5c) that the Communication adapter 23 is in a poll mode (block 184). The Sequence counter 86 during count 1 will determine if the Communication adapter is to go to an idle mode from a poll mode (block 185). If it is to enter the Idle mode, the Command control term SAM 1 from the CPU 95 in the Command decode logic 97 will be low as sensed by the Sequence Control logic 85 (FIG. 5c) which will reset the P011 latch 142 and the Sequence counter 86, (block 186) allowing the adapter to return to the idle mode (block 187). If the term SAM 1 is high, the Sequence Control logic 85 will test for the next term SET 1, (block 188) which determines If the CA should go into an exchange mode. If the CA is to go from a poll mode into an exchange mode, the Exchange latch 176 (FIG. 5c) in the Command Decode logic 97 is set (block 190), the Poll latch 142 and the Sequence counter 86 are reset (block 191) and the CA will go into exchange mode block 192.

If the term SET 1 so indicates that the CA is not to go into an exchange mode, the Sequence counter in count 3 will test for an active terminal in the Presence register (FIG. 5c) (block 193). If the output of the presence register 101 (FIG. 5d) is low indicating an inactive terminal (block 194), the terms PCNT (block 195) will be raised to increment the presence register and to increment (block 196) the ID counter to indicate the condition and the ID of the next terminal. The CA will return to a poll mode (block 197).

If there was an active terminal indication present in the output of the presence register, the Sequence Control logic 85 (FIG. 50) will generate the terms PLOD which enables the active terminal ID bits in the output of the ID counter to be loaded into the ID register 93 (FIG. 5c) and the Output Buffer 113 (block 198) and starts the I00 usec response timer 105 (FIG. 50) (block 200) in the Sequence Control logic 85. The communication adapter will then begin to transmit the poll message (block 201) to the terminals.

During count 4 of the Sequence counter 86, the Sequence Control logic 85 will raise the term SYNCO (block 202) in the Transmit Counter 118 (FIG. 5b) which causes the sync bits from the Output Control 121 (FIG. 5b) to be transmitted to the terminals. During count 5, the term DATAO (block 203) is raised in the Transmit Counter 118 (FIG. 5b) which allows the data in the Output Buffer 113 to be transmitted to the terminal. During count 6, the term CRCO (block 204) is raised in the Transmit Counter 118 which allows the CRC character to be transmitted to the terminals from the CRC generator 81 (FIG. 5b).

During count 7, the communication adapter will start checking the response message from the terminals transmitted in response to the Poll message. During count 7, the Transmit Counter 118 is disabled and the Sequence Counter is clocked by the Receiver Clock (RC) (FIG. 7) over line 134, rather than the Data Clock (DC.N) over line 133.

During count 8, the Sequence Control logic will test for the condition of the term SYNDET.C (block 205) from the Sync Detect logic 88 (FIG. 5b). If SYN- DET.C is low, indicating that no sync bits have been detected, the timer in the Sequence Control logic 85 is checked (block 206) to see if it has timed out. If it has not, the term SYNDET.C is again tested for a response. If it has timed out, the communication adapter will go into error flow (block 207) which results in the Sequence Control logic 85 sending a Program Interrupt signal to the CPU (FIG. 50) indicating the lack of a response from the terminal and resets the logic of the communication adapter. The CPU 95 (FIG. 50) will then put the CA into an idle mode.

If the term SYNDET.C is high indicating that the response message is being shifted into the Input buffer 78 (FIG. 5b), the Sequence counter 86 is incremented and the Transmit counter 118 is enabled. During count 9, the Transmit counter 118 will count 18 bits of received data that is loaded into the Input buffer 113 which is then disabled and the Sequence counter 86 is incremented to count 10. During count 10, the timer in the Sequence control logic is sensed (blocks 208, 209) to see if the message has been received in time and to sense whether a complete terminal response has been received (block 210). This is accomplished by sensing the condition of the Transmit counter 118. If there has been a complete transmission, the Sequence counter 86 is incremented and the Transmit counter is disabled. Also the data check (DC.N) is returned to the Sequence counter. If the transmission of the message was incomplete, the communication adapter would go into an error flow operation (block 207).

During count 11, the Sequence control logic 85 will sense (block 239) the output of the CRC generator 81 (FIG. 5b) to determine if the CRC character of the response message is valid, will sense (block 219) the output of the ID compare 91 (FIG. 5b) during count 12 to see if the ID is valid and sense (block 211) the function bits in the Input Buffer 78 (FIG. 5b) during count 13 to determine if the response message contains data for the CPU 95. If the CRC and ID checks are found invalid, the CA will enter into an Error flow operation (block 207). i

If the Function bits tested characterized the message as a no data response, the term NDRESP (block 212) is raised in the Sequence Control logic 85 which steps the Sequence counter 86 to count 14. During count 14, the Poll latch 142 is tested (block 213) to determine if the last message from the CA was a poll or exchange. If the latch is set indicating a poll-no-data-response condition, the Sequence counter 86 is reset and the Presence register 101 (FIG. 5c) and ID counter 102 are incremented to find the next active terminal (block 194). If the last message was an exchange producing either a data response or a no-data-response condition, the communication adapter will start an exchange flow (block 214) with the CPU 95 so that the next character in the CPU 95 will be sent to the terminal in an exchange message.

If the response from the terminal is a Poll-dataresponse, the Sequence Control logic 85 will raise a DRESP signal (block 215) and a data interrupt signal to the CPU 95 and reset the sequence counter 86. The data will then be shifted into the CPU 95. If the CPU 95 has a character of data to transmit (block 216) to the terminal, it will put the Communication adapter into an Exchange Mode (block 217). If not, the Communication adapter will be put into a poll mode (block 218) and poll the same terminal again.

Referring to FIG. 9, there is shown a flow diagram of the events that occur in a poll communication between the controller and a specific terminal. While waiting (block 224) for a message from the controller, the micro-processor 32 (FIG. a) in the terminal will scan the keyboard for data and monitor the status of the keyboard (block 220). Upon receiving a poll message from the controller (block 221), the sync bits of the message are loaded into the'Send-Receive register 50 (FIG. 5a). If the sync pattern is correct, the Sync detector 51 will generate the term SYNDETL enabling the Clock control 52 and the Sequence counter 53 which loads the remainder of the message into the Register 50 (block 222). The ID bits of the input message are compared (block 223) with the terminal ID. If they do not compare, the terminal disregards the message and returns to block 220. If they do compare, the CRC character is compared (block 225). If the CRC character is bad, the terminal will return to block 220 through start block 224. The controller will then send a repoll message (block 226) to the terminal. If this is a second repoll message (block 227), the CPU 95 in the controller will consider this terminal inactive (block 228) and generates a command signal to the Command Decode logic 97 (FIG. 5c) which issues a SET 2 signal over line 145 (FIG. 6) to the Presence register 101 and the ID Counter 102 to reconfigure the Presence register and clear the ID counter. The communication adapter will then start a new polling procedure for the terminals connected to the CA. The communication adapter will wait up to 100 usec for a response to the most recent poll or repoll message it has sent.

If the CRC character is good, the terminal will check to see if BUSY M is true (block 230). If it is, a data response message with one data character is sent (block 231) to the communication adapter. The data character that is sent is retained in the Pre-data register 40 (FIG. 5a) for possible retransmission until the terminal receives another poll or exchange message. This provides an implied acknowledgement (ACK) that the controller has received an error-free response message (block 233) from the terminal. If BUSY M was false (block 230), a no-data response (block 234) is sent to the Communication adapter. If the controller does not receive such a response message, it sends a repoll message to the terminal (block 226), which is an implied negative acknowledgement (NAK), i.e., that the CA did not receive a proper response message.

If the terminal receives a second poll message (block 232) from the communication adapter, the terminals respond with a no-data response (block 234) allowing the micro-processor 32 (FIG. 5a) to clear the pre-data register 40 (block 235) and prepare to load a new data character if one is available. The new data character is then transmitted in the next response message.

While the principles of the invention have now been made clear in an illustrated embodiment, it will be obvious to those skilled in the art that many modifications of structure, arrangements, elements and components can be made which are particularly adapted for specific environments and operating requirements without departing from those principals. The appended claims are therefore intended to cover and embrace any such 20 modifications, within the limits only of the true spirit and scope of the invention.

What is claimed is:

l. A system for transmitting data between a central processor and a group of data terminals which includes active and inactive terminals, the group of data terminals coupled to the central processor through a controller which formats a polling message to only those terminals which are active wherein the improvement comprises:

a. storage means for storing and outputting a plurality of control signals each representing the active or inactive state of a corresponding terminal;

b. and means detecting the output control signal of said storage means for formatting a polling message, said detecting means being enabled to format a polling message to the terminal corresponding to the output signal of said storage means upon detecting an output signal indicating that the corresponding terminal is in an active state.

2. The data transmission system of claim 1 which includes counter means for producing count numbers corresponding to the address of each terminal in said group, said counter means being incremented in sequence with the outputting of said storage means whereby the count represents the address of the terminal corresponding to the output signal of said storage means.

3. The data transmission system of claim 2 which includes means for incrementing said counter means and said storage means when enabled and said detecting means, upon detecting an output signal in said storage means indicating an inactive terminal, successively enabling said incrementing means until the output signal of the storage means indicates an active terminal.

4. The data transmission system of claim 3 which includes timing means coupled to and operated by said detecting means upon detecting an active signal in said storage means for generating a control signal when the active terminal polled fails to provide a response within a predetermined amount of time.

5. The data transmission system of claim 3 in which a circulating channel is connected between the output and the input of said storage means whereby upon the enabling of said incrementing means, the output signal of said storage means is recirculated into the input of said storage means.

6. The data transmission system of claim 4 in which the central processor is coupled to said storage means and said detecting means is coupled to the central processor for generating an interrupt signal to the central processor upon detecting a control signal from said timing means whereby the central processor will load a new set of signals indicating the active and inactive state of the terminals coupled to the central processor, into the storage means after receiving a predetermined number of interrupt signals from said detecting means.

7. A system for transmitting data between a central processor and a plurality of active and inactive data terminals, the data terminals connected to the central computer through a controller which generates a poll message to only those terminals which are active wherein the improvement comprises:

a. register means located in the controller for storing in sequence a plurality of bits each uniquely representing the active or inactive state of a corresponding terminal;

b. counter means for generating consecutive counts,

each count comprising a terminal address;

c. means for synchronously shifting, when enabled, said register means and incrementing said counter means whereby the address represented by the count of said counter means corresponds to the address of the data terminal representative by the output bit of the register means;

d. and means detecting the output bit of said register means for formatting a poll message, said detecting means being enabled to format a poll message to the terminal corresponding to the output bit of said register means upon detecting an output bit indicating that the corresponding terminal is active.

8. The data transmitting system of claim 7 which includes timing means coupled to and operated by said detecting means upon detecting an active bit in said register means for generating a control signal when the active terminal polled fails to provide a response within 2 a predetermined amount of time.

9. The data transmitting system of claim 7 in which the register means is a recirculating shift register.

10. The data transmission system of claim 8 in which the central processor is coupled to said register means and said detecting means is coupled to the central processor for generating an interrupt signal to the central processor upon sensing a control signal from said timing means whereby the central processor will load a new set of signals indicating the active and inactive state of the terminals coupled to the central processor into the register means after receiving a predetermined number of interrupt signals from said detecting means.

11. A system for transmitting data between a central processor and a plurality of peripheral devices, the improvement comprising:

a. a plurality of controller circuits;

b. a number of peripheral devices assigned to each controller circuit;

c. a controller for each controller circuit for generating poll messages to the peripheral devices assigned to each controller circuit, each of said controllers coupled to said control processor;

(1. serializing means in each controller for generating a plurality of output signals representing the active or inactive state of each peripheral device and in the order in which they are to be polled;

e. means for detecting the output signal in the serializing means representing an active peripheral device;

f. and means responsive to said detecting means for generating and sending a poll message to the active peripheral device.

12. The data transmitting system of claim 11 which includes:

a. counter means in each controller for generating consecutive counts representing the address of a peripheral device;

b. and operating means for synchronously operating said serializing means and incrementing said counter means whereby the address represented by the count of said counter corresponds to the address of the peripheral device represented by the output signal of the serializing means.

13. The data transmitting system of claim 12 which includes means responsive to a negative response from the active peripheral device to a poll message for enabling said operating means and causes said detecting means to detect the next active peripheral device.

14. The data transmitting system of claim 13 which includes means responsive to a positive response from the active peripheral device to a poll message to disable said operating means and causing the central processor to generate an output message to the polled active device.

15. The data transmitting system of claim 14 in which each peripheral device includes a plurality of functional control areas and the output message from the control processor includes a data portion, a first address portion indicating the address of the peripheral device and a second address portion indicating the functional control area of the device the data is intended.

16. The data transmitting system of claim 15 which includes:

a. first address logic means in each peripheral device for enabling said peripheral device to become 0perative upon identifying its address in said first address portion of said output message;

b. and second address logic means in each peripheral device for enabling a particular functional control area of the peripheral device to receive the data in the data portion of the output message upon identifying the address of the particular functional control area in said second address portion of said output message.

17. A method of generating polling messages to a plu-' rality of addressable data terminal devices including the steps of a. generating in a central processor a table of signals, each representing the active or inactive state of a data terminal device in the order in which they are to be polled;

b. storing said table of signals in a polling device ex ternal to said central processor;

c. generating in the polling device a table of addresses of the data terminal devices in the order in which they are to be polled;

d. and utilizing the signals and addresses in said tables in succession to generate polling messages from said polling device to only those terminals which are active.

18. A method of the type describe in claim 17 including the steps of a. receiving responses at said polling device from the polled terminal and testing each response to determine if it is positive or negative;

b. incrementing said table of signals and addresses each time a negative response is received to a poll message;

c. and generating a poll message to the data terminal indicated by the next active signal in the signal table.

19. A method of the type described in claim 18 further including the step of generating an interrupt to the central processor allowing the central processor to receive a message from the polling device each time a positive response is received to a poll message.

20. A method of the type described in claim 19 further including the steps of a. testing to determine if a response is received to a poll message within a predetermined period of time;

b. generating an interrup to the central processor indicating no-response from the polled terminal if a response is not received within said predetermined period of time; p

c. and storing a new table of signals in the polling device after a predetermined number of interrupts have been generated indicating a no-response from the polled terminal.

21. A method of polling a plurality of data terminal devices including the steps of a. generating a table of coded signals each representing the active or inactive state of a data terminal device;

b. and generating a polling message to a terminal when the coded signal indicates the terminal is in an active state.

22. The method of claim 21 further including the steps of a. generating a table of addresses of the data terminal devices in the same order as the table of coded signals;

b. and generating a poll message to the terminal whose address corresponds to a coded signal indicating the active state of the terminal.

23. A method of generating polling messages to a plurality of addressable data terminal devices including the steps of a. generating a table of signals each representing the active or inactive state of a data terminal device in the order in which they are to be polled;

b. generating in a table of addresses of the data terminal devices in the order in which they are to be polled;

c. synchronizing the output of the tables of signals and addresses so that each signal will represent the state of the addressed terminal;

d. sensing each signal in the order in which the terminals are to be polled;

e. and generating a polling message which includes the address of the terminal whose corresponding signal was sensed indicating an active state.

24. A method of the type described in claim 23 including the steps of a. receiving responses from the polled data terminal and testing each response to determine if it is positive or negative;

b. incrementing the tables of signals and addresses each time a negative response is received to a polling message;

c. and generating a polling message to the data terminal indicated by the next active signal sensed in the signal table.

25. A method of the type described in claim 24 further including the steps of a. testing to determine if a response is received to a polling message within a predetermined period of time;

b. generating a control signal each time a response is not received within said predetermined period of time;

c. and generating a new table of signals after a predetermined number of control signals have been generated indicating a no-response from a polled terminal.

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Classifications
U.S. Classification340/9.14, 340/3.51
International ClassificationH04L12/403, G06F13/22
Cooperative ClassificationG06F13/22, H04L12/403, H04L12/40006
European ClassificationG06F13/22, H04L12/403, H04L12/40A