US 3873815 A Abstract A divider circuit for dividing the frequency of a cyclic input signal by any odd modulo N while still maintaining a symmetrical 50/50 duty cycle includes a counter for counting to N, a sensing circuit for resetting the counter on reaching the N count, and encoding means responsive to the output of the counter and the input clock signal offset 1/2 cycle for providing a symmetrical output.
Claims available in Description (OCR text may contain errors) United States Patent Summers Mar. 25, 1975 FREQUENCY DIVISION BY AN ODD INTEGER FACTOR [75] Inventor: Gary J. Summers, Mountain View, [52] U.S. Cl 235/l50.3, 307/225, 328/48 [51] Int. Cl. H03k 21/36 [58] Field of Search 235/150.3, 156, 92 DM; 7/1973 Rogers 307/225 C OTHER PUBLICATIONS L. A. Mann, Divider Circuit Maintains Pulse Symmetry EDN July 1, 1972 pp.5455. Primary E.raminerFelix D. Gruber Assistant Examiner-David H. Malzahn Attorney, Agent, or FirmFlehr, Hohbach, Test, Albritton & Herbert [57] ABSTRACT A divider circuit for dividing the frequency of a cyclic input signal by any odd modulo N while still maintaining a symmetrical 50/50 duty cycle includes a counter for counting to N, a sensing circuit for resetting the [56] References Cited counter on reaching the N count and encoding means UNITED STATES PATENTS responsive to the output of the counter and the input 3,230,352 l/1966 Grondin et a1 235/156 l k i l ffset /2 cycle for providing a symmetrical 3,283,131 11/1966 Carbrey 235/156 X Output. 3,424,986 1/1969 Vasseur 328/48 3,605,025 9/1971 Lincoln et a1 328/48 11 Clalms, 8 Drawing Figures SYMMETRICAL s IO MC |4s2o R C f H T-I2v R 1 V4140 D 6 14013 Lg 14009 17 C s Q 1400s 16 12v :Lc- PATENTED MR 2 5 I975 sum 1 BF 8 N .YI N 2 33002 6 Nd we FREQUENCY DIVISION BY AN ODD INTEGER FACTOR BACKGROUND OF THE INVENTION The present invention is directed to a divider circuit and more specifically to a circuit which divides the frequency of a cyclic input signal by an odd modulo. Digital frequency circuits such as synthesizers, filters and phase locked loops many times require output frequencies which have a 50/50 duty cycle and are of odd frequency multiples. In the prior art, where a common clock frequency was used it was very difficult to provide if at all a divider circuit which would maintain the original symmetry or 50/50 duty cycle of the master clock frequency when it was necessary to divide down by an odd multiple. Output waveforms having a 50/50 duty cycle duration are advantageous from a frequency filtering standpoint since they will have a spectral distribution consisting only of odd harmonics. Odd modulo dividers with symmetrical outputs have been discussed by several authors but only special cases have been mentioned. For example, in EDN magazine dated July 1, 1972, an article titled Divider Circuit Maintains Pulse Symmetry" by Leslie A. Mann shows a divide by five circuit. In addition to having excessive numbers of components, it is not clearfrom the circuit how it could be expanded to other odd modulos. OBJECT AND SUMMARY OF THE INVENTION It is, therefore, an object of the present invention to provide an improved divider circuit for dividing a cyclic input signal by any odd modulo. In accordance with the above object there is provided a divider circuit for dividing the frequency of a cyclic input signal,f,, by an odd modulo, N. Such input signal has a 50/50 duty cycle. A counter is responsive to J} for counting to N. Means sense the reaching of the N count by sensing all logical 1 levels of the counter for resetting the counter. Encoding means are responsive to a predetermined output of the counter and the input signal offset /2 cycle for providing a symmetrical output signal having a frequency offi. divided by N. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram embodying the present invention of a modulo divider; FIG. 2 is a timing diagram associated with FIG. 1; FIG. 3 is a block diagram embodying the present in vention of a modulo 7 divider; FIG. 4 is a timing diagram associated with FIG. 3; FIG. 5 is a block diagram embodying the present invention of a modulo l3 divider; FIG. 6 is a timing diagram associated with FIG. 5; FIG 7 is a block diagram embodying the present invention of a modulo 19 divider; and FIG. 8 is a timing diagram associated with FIG. 7. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1' illustrates a divide by 5 divider circuit and includes a binary counter 10 having as outputs Q Q Q and Q the subscripts referring to the binary position of the output. Counter 10 includes a clocking input terminal coupled to a cyclic input signal, f and a reset terminal R. Counter 10 with its four binary output terminals is capable of counting to 16. However, only three of its Q output terminals are used since the maximum count necessary is 5 before it is reset. The output terminals Q and Q are coupled to NAND gate 11 to provide for resetting through an inverter 12 when the count of 5 is reached, as illustrated in the timing diagram, where the clocking pulses off are numbered from 1 through 5. Reset occurs on the leading edge of the fifth input clock pulse as indicated by the arrow on the reset timing diagram. Such resetting is accomplished by the output from NAND gate 11 due to the coincidence of logical 1 inputs from Q and Q as indicated by the dashed portions of the waveforms. Encoding means consist of a D type flip-flop 13, a NAND gate 16 which has as an output the input signal divided by five as indicated and an inverter 14. Such inverter offsets f, by /2 cycle and couples the signal to input C of flip-flop 13; the D input is coupled to the Q input of counter 10. NAND gate 16 has two inputs; one ofthe inputs is Q, from the counter 10 which is coupled to the gate through a n inverter 17. The other input on line 18 is from the Q output of flip-flop 13. The O input to NAND gate 16 is the most significant bit of the counter minus 1, the most significant bit being the Q output or in more general terms the Q,- output. Th e timing diagram of FIG. 2 illustrates both the Q and Q outputs of flip-flop 13, the Q, output of counter 10 which is coupled to NAND gate 16 and the output signaIf /S of NAND gate 16 which is in effect the inversion of?) and 6 Such signal shown in FIG. 2 obviously has a symmetrical 50/50 duty cycle and is one-fifth the frequency of the original input clock frequency f,.. Referring now both to FIGS. 1 and 2 from an operational standpoint it is apparent that inverter 14 shifts the clock frequency /2 cycle so that the flip-flop 13 is actuated; that is, set and reset. only on the leading edge of the delayed or offsetglock pulse frequency f Thus, referring to the Q and Q waveforms transitions occur at /2 cycle offset points. This type of leading edge transition is a characteristic ofa D-type flip-flop along with a single actuating input. Where the modulo is N 2 l (where i= 2, 3, 4...) the predetermined output of counter 10 which is cou pled to the D input of flip-flop 15 and NAND gate 16 is one bit less than the most significant bit, Q,, of the counter; that is, Q, 1 which is in FIG. 1 the Q output as indicated. The sensing NAND gate 11 is responsive to the reaching of the N count of five by sensing all the logical 1 levels in the binary word five of the counter. These will occur on the Q and Q outputs as indicated by the dashed waveform 21 in the case of Q and 22 in the case of Q0. Q0 occurs only instantaneously to provide a reset as indicated by the arrow 23. Thus, in providing a divider circuit for the modulo of FIG. 1 where N 2 l the following basic rules are applicable. A. There must be a total of i 1 bits in the counter chain. For example, ifi 3, N =9and thus, four binary states or flip-flops are necessaryf B. The sensing network for resetting the counter must have as its inputs all logical 1 levels contained in the binary word N. C. The encoding network must consist of one delayed or D-type flip-flop and one two input NAND ate. The D and C inputs to the flip-flop aI Q;.. and respectively. The NAND gate inputs are Q, and O. FIGS. 3 and 4 illustrate a modulo N 2 l, where 1' equals three, type of divider circuit to provide a divide by seven device. Identical components are used as in the divide by five circuit of FIG. 1. To accommodate the divide by seven, however, rule C set out above is as follows. The D input to the flip-flop must be O (which in the case of a divide by seven is Q2). The NAND gate 16 inputs are Q,- and Q. The timing diagram of FIG. 4 is similar to that of FIG. 2 except for the f,./7 type output of the NAND gate 16. From the foregoing it has been shown how by use of the above rules divider circuits for modulo N 2 i 1 can be constructed. Such division would include divide by three, five, seven, nine, 15, 17,31, 33, etc. In addition, however, if a modulo N 21 is desired, the cascaded network of a divide by seven and divide by three may be used. Also, if the desired N contains the factor two, this factor may be removed and treated in a classical sense by use of a typical flip-flop or divide by two circuit which is well known. When an odd modulo divider does not fall under the above rules, that is, N a 2 :t I with [greater than 1, a circuit concept as shown in FIGS. 5 and 7 can be utilized. As is true of the modulo divider circuits of FIGS. 1 and 3 the encoding means includes flip-flops and NAND gates. However, the encoding network of the divider as shown in FIG. 5 with N 13 will consist of three NAND gates designated A, B and C and two D- type or delayed flip-flops 26 and 27. In addition to the A, B and C NAND gates in the encoding circuit there is a NAND gate 25 in the sensing circuit which senses the reaching of N by the counter 28. The output of NAND gate C is f. divided by the quantity N/2. Thus, this output is coupled to a subsequent divide by two flip-flop 27 to provide the final output off /N. The following rules apply to the circuit of FIG. 5 and also similar type prime number divider circuits. A. The counter must have enough bits to reach the next binary state above N. B. The sensing network for resetting the counter must have has its inputs all logical 1 levels contained in the binary word N. C. The encoding network must consist of three NAND gates A, B and C and two delayed or D-type flip-flops. The A NAND gate will have as its outputs Q0, (1,6 Q j being the most significant bit of the counter. The B NAND gate will have as its inputs the binary word (N 3)/2. The D and C inputs tgthe first D-type flip-flop are the outputs of gate A andf respectively. The C NAND gate will have as its inputs the Q output of the first D-type flip-flop and the output of gate B. D. The output of NAND gate C will be divided by two by means of the second D-type flip-flop to obtain the final symmetrical output. Referring now specifically to the circuit of FIG. 5 and its associated timing diagram of FIG. 6, counter 28 is capable of counting to 16 which is above the odd modulo l3. NAND gate 25 is coupled to Q Q and Q which provide a binary 13 at the point on the timing diagram of FIG. 6 indicated by the reset arrow and the dashed portions of the wavefgrm ofg Q and Q The A NAND gate has as inputs Q Q2. Q and Q in accordance with rule C). Inverters provide for the inversion of the necessary Q outputs of the counter 28. The B NAND gate is provided with inputs equivalent to the binary word (N 3)/2 in counter 28 which in the case of a modulo N 13 the binary word is 8. l n te r ms 9f the binary outputs of counter 28 this is Q Q 0,, Q The inversion again is provided by inverters and where possible common inverters are used both for the A and B NAND gates. The D and C inputs of the D-type flip-flop 26 are the output of NAND gate A and an inverted f, provided by inverter 29. The Q output of flip-flop 26 is coupled to NAND gate C along with the output of NAND gate B. This output wfih is f,. divided by the quantity 13/2 is shown as the QB timing diagram of FIG. 6. When the output of NAND gate C is divided again by a delayed flip-flop 27 the final symmetrical 50/50 duty cycle output is provided at the Q output of the flip-flop and is shown by the last timing diagram. FIGS. 7 and 8 show a divide by '19 circuit which differs from the divide by 13 circuit of FIG. 5 in that an additional counter unit 28' is necessary. Also, of course, in accordance with rule C the connections to the sensing NAND gate 27 are adjusted in accordance with the rule C along with inputs to NAND gates A and B. The divide circuits of the type shown in FIGS. 5 and 7 are, of course, similar to those of FIGS. 1 and 3 in that a counter is utilized which is responsive to f, for counting to N, means for sensing the reaching of N count by sensing all of the logical 1 levels of the counter are provided for resetting the counter, and finally encoding means are provided which are responsive both to the /.a cycle offset off,. and to the output of the counter via NAND gates to provide an output frequency off. divided by N. Thus, an odd modulo frequency divider circuit with symmetrical outputs for any integer N has been provided which can be implemented by a specific system atic set of design rules utilizing one of two basis circuit configurations. Moreover, a minimum of parts is used; in the case of N 2 i l the encoding circuit utilizes only one NAND gate and one flip-flop. In the case of the other prime number circuits, three NAND and two D-type flip-flops are used in the encoding circuit. I claim; 1. A divider circuit for dividing the frequency, f of a cyclic input signal by an odd modulo, N, such input signal having a 50/50 duty cycle, comprising: a counter responsive to f. for counting to N; means for sensing the reaching of said N count by sensing all logical l levels in the word N of said counter and for resetting said counter in response to said sensing of all of said I levels; means for inverting said input signal; and encoding means responsive only to a single predetermined output of said counter and said inverted input signal for providing a symmetrical output signal having a frequency off divided by N. 2. A circuit as in claim 1 where N 2" 1 (i 2, 3, 4...) and where said predetermined output is the most significant bit of said counter and where said encoding means includes a D-type flip-flop having D and C inputs the D input being coupled to said predetermined output of said counter and the C input being coupled to said inverted input signal said flip-flop having a 6 output, said encoding means also including means for inverting said predetermined output a n d including NAND gate means having as inputs said O output and said inverted predetermined output of said counter the output of said gate being f divided by N and having a 50/50 duty cycle. 3. A circuit as in claim 2 where said encoding means consists of said flip-flop, said NAND gate and said inverter for inverting said predetermined output. 4. A circuit as in claim 1 where N =2 l (i =2, 3, 4...) and where said predetermined output is one bit less than the most significant bit of said-counter and where said encoding means includes a D-type flip-flop having D and C inputs the D input being coupled to said predetermined output of said counter and the C input being couplgl to said inverted input signal said flip-flop having a Q output, said encoding means also including means for inverting said predetermined output a d including NAND gate means having as inputs said O and said inverted predetermined output of said counter the output of said gate being f divided by N and having a 50/50 duty cycle. 5. A circuit as in claim 4 where said encoding means consists of said flip-flop, said NAND gate and said inverter for inverting said predetermined output. 6. A divider circuit for dividing the frequency,f,., of a cyclic input signal by an odd modulo, N, where N 2?;1 (i 2, 3, 4 s uch inpt t signalhavinga 50/50 duty cycle, comprising: a counter responsive to g'for' counting to N, where said counter is binary and has as outputs Q Q Q Q; where Q is the most significant bit of the counter; means for sensing the reaching of said N count by sensing all logical 1 levels in the word N of said counter and for resetting said counter in response to said sensing of all of said 1 levels; means for inverting said input signal; and encoding means responsive only to said inverted input signal and a predetermined output of said counter, said encoding meggs i3- cluding a first NAND gate having as inputs Q Q Q a second NAND gate having as inputs said counter outputs corresponding to the binary word, N 3/2, and a D-type flip-flop having C and D inputs said D input being coupled to the output of said first NAND gate and said C input being coupled to said inverted input signal said flip-flop having a 0 output said encoding means including a third NAND gate having said Q output and the output of said second NAND gate as inputs, the output of said third gate having a frequency off divided by the quantity N/2. 7. A circuit as in claim 4 where said encoding means consists of said flip-flop, an additional divide by two circuit coupled to the output of said third NAND gate to provide a symmetrical output signal having a he quency offi. divided by N, said three NAND gates and a plurality of inverters. 8. A circuit as in claim 6 where said encoding means includes a divide by two circuit coupled tothe output of said third NAND gate to provide a symmetrical output signal having a frequency off. divided by N. 9. A divider circuit for dividing the frequency, f,., of a cyclic input signal by an odd module, N, such input signal having a 50/50 duty cycle, comprising: a counter responsive to f for counting to N; means for sensing the reaching of said N count by sensing all logical l levels in the word N of said counter and for resetting said counter in response to said sensing of all of said i levels; means for inverting said input signal; and encoding means responsive only to said inverted input signal and a single predetermined output of said counter, where said encoding means includes a D-type flip-flop having D and C inputs the D input being coupled to said predetermined output of said counter and the C input being couple d to said inverted input signal said flip-flop having a Q output, said encoding means also including means for inverting said predetermined output 22d including NAND gate means having as inputs said O output and said inverted predetermined output of said counter, the output of said gate having a frequency of f. divided by N and a 50/50 duty cycle. 10. A circuit as in claim 9 where N 2 l (i 2, 3, 4...) and where said predetermined output is the most significant bit of said code. 11. A circuit as in claim 9 where N =2 l (i 2, 3, 4...) and where said predetermined output is one bit less than the most siginificant bit of said counter. =l -1 l= l Patent Citations
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