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Publication numberUS3885061 A
Publication typeGrant
Publication dateMay 20, 1975
Filing dateAug 17, 1973
Priority dateAug 17, 1973
Also published asCA1025334A1, DE2422508A1, DE2422508B2, DE2422508C3
Publication numberUS 3885061 A, US 3885061A, US-A-3885061, US3885061 A, US3885061A
InventorsJohn Francis Corboy, Glenn Wherry Cullen, Nicholas Pastal
Original AssigneeRca Corp
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Dual growth rate method of depositing epitaxial crystalline layers
US 3885061 A
Abstract
Method of forming an epitaxial crystalline layer on a crystalline substrate by depositing a first portion at a rapid growth rate and a second portion at a slower growth rate.
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Description  (OCR text may contain errors)

[ May 20, 1975 148/175 ll7/106 A X Boss et 117/106 A X ABSTRACT United States Patent [191 Corboy et a1.

[ DUAL GROWTH RATE METHOD OF DEPOSITING EPITAXIAL CRYSTALLINE LAYERS [75] Inventors: John Francis Corboy, Ringoes;

Glenn Wherry Cullen, Princeton; Nicholas Pasta], Trenton, all of NJ.

[73] Assignee: RCA Corp., Princeton, NJ.

[22] Filed: Aug. 17, 1973 [21] Appl. No.: 389,192

[52] US. Cl. 117/201; 117/106 A; 148/175 [51] Int.

[58] Field of Search 117/106 A, 201; 148/175 [56] References Cited UNITED STATES PATENTS m w n 1 H 2. e: 0 L I H l ql 2 2 I M F m l I 3 4 6 8 1 6 .72 3 w! 2 H 2 vI-. u u E a v I. z s w 8 W -l u n I- m /M lu w W I. l W l a 1 1 s 6 MM M w. Aw.

PATENTEB HAYZU I975 SHEET 10F 2 GASES OUT cour'se'of or under contract No."F336l-C-l695 with the Department of the Air Force.

BACKGROUND OF THE INVENTION Device interaction in integrated circuits can be avoided by utilizing a type of circuit in which each active device occupies a separate island of single crystal semiconductor material deposited on an appropriate insulating substrate. For single crystal silicon films, for example, single crystal sapphire or spinel (magnesium aluminate) has proved to be a satisfactory substrate material. Hence this type of circuit has been referred to as an SOS (silicon-on-sapphire or silicon-on-spinel) circuit.

Experience has shown that it is difficult to make transistors in SOS work pieces which have all electrical characteristics as good as those of transistors made in bulk silicon work pieces. It has also been found that transistors in SOS work pieces vary widely in characteristics as growth parameters of the silicon films in which they are formed, are varied. This latter is due to the fact that properties of the grown silicon film, such as degree of crystalline perfection, vary with growth parameters such as growth rate of the film.

It has been found that, in the case of homoepitaxial growth, low growth rates tend to yield better crystalline quality than do high growth rates. Thus it would appear that heteroepitaxial films of silicon should also be deposited at relatively low growth rates in order to obtain optimum characteristics.

However, factors other than crystalline perfection must be considered. Heteroepitaxial silicon films are usually grown by passing a mixture of silane (SiH and hydrogen over a heated sapphire or spinel substrate. These deposition constituents (including silicon) react with these substrates and form gaseous reaction products which tend to contaminate the crystalline deposit. At slower growth rates, the increased time of exposure leads to a higher degree of contamination.

Another factor which influences contamination of the grown film is growth temperature. As growth temperatures increase, autodoping with contaminants from the substrate also increases.

Because of the above described difficulties, workers in the art have attempted to minimize the autodoping problem by using as low a growth temperature and as high a growth rate as are consistent with acceptable crystalline perfection and electrical properties in the crystalline deposit.

Active device characteristics tend to be most desirable when the mobility of the charge carriers (Hall mobility) is relatively high, leakage currents are relatively low, and minority carrier lifetime is relatively high. Best MOS/SOS transistor characteristics have been obtained on films 0.8 pm thick. In general, however, the epitaxial layer thickness should be as thin as possible consistent with acceptable electrical characteristics, since reduced film thickness reduces metallization failure along the film edges where vapor deposited leads are utilized to connect to the electrode regions.

It would be desirable to be able to deposit epitaxial I silicon films on sapphire or spinel having a thickness of the order of 0.5 pm which have characteristics for making good electrical devices such as MOS transistors equal to those made in films one or more pm thick. In the past, one reason why this has been difficult to achieve, using a growth rate of 2.0 um/min, is that only about 15 seconds were available to deposit such a film considering the factors discussed above. This was too short a time to reproducibly manipulate reaction gas flow rates and concentrations so as to alter the conduc tivity type or carrier concentration at the siliconsubstrate interface.

INVENTION SUMMARY The present invention is an improved method of depositing an'epitaxial film on a crystalline substrate. This is accomplished by depositing a film in two stages by an improved technique. The first stage is the deposition of a very thin film (i.e., one having a thickness of about 500-2000 A) using a burst technique. Using the burst technique an average growth rate of 4-6 ,um/min can be achieved. The second stage is the deposition of the remainder of the film at a slower rate (i.e., not over about 0.5 um/min). By this method, a satisfactory silicon film 0.5 urn thick can be deposited in 1-4 minutes.

THE DRAWING FIG. 1 is an elevation view, partly in section, of a reaction chamber that can be used in the present method; and

FIG. 2 is a schematic diagram of a gas supply and mixing system which can be used to carry out the method of the present invention.

DESCRIPTION OF PREFERRED EMBODIMENT Although the present method can be carried out using either a vertical type or a horizontal type reactor, it will be described in connection with using a barrel type vertical reactor.

Referring to FIG. 1, a suitable reactor may comprise a reaction chamber 2 which is generally bell-shaped. The chamber 2 has inner walls 4 and outer walls 6 so that water may be circulated between the walls to keep the inner walls 4 cool when the chamber is in use. The top of the chamber 2 is provided with a gas inlet port 8. Suspended from the top of the chamber is a disc-shaped gas deflection means 10. The gas deflection means 10 is disposed near the top of the chamber so as to direct incoming gases toward the walls of the chamber.

The chamber 2 is mounted on a hollow base plate 12 through which cooling water maybe circulated by means of an inlet port 14 and an outlet port 16.

Rotatably mounted within the chamber 2 on a vertical spindle 18 is a susceptor 20 which may be made of carbon. The susceptor 20 is shaped like a hexagonal truncated prism, and each of its six sloping faces 22 is provided with a ledge 24 on which a semiconductor wafer 26 may be placed for treatment.

The spindle I8 is mounted on a vertically disposed shaft 28 housed within a sleeve 30 and provided with a bearing 32. The lower end of the shaft 28 is provided with a pulley 34 which is driven through a belt 36 by a variable speed motor 38. In use, the susceptor 20 is slowly rotated as gases are circulated through the chamber 2. Y

A mixture of reaction gases is delivered to the reaction chamber 2 using the mixing and delivery system 40 as shown in FIG. 2. In the present embodiment, the invention will be described as applied to deposition of an epitaxial silicon film from a doped mixture of silane and hydrogen.

The system 40 includes 3 gas input lines 42, 44 and 46 for delivering a dopant, silane and hydrogen, respectively. The lines 42, 44 and 46 are each provided with gas flow monitoring means 48, 50 and 52, respectively, control valves 54, 56 and 58, respectively, and pressure regulating valves 60, 62 and 64, respectively.

The input lines 42, 44 and 46 are all connected through a control valve 66 to one end of a burst chamber 68 which is provided with a pressure gauge 70. in this example, the burst chamber is inches long and has a diameter of 2 inches. Connected to the opposite end of the burst chamber is an outlet orifice 72 of known diameter. In this example, the diameter of the-outlet orifice is 0.050 inch.

Connected into an outlet line 74 from the outlet orifice 72 is a control valve 76. An exhaust line 78 is connected to the outlet line 74 and an exhaust valve 80 controls gas flow through the exhaust line 78.

A branch line 82 connects the outlet from control valve 76 to the gas inlet port 8 of the reaction chamber 2 (HO. 1).

Another input line 84 connects the single output of a second series of inlet lines (not shown) to the line 84 through a control-valve 86.

The above described system may be used to deposit a two-stage composite coating as will now be explained.

First, the burst chamber 68 is made ready for the film growth process by flushing it with the gases to be used. Valves 66 and 80 are opened, valve 76 is closed, and valves 54, 56 and 58 are opened to permit flow of dopant gas from the line 42, silane from the line 44 and hydrogen from the line 46, to the burst chamber 68. Gas flow-rates are controlled so as to admit a mixture having the proportions 100 cc of dopant gas, which comprises hydrogen, having suspended therein 100 p.p.m. of diborane or arsine (depending upon whether p type or n type doping is desired), 5000 cc of 6% silane in hydrogen and 25,000 cc of hydrogen. These gases are first flushed through the burst chamber 68 and the rest of the system including the exhaust line 78 to replace air, and then valve 80 is closed and the burst chamber 68 is filled with the gaseous mixture at 60 lbs./sq. in. pressure. When the burst chamber 68 is filled, the valve 66 is closed.

The susceptor is then heated to l000C by means of rf heating. The susceptpor is also rotated at a speed of 18 rpm. The valve 76 is then opened and the gases from the burst" chamber 68 are suddenly emptied into and through the reaction chamber 2. The gases pass over the heated substrate wafers 26 and begin to deposit an epitaxial layer of silicon thereon. A single crystal layer of silicon approximately 1000 A thick is deposited in l to 1.5 seconds. At the end of this brief period, valve 76 is closed, thus sealing off the burst chamber 68 and its associated piping system from the remainder of the system.

Meanwhile, preparations are also made for growing the remainder of the film at a slower rate by a conventional process. At the same time as the contents of the burst chamber 68 are passing through the reaction chamber 2, a mixture having the proportions: 50 cc of hydrogen containing 10 p.p.m. diborane or arsine, 500 cc 6% silane in hydrogen and 25,000 ccof hydrogen are admitted into the reaction chamber 2 by opening the valve 86. This causes an epitaxial film of silicon to continue growing but at a much slower rate.

The second stage of growth can be continued for as long as desired to produce a desired total thickness of silicon. As an example, the slower growth rate may be kept between 0.1 and 0.5 ,um/min and the total film thickness may be 0.5 pm.

Both film stages may be doped the same, n type or p type, or one may be doped n type and the other p type. The first stage film may be more highly doped as in this example. In this example, the first stage is doped to about 10 to 10 atoms/cc and the second stage is doped to about 10 atoms/cc.

Although the method has been described in connection with depositing an epitaxial layer of silicon on a sapphire or spinel substrate, it can be used whenever there is danger of unwanted contaminants from the substrate getting into the crystalline layer which is being deposited and thus causing undesirable characteristics to appear in the deposited film.

We claim:

1. A method of comprising a composite layer of heteroepitaxial silicon on a heated sapphire or spinel substrate comprising:

depositing a first portion of said layer having a thickness of about 500-2000 A at an average growth rate of about 4-6 am/min and the remainder of said layer at a rate of not more than about 0.5 sm/min.

2. A method according to claim 1 in which said first portion of said layer is deposited by pressurizing a gas cylinder with a mixture of silane and hydrogen and allowing the mixture to flow suddenly into the reaction chamber.

3. A method according to claim 2 in which arsine or diborane is included in said mixture.

4. A method according to claim 2 in which said remainder of said layer is deposited immediately following deposition of said first portion of said layer by introducing into said reaction chamber, a mixture of silane and hydrogen having a lower proportion of silane to hydrogen than the mixture in said gas cylinder.

5. A method according to claim 4 in which the mixture in said gas cylinder comprises 5 parts hydrogen to 1 part 6% silane in hydrogen, and the gas mixture for depositing said remainder of said layer comprises 50 parts hydrogen to 1 part 6% silane in hydrogen, all

parts being by volume.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3189494 *Aug 22, 1963Jun 15, 1965Texas Instruments IncEpitaxial crystal growth onto a stabilizing layer which prevents diffusion from the substrate
US3663319 *Nov 20, 1968May 16, 1972Gen Motors CorpMasking to prevent autodoping of epitaxial deposits
US3669769 *Sep 29, 1970Jun 13, 1972IbmMethod for minimizing autodoping in epitaxial deposition
US3765960 *Nov 2, 1970Oct 16, 1973IbmMethod for minimizing autodoping in epitaxial deposition
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4106959 *Jul 6, 1976Aug 15, 1978Bell Telephone Laboratories, IncorporatedProducing high efficiency gallium arsenide IMPATT diodes utilizing a gas injection system
US4201604 *Sep 8, 1976May 6, 1980Raytheon CompanyProcess for making a negative resistance diode utilizing spike doping
US4279688 *Mar 17, 1980Jul 21, 1981Rca CorporationMethod of improving silicon crystal perfection in silicon on sapphire devices
US4419332 *Oct 21, 1980Dec 6, 1983Licentia Patent-Verwaltungs-G.M.B.H.Epitaxial reactor
US4596208 *Nov 5, 1984Jun 24, 1986Spire CorporationCVD reaction chamber
US4772356 *Jul 3, 1986Sep 20, 1988Emcore, Inc.Gas treatment apparatus and method
US4775641 *Sep 25, 1986Oct 4, 1988General Electric CompanyMethod of making silicon-on-sapphire semiconductor devices
US4838983 *Mar 18, 1988Jun 13, 1989Emcore, Inc.Gas treatment apparatus and method
US4894349 *Dec 15, 1988Jan 16, 1990Kabushiki Kaisha ToshibaTwo step vapor-phase epitaxial growth process for control of autodoping
US5010033 *Apr 30, 1990Apr 23, 1991Canon Kabushiki KaishaProcess for producing compound semiconductor using an amorphous nucleation site
US5104690 *Jun 6, 1990Apr 14, 1992Spire CorporationCVD thin film compounds
US5118365 *Mar 4, 1991Jun 2, 1992Canon Kabushiki KaishaIi-iv group compound crystal article and process for producing same
US5281283 *Dec 4, 1992Jan 25, 1994Canon Kabushiki KaishaGroup III-V compound crystal article using selective epitaxial growth
US5304820 *Mar 13, 1992Apr 19, 1994Canon Kabushiki KaishaProcess for producing compound semiconductor and semiconductor device using compound semiconductor obtained by same
US5425808 *Oct 29, 1993Jun 20, 1995Canon Kabushiki KaishaProcess for selective formation of III-IV group compound film
US6399429Jun 30, 1999Jun 4, 2002Sony CorporationMethod of forming monocrystalline silicon layer, method for manufacturing semiconductor device, and semiconductor device
EP1018758A1 *Jun 30, 1999Jul 12, 2000Sony CorporationMethod for forming monocrystalline silicon layer, method for manufacturing semiconductor device, and semiconductor device
Classifications
U.S. Classification117/93, 148/DIG.700, 148/DIG.129, 257/E21.121, 148/DIG.150, 438/479, 257/E21.104, 148/DIG.250, 117/933
International ClassificationC23C16/44, H01L27/12, H01L21/86, H01L21/205, C30B25/02, C30B29/06, H01L21/20
Cooperative ClassificationY10S148/007, Y10S148/15, H01L21/02576, H01L21/02579, H01L21/0262, H01L21/0242, H01L21/02532, Y10S148/129, Y10S148/025
European ClassificationH01L21/02K4C3C1, H01L21/02K4A1J, H01L21/02K4C1A3, H01L21/02K4C3C2, H01L21/02K4E3C