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Publication numberUS3887795 A
Publication typeGrant
Publication dateJun 3, 1975
Filing dateOct 2, 1973
Priority dateOct 2, 1973
Also published asCA1019981A1
Publication numberUS 3887795 A, US 3887795A, US-A-3887795, US3887795 A, US3887795A
InventorsEyrick Theodore B, Hattes Neil R
Original AssigneeChemetron Corp
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Respiration ratemeter
US 3887795 A
Abstract
Circuitry for displaying an averaged respiration rate is disclosed. Inspiration pulses from a respirator representing a breathing rate to be monitored are fed to three counters, each of which counts the pulses for a period of 30 seconds. Each 10 seconds the accumulated count in a different counter is transferred to a display storage register, and that counter cleared.
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Description  (OCR text may contain errors)

United States Patent [1 1 [111 3,887,795 Eyrick et al. June 3, 1975 [5 RESPIRATION RATEMETER 3,643,652 2 1972 Beltran 128/DIG. 29 [75] Inventors: Theodore B. y c g; eil 3,644,718 2/1972 Osborne et al. 235/92 EA Hattes Danvers both of Mass Primary Examiner.loseph M. Thesz, Jr. [73] Assignee: Chemetron Corporation, Chicago, rn y, g or Firm--lI1e$, Tuner & COOPBY Ill.

[22] Filed: Oct. 2,1973 [5 7] ABSTRACT Circuitry for displaying an averaged respiration rate IS PP N0-1402,678 disclosed. Inspiration pulses from a respirator representing a breathing rate to be monitored are fed to [52] us CL 235/92 EA; 235/92 235/92 three counters, each of which counts the pulses for a 235/92 128/DIG period of 30 seconds. Each seconds the accumu- 51 Int. Cl. H03k 21/18 lated count in a different is transferred a [58] Field of Search 23 5 /92 TF, 92 F0 92 MT, display storage register, and that counter cleared.

235/92 BA, 92 ST, 92 CC; 128/DIG. 29, The input inspiration pulses are doubled before DIG. 17, 2.08 counting, so that the count that is transferred to the display represents the breathing rate for a one minute [56] References Cited period. The display thus presents a breath per minute UNITED STATES PATENTS indication which is updated every 10 seconds.

3,422,422 1/1969 Frank et al. ..1 235 92 F0 12 Claims, 3 Drawing Figures 9.93 sewn? l- 02 l0 SEC I00 lNV TIMER '1 i 88 H0 70ms CLEAR l L LIMITER PULSE I COUTER g MULT| DISPLAY DIGITAL Ho's/S ATBOW PLEXER STORAGE DISPLAY s LIMITER I28 COUNT i H5 4 2 78 I74 g '0 AND g g/IULTIPL. 32 DDRESS INSR i 92 L a r l2 PULSE JUL. W i r COUNTER DOUBLER SELECT n r 56 e4 coum f \coum l 70M 3. LIMITER 96 34 AND Q l RESPIRATION RATEMETER BACKGROUND OF THE INVENTION The present invention relates, in general, to pulse counter circuits, and more particularly to a counter for providing an averaged display of a breathing rate.

In the use of respirator systems of the type disclosed and claimed in copending applications Ser. No. 402,677 of Theodore B. Eyrick, Allen C. Brown and Neil R. Hattes entitled Volume-Rate Respirator System and Method, and Ser. No. 402,679 of Theodore B. Eyrick and Allen C. Brown, entitled Breathing Gas Delivery Cylinder for Respirators, both filed on even date herewith and assigned to the assignee of the pres ent application, it is highly desirable to provide an accurate, continuing measurement and display of the breathing rate of the patient under treatment. Not only does such a readout provide an ongoing monitoring of patient condition, but it serves as well as a check on the operation of the machine and enables the operator to determine at a glance whether any serious problems have arisen.

Although respiration monitors are well known in the art, many such devices rely only on visual or audible alarms to provide an indication of existing problems. Such alarms are, of course, necessary in order to call attention to malfunctions in the respirator or to summon aid for the patient. However, such alarms generally operate after the fact, and do not enable the operator to detect impending difficulties, such as a gradually increasing or decreasing rate not yet at the alarm stage.

Some monitoring devices have incorporated rate indicators which provide an indication of a measured count, but too often such devices have simply provided a meter readout or a continuous instantaneous indication which is of limited usefulness to the operator. A meter indicator is often difficult to read, and thus is subject to erroneous interpretation, and shares with the instantaneous indicators the difficulty of a continuously changing reading in situations where variations in breathing rate are occurring. Thus, this type of indicator is not easy to read, can be misleading to the operator, and is, therefore, not entirely satisfactory from the standpoint of ease and convenience of use, and patient safety.

SUMMARY OF THE INVENTION It is, accordingly, an object of the present invention to provide a reliable, easily read, stable indication of the breathing rate of a patient.

It is another object of the present invention to provide a ratemeter that is capable of producing a timeaveraged indication of the breathing rate of a patient.

It is another object of the invention to provide a digital ratemeter for counting, averaging and displaying the inspiration rate of a patient.

In accordance with the present invention, the ratemeter receives inspiration pulses from a respirator, respiration monitor, or the like, averages the pulses over a period of time, produces a digital display of the pulse rate, and periodically updates the display. The inspiration pulses received by the ratemeter are fed through a frequency doubler and the resultant pulse train is fed in parallel to three counters. Each'counter counts the input pulses for 30 seconds, after which time its count is transferred to a storage register. The counter outputs are selected in sequential order and every seconds the output from a different counter is transferred to the storage register to update the register with a new 30- second count. The storage register operates a digital optical display to provide a visual readout of the accumulated timeaveraged counts which, because of the frequency doubling at the input, represent the number of breaths per minute, averaged over thirty seconds, and updated every 10 seconds.

BRIEF DESCRIPTION OF THE DRAWINGS The foregoing and additional objects, features and advantages of the present invention will be more fully appreciated from a consideration of the following detailed description of a preferred embodiment thereof, as illustrated in the accompanying drawings, in which:

FIG. I is a block diagram of a preferred form of the ratemeter of the present invention; and

FIGS. 2 and 3 are a schematic logic diagram of the circuit of FIG. 1.

DESCRIPTION OF A PREFERRED EMBODIMENT Turning now to a consideration of the drawings, there is illustrated at 10 a pulse doubler to which is applied by way of input line 12 a pulse 14 representing an event to be counted. This input signal preferably is a respiration pulse from a respirator, from a conventional respiration monitor or from other sources of pulses to be counted and time averaged.

Pulse doubler 10 is a frequency doubler comprising flipflop logic elements which respond to successive input signals in known manner to produce alternating outputs, flipflops 16 and 18 (FIG. 2) being interconnected to form a ring counter. The inspiration pulse on line 12 is applied to the clearing inputs of both flipflops, the line being low in the absence of an event pulse to hold them direct cleared. A HZ clock pulse is applied to the timing inputs T of the flipflops by way of line 20, one input ofa clock AND gate 22, and lines 24, 26 and 28. The clock pulse appearing on line 24 is also applied to one input of an AND gate 30 at the output of the doubler. Output line 32 of flipflop 16 is connected to an input of flipflop 18, to one input of an OR gate 34 and to one input of a clock inhibiting AND gate 36, the output of which is applied through inverter 38 and line 40 to the second input of clock AND gate 22. Output 32 and output 42 of flipflop 16 are connected to the inputs of flipflop 18, with the output 44 of flipflop 18 being connected through line 46 to the second input of AND gate 36 and through line 48 to one of the inputs of flipflop 16. The output line 50 of flipflop 18 is connected by way of line 52 to the other input of flipflop 16, and to the second input of OR gate 34, the output of which is connected by line 54 to the second input to AND gate 30.

When no input signal is being received on line 12, the line is low and holds the ring counter flipflops 16 and 18 direct cleared, in their reset states. The ring counter remains in this state until a signal representing the event to be counted is applied to input line 12. The counters are then freed to start counting in response to the clock input pulses on line 20. The trailing edge of the first clock pulse received after the inspiration pulse shifts line 12 high, passes through AND gate 22 and is applied to flipflops 16 and 18 and to AND gate 30. The clock pulse sets flipflop 16, but not flipflop 18, and the resultant output on line 32 enables OR gate 34 to provide a signal to one input of AND gate 30.

The second clock pulse passes through AND gate 22 and is applied to AND gate 30, enabling that gate and providing a count pulse on doubler output line 56. The trailing edge of the second clock pulse sets flipflop 18, shifting its outputs.

The third clock pulse following the inspiration signal passes through AND gate 22 and enables AND gate 30 to produce a second count pulse on output line 56. The trailing edge of the third clock pulse resets flipflop 16, producing a signal on its output line 32 which enables AND gate 36. The resulting output from gate 36 is inverted to inhibit clock AND gate 22, and subsequent clock pulses are blocked. This prevents further shifting of the flipflops, and the doubler remains in this state until the end of the pulse on line 12. At that time the ring counter will again be direct cleared and reset for the next occurrence of an inspiration input pulse. Thus, for each inspiration pulse received by the doubler, two count pulses are produced on line 56.

The count pulses from the doubler are applied by way of line 56 (FIG. 1) to three counter AND gates 60, 62 and 64, each of which is thereby enabled to provide output count pulses to a corresponding one of counters 66, 68 and 70. As illustrated in FIG. 3 with respect to counter 66, each counter is comprised of a pair of conventional decade counters 72 and 74 connected to provide a digital output representing the counts 0 through 98 on output leads A-I-I inclusive. Outputs A1 through H1 are obtained from the first counter 66, outputs A2 through H2 from the second counter 68, and outputs A3 through H3 from the third counter 70.

Each pulse to be counted is applied to all three of the counters in parallel, and each unit counts all of the pulses, providing a pattern of high and low digital outputs on its output terminals corresponding to the number of received pulses, in well known manner. All three of the counters 66, 68 and 70 are pegged, or limited, to a count of 98, in the preferred embodiment, in order to allow operation of the system with a two-digital display. This can be done since any breath rate at that level or above represents an alarm condition, and thus there is no need to display actual counts having a higher rate. However, if desired, additional counters and displays could be used to enable the system to display higher counts.

To provide the count limiting function for counters 66, 68 and 70, each is provided with a corresponding count limiter, 76, 78 and 80 (FIGS. 1 and 3). As shown in FIg. 3, the count limiter 76, which is typical of the three limiters, comprises an AND gate 82 receiving inputs from the three counter outputs that indicate a count of 98. When this count is reached, the AND gate provides a decoding output on line 84 which is inverted in inverter 86 and applied by way of line 88 to the second input of AND gate 60. This inhibits gate 60 and prevents further advance of counter 66 until that counter is cleared. In similar manner, limiter 78 produces a decoded output signal on line 90 when the second counter reaches a count of 98, thereby inhibiting AND gate 62, while limiter 80 inhibits AND gate 64 by way of a decoded signal on line 92, when the third counter reaches the presetlimit.

Each counter is cleared by the simultaneous applica tion of two pulses, one from a timer 94, which produces periodic transfer and clear pulses, and the other from a multiplexer address and counter selector 96, which sequentially selects the counters, whereby the pulse counts in one of the three counters is transferred each time a transfer pulse is produced by the timer.

The timer of 94 may be a type NE 555 timer module 96 wired to function as an astable multivibrator having a period of 10 seconds. The multivibrator is free running to produce an output pulse 98 which is high (on) for 9.93 seconds, and is low (off) for 0.07 seconds during each cycle. The pulse is fed by way of timer output line 100 to a pair of inverters 102 and 104, which provide at the end of the on time transfer input pulses to the display storage registers 106 by way of lines 108 and 110. As shown in FIG. 3, the storage registers 106 comprise a pair of latch modules 112 and 114, latch 112 receiving the transfer signal on line 108, and latch 114 receiving the transfer signal on line 110. These signals release the latches and allow them to follow their inputs received from the counters by way of multiplexer unit 115. At the end of the timer off period the transfer pulses terminate and the data in the storage latches 112 and 114 is retained until the next transfer pulses are received.

The timer output signal on line 100 is also applied by way of line 116 to a Clear Pulse Generator 118 which comprises an AND gate 120 having one of its inputs fed by the signal on line 116, and the other input fed by the signal from inverter 104, by way of line 122. At the end of the off period of timer 94, the combination at AND gate 120 of signals provided by inverter 104, Resistor 124 and capacitor 126 produces a 0.5 u second counter clearing pulse at the output of AND gate 120, on line 128. This short pulse is applied to enable one of the two clear inputs in each of counters 66, 68 and 70, by way of lines 130, 132 and 134, respectively. The other clear input is provided by the counter select network 96, which operates to provide a clearing signal to only one counter at a time, and each 10 seconds operates to clear a next succeeding counter so that the counters are offset in their operation.

Selection of the counter which is to be cleared upon the occurrence of the periodic 0.5 1.0 second counter clearing pulse is by means of the multiplexer address and counter select network 96, which comprises a pair of flipflops and 142 (FIG. 2). These flipflops are interconnected in known manner to provide a count of three counter, sequentially producing signal combinations on each of the flipflop outputs 144, 146, 148 and 150 which may be decoded to produce a sequence of counter selecting signals and which are also used to address the multiplexer.

Initially, with flipflops 140 and 142 both reset, or cleared low output signals are produced on both flipflop outputs 146 and 144, and both signals are applied to a first selector AND gate 152, enabling the gate to produce a first counter selecting signal which is fed by way of line 154 to the second clear input of counter 66. Upon occurrence of the first 0.5 u second counter clear pulse on lines 128 and 130 which occurs at the end of a timer off period, while the signal on line 154 is present, counter 66 is reset to a zero count and begins to count again.

At the trailing edge of the timer on pulse, inverter 102 produces a transfer pulse which is fed via lines 108 and 156 to the clock input of flipflop 140, setting that element and shifting its output to line 148. Selector AND gate 152 is disabled, and the signals on lines 148 and 144 now enable selector AND gate 158, producing a second counter output pulse on line 160 which is fed to the second clear input of the second counter 68. The beginning of the next (second) time period (which is the end of the off period) triggers a 0.5 p. second counter clearing pulse which combines with the signal on line 160, so that for this time period the clearing inputs of only counter 68 are satisfied. This counter is reset to zero and starts counting the inspiration inputs.

At the end of the second time period, a signal is produced on line 156 which again clocks flipflop 140, resetting it to provide an output on line 146, and setting flipflop 142 to produce an output on line 150, whereby AND gate 158 is inhibited and AND gate 162 is enabled. This produces a third counter selecting signal on line 164 which is applied to the second clear input of the third counter 70, and the 0.5 ,u. second counter clearing pulse at the end of the off time and initiating the start of the third timeperiod clears counter 70, which then starts from zero to count the input inspiration pulses.

The trailing edge of the third timing pulse again produces a clock pulse on line 156 which again sets flipflop 140, resulting in both flipflops 140 and 142 being in the set state. This enables reset AND gate 166 which is connected to lines 144 and 146, to produce a clearing signal on line 168 to reset both of flipflops 140 and 142, thereby enabling selector AND gate 152 to clear counter 66, and the counting cycle thus repeats itself.

As will be seen from the foregoing, then, every seconds a timer pulse will operate to advance selector 96 which will then cooperate with a clearing pulse from the timer to reset one of the three counters 66, 68 and 70. Each counter is, therefore, cleared once every 30 seconds, and is thus able to accumulate a count corresponding to twice the number of inspiration pulses received by the ratemeter in 30 seconds.

Connected to corresponding outputs of the three counters are the selector gates of multiplexer 115, illustrated in FIG. 3. As shown, the multiplexer incorporates four gates 170, 171, 172 and 173, each of which is continuously connected to receive the digital output signals from the counters, with selector gate 170 being connected to receive all of the A and B outpts, selector gate 171 receiving all of the C" and D outputs, and so on, as illustrated in FIG. 3. The selector gates are selectively enabled by means of binary address signals received from the counter clear select and multiplex address counter 96, by way of lines 174 and 176. The signals on lines 174 and 176 follow the out puts on lines 144 and 146 at the outputs of flipflops 140 and 142, and thus provide an address count which is advanced with each transfer pulse on line 156 that is received by the flipflops. Thus, when flipflops 140 and 142 are both reset, low signals appear on both of the output lines 144 and 146 not only to enable AND gate 152, as has been explained, but also to enable the l gates in each of the multiplexer selector gates 1701 73. This causes the selector gates to reproduce on their output lines 178-185 the binary coded decimal count which is at that instant appearing on the output lines A1 through I-Il of the first counter 66.

The outputs appearing at the selector lines 178-181 are fed to the latch 112, while the outputs appearing on selector lines 182-185 are fed to latch 114. When transfer pulses are received by the latches from lines 108 and 110, the latches are opened to receive the count Al-Hl from the selector gates, which count is then locked into the latches at the end of the transfer 6 pulses, and is used to drive corresponding display devices 188 and 190. At the end of this first transfer pulse, counter 66 is reset and starts a new count.

When the second transfer pulse is received on line 156, shifting the counter selector flipflop to enable AND gate 158, the signal on line 174 remains low, but the signal on line 176 goes high, thus shifting all of the selector gates -173 to enable their 2 inputs. This causes the selector gates to reproduce on their output lines 178-185 the digital count which is at that time appearing on the output lines A2 through H2 of the sec ond counter 68. At the same time, latches 112 and 114 are enabled to receive the new inputs from lines 178l85, and at the end of the transfer pulse, the latches are again locked to now update the display to show the new count. The end of the transfer pulse also causes the 0.5 p. second counter clearing pulse to clear counter 68.

The third transfer pulse shifts flipflops 140 and 142, as explained, to enable AND gate 162, and this same output is fed through lines 174 and 176 to enable the 3 gates of selector gates 170-173. The transfer pulses on lines 108 and 110 transfer the A3 through H3 outputs to the latches 112 and 114 to again update the display, and thereafter the third counter is cleared.

The next following transfer pulse shifts the selector 96 back to its original condition, selecting counter 1 and shifting the A1 through H1 outputs to the latches 112 and 114. This sequence continues, with the contents of each counter being selected every thirty seconds for transfer to the latches, and a different one of the three counters being selected every 10 seconds to provide an update of the displays. It will be seen that each new counter selected has accumulated doubled input pulses for thirty seconds, thus providing a count corresponding to the number of input events occurring per minute, which count is updated every 10 seconds to provide a new 30-second count.

The particular logic components used in the present invention are all conventional, readily available devices which are supplied on an off-the-shelf basis by numerous electronic supply houses. In general, these components may be conventional series 7400 logic circuits as follows:

TYPE DESCRIPTION 7400 Quadruple 2-lnput Positive Nand 7402 Quadruple 2-Input Positive Nor 7404 Hex Inverters 7410 Triple 3-lnput Positive Nand 7474 Dual D-Type Edge-Triggered Flip-Flop 7475 4-Bit Bistable Latch 7490 Decade Counter 74l07 Dual J-K Master-Slave Flip-Flop 74l2l Monostable Multivibrators 74153 Dual 4-Line-To-l-Line Data Selector] Multiplexer unit time than the rate of the event being monitored, and the number of count transfers per unit time may be varied. The desired relationship between the number of data updates, or count transfers, and the number of count pulses produced for each event to be produced per unit time of the display may be varied without departing from the true spirit and scope of the invention, as described in the following claims.

What is claimed is:

1. In a meter for counting pulses representing the rate occurrence of an event to be monitored and displaying a periodically updated accumulated count representing said rate of occurrence,

at least two counters each receiving and accumulating all of said pulses representing said event, timer means generating a train of periodic timing pulses;

selector means responsive to said timing pulses for sequentially selecting said counters;

indicator means;

means responsive to said timing pulses for transferring the accumulated count in a selected counter to said indicator means; and

means for clearing said selected counter after transfer of the accumulated count, whereby the output of each counter in turn is periodically selected and displayed to provide a periodic update in the display representing said rate.

2. The meter of claim 1, wherein each of said counters accumulates said pulses over a predetermined period of time, and said timing pulses are generated at a rate to produce a plurality of transfers of accumulated counts during said period of time, whereby each periodicallly updated display is of a count accumulated over the entire said period.

3. The meter of claim 2, including three counters, said selector means selecting each counter in turn, each counter being selected once during each said period.

4. The meter of claim 3, wherein said selector means comprises a fourth counter responsive to successive ones of said timing pulses to produce a repetitive series of three counter selecting pulses, each timing pulse advancing said fourth counter means to the next succeeding counter selecting pulse, and means for applying each said selecting pulse to a corresponding counter.

5. The meter of claim 4, wherein said means for clearing said selector counter comprises clear pulse generating means for resetting a selected counter to zero count.

6. The meter of claim 4, wherein said means for transferring the accumulated count comprises multiplexer gating means connected to the outputs of each counter, said multiplexer gating means being operative to transfer to said display means the accumulated count in a selected counter.

7. The meter of claim 6, wherein said forth counter means further comprises address means for activating multiplexer gating means corresponding to the selected counter.

8. The meter of claim 7, further including pulse doubler means for doubling said pulses representing the event to be monitored, whereby each periodically updated display represents the count for twice said period.

9. A method of measuring and displaying the number of breaths per unit time drawn by a patient, comprising:

generating a first train of pulses simultaneously wherein each pulse represents a patient inhalation; generating a second train of pulses having a rate double the rate of said first train;

applying said second train of pulses to first, second 4 and third counters for accumulating a count corresponding to the number of pulses received;

cyclically selecting and resetting said first, second and third counters after first, second and third periods of time, respectively; and

transferring the count accumulated in each of said first, second and third counters upon selection thereof to a display means, whereby said display means is updated after each of said periods.

10. The method of claim 9, wherein each of said counters is selected once during each of two halves of said unit time, whereby a counter will accumulate pulses over only one-half of said unit time before being selected, and said display will indicate a count representing the number of patient inhalations per unit time.

11. A method of measuring and displaying the rate of physiological occurrences in a patient, comprising:

generating a train of count pulses representing one of said occurrences;

accumulating simultaneously in a plurality of counters a count corresponding to the number of count pulses received;

cyclically selecting and resetting said counters, said counters being periodically and sequentially selected;

transferring to a display means the count accumulated in each counter upon its selection, whereby said display means is updated by the counts from successive selected counters to produce a series of updated displays, each display representing the number of physiological occurrences measured over a predetermined unit time greater than the time period between successive updated displays.

12. The method of claim 11, further including generating a second train of count pulses having a rate which is a multiple of the rate of said first-named train, and wherein each said counter accumulates count pulses for less than said unit time before its count is trans ferred to said display.

UNITED STATES PATENT OFFICE CERTEHCATE 0F CORRECTIUN PATENT NO. 3,887,795

DATED June 3, 1975 'NVENTOWS) 1 Theodore B. Eyrick; Neil R. Hatt It is certified that error appears in the above-Identified patent and that said Letters Patent are hereby corrected as shown beiow:

In the claims line 1 (column 7 line 56) change "forth" to fourth.

Claim 7,

line 3, (column 8, line ll) cancel "simultaneously" line 7 after "pulses" insert -simultaneously.

Claim 9,

line 3, (column 8, line 27) "a counter" should read -any one of said counters-.

Claim 10,

fiigncd and fiealed this fif Day of August1975 {SEAL} Arrest:

RUTH C. MASON Arresting ()fj'irer C. MARSHALL DANN 'mnmissr'uner nfluu'nls and Trademarks

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3422422 *Nov 5, 1964Jan 14, 1969Gen Radio CoMethod of and apparatus for frequency display
US3643652 *Dec 31, 1969Feb 22, 1972Delfin J BeltranMedical breathing measuring system
US3644718 *May 20, 1969Feb 22, 1972English Electric Co LtdPulse-counting arrangements
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4007419 *Oct 2, 1975Feb 8, 1977Richard JasmineDigital bicycle speedometer-odometer
US4138722 *Sep 9, 1977Feb 6, 1979Bonnett Robert NElectronic aid for inhibiting smoking
US5033067 *Dec 15, 1989Jul 16, 1991Alcatel Na Network Systems Corp.Variable shift register
Classifications
U.S. Classification377/6, 377/56, 600/537, 377/37, 324/76.39, 600/534
International ClassificationH03K21/08, H03K21/00, A61B5/08
Cooperative ClassificationH03K21/08, A61B5/0816
European ClassificationH03K21/08, A61B5/08R
Legal Events
DateCodeEventDescription
Sep 25, 1992ASAssignment
Owner name: ALLIED HEALTHCARE PRODUCTS, INC.
Free format text: RELEASED BY SECURED PARTY;ASSIGNOR:BANE BOSTON FINANCIAL COMPANY;REEL/FRAME:006329/0348
Effective date: 19920831
Aug 26, 1985ASAssignment
Owner name: BANCBOSTON FINANCIAL COMPANY (THE LENDER)
Free format text: SECURITY INTEREST;ASSIGNOR:ALLIED HEALTHCARE PRODUCTS, INC. A CORP. OF DE.;REEL/FRAME:004444/0863
Effective date: 19850612
Mar 27, 1981ASAssignment
Owner name: ALLIED HEALTHCARE PRODUCTS, INC.
Free format text: CHANGE OF NAME;ASSIGNOR:CHEMETRON-MEDICAL PRODUCTS, INC.;REEL/FRAME:003925/0807
Effective date: 19810227