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Publication numberUS3890490 A
Publication typeGrant
Publication dateJun 17, 1975
Filing dateJan 28, 1974
Priority dateJan 28, 1974
Publication numberUS 3890490 A, US 3890490A, US-A-3890490, US3890490 A, US3890490A
InventorsBuenger George L
Original AssigneeRycom Instr
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Digital data totalizer system
US 3890490 A
Abstract
A digital data system comprising one or more counterencoders and a decoder-display unit monitors remotely occurring events from a central location. Switch closures, in proportion to the frequency of an event to be measured, provide the primary source of data for the counter-encoder. The latter unit generates and stores digital data in response to repetitive switch closures. When desired, the encoder will transmit data either directly or via a communications link, to the decoder-display unit which converts same and displays it in decimal form and/or provides a parallel BCD output. The novel interconnection of a user-programmable weighting counter in a single counter-encoder unit facilitates the determination of several parameters such as accumulated count, scaled counts, counts accumulated in a marked time interval, time between switch closures or time since the last switch closure.
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United States Patent 11 1 Buenger I DIGITAL DATA TOTALIZER SYSTEM [75] Inventor: George L. Buenger, Olathe, Kansi [73] Assignee: Rycom Instruments, Raytown Mo.

{22] Filed: Jan. 28, 1974 [21] App]. No.: 437,340

[52] US. Cl.... 235/92 TF; 235/92 EA; 235/92 MT; 235/92 R; 324/186 [51] Int. Cl. H03k 21/08 [58] Field of Search 235/92 TF, 92 SH, 92 EA, 235/92 DP, 92 MT; 328/4l; 324/l8l, 186

Primary Examiner-Joseph M. Thesz, Jr. Attorney, Agent, or FirmLowe, Kokjer & Kircher OUTPUT AND CONTROL 1 June 17, 1975 [57] ABSTRACT A digital data system comprising one or more counterencoders and a decoder-display unit monitors remotely occurring events from a central location Switch closures, in proportion to the frequency of an event to be measured, provide the primary source of data for the counter-encoder. The latter unit generates and stores digital data in response to repetitive switch closures. When desired, the encoder will transmit data either directly or via a communications link, to the decoder-display unit which converts same and display it in decimal form and/or provides a parallel BCD output. The novel interconnection of a userprogrammable weighting counter in a single counterencoder unit facilitates the determination of several parameters such as accumulated count, scaled counts, counts accumulated in a marked time interval, time between switch closures or time since the last switch closure.

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37 TRANSFER INPUT (SWITCH) I II III JIZ I TIMING INTERVAL5 'IEBIE3I83123I23 SUB/NTERVALS I I I DIGITAL SHIFT I I I REGISTER OUTPUT I I I I I ENCODER OUTPUT I I I I I I I I I I I I I l I I I I I I I PATENTEDJUN I 7 I975 WE IGH TING COUAEI I/Ia .20 ASYNCHRONDUS I 7) COUNTER I OUTPUT AND CONTROL I ,45 #46 I 10 4& 5B 75 COUNT I CONTROL I II I CONTROL l cou/vrsn 6O CLOCK I -57 I I I I I I I 59 COUNT REGISTER AI I SERIAL F70 I I ADDER I63 I I (53 I I -6I I 56 4-775ERIAIL I I 54 79 COUNT POWER I LIMIT EQI IZ 6 g I OFF I I I- I /4' I 652 I TRA/vsFsR7I- TRANSFER I 5' I CONTROL I I I 5+ I /66 I I I 5O? 64' I SERIAL I STORAGE I 78 I REGISTER I I STORAGE REGISTER I I (L I r I /6 OUTPUT 6a TRANSMIT II CONTROL comm/mus I I I I I I I I I I I I I l I I I I I I I I I I I I OUTPUTS PATENTEDJUN 1 7 I975 SHEET 3 r r v T SERIAL INPUT :ERIAL VALIDATION WPUT I SHAPER REGISTER 9a SERIAL r SUBTRACT 86'\\ 94 j PR/NT LOAD 97 DELAY CONTROL -RuN *STATUS V CONVERSION -PR/NT CONTROL CONTROL DELAY -COUNTR #DISPLAY 87 =CDU/VT 5/ PRINTER HOLD /NPuT 995 SET RUN SWITCH BQD J COUNTER PARALLEL BcO I 7 OUT DISPLAY DATA DIGITAL DATA TOTALIZER SYSTEM BACKGROUND AND BRIEF DESCRIPTION OF THE INVENTION This invention relates to data accumulation and mon itoring systems. More particularly, the invention relates to data coding and decoding systems for use in monitoring and parameterizing remotely occurring events. It is an object of this invention to accumulate data and convert it into a form suitable for transmission over a distance and to reconvert and display the information at a receiving facility. The encoder and decoder units are compatible with conventional MODEMS, although many other kinds of transmission links may be used.

A fundamental object of the invention is to provide a system of the type described which may be activated by simple switch closures, rather than the complex and expensive data pick-off arrangements which currently are in common use. Thus, a single-pole, single throw switch may be combined with a measure"tripping device or other inexpensive tripping linkage to measure the flow of a commodity by making" or breaking" an electrical connection in proportion to the occurrence of an event. Thus, electric power, gas or water flow, traffic, items on a conveyor. or people passing through a turnstile may be counted in binary fashion, and the invention will convert the information to a serial binary form suitable for transmission over a communications link to a central location, where the data will be decoded and displayed to the recipient,

A further object of the invention is to increase the reliability of the data transmitted while at the same time minimizing the number of component parts. Accordingly, serial data is generated by the encoder in the form of -bit binary numbers, thus requiring simpler logic circuitry and fewer components than BCD systems. Further, if a circuit element should fail, in a large number of cases, the resultant output will consist of all ones" or zeroes, so that an error will be apparent. On the other hand, the necessity of complex encoder parity" circuitry is avoided by transmitting the binary message twice and comparing the two messages in the decoder.

It is further object of the subject invention to expand the flexibility of a data system of the character described by providing a weighting counter which, through the use of jumpers, may be variably programmed and interconnected by the user. This enables the unit to measure the number of counts accumulated, or the number of counts accumulated in a marked time interval generated internally. When the weighting counter is connected to the clock to facilitate the generation of internal count signal, the elapsed time between switch closures or the time elapsed since the last switch closure may be conveniently determined. The use of the weighting counter provides input scaling, so that the shift registers will register a count for every I-IOO switch closures.

Devices of this type normally employ a count" register and a storage register, but typical prior art devices such as that disclosed in the Leeds & Northrup (of North Wales, Pa.) manuals entitled Directions, l090l Digital Telemetering Transmitter" and Directions, 10902 and 10903 Digital Telemetering Receiver- Control Unit, provide access only to the storage register. If the operator wishes to read the count register information, for example, the data must first be transferred to storage. Thus, while the count register data may eventually be sampled. the information formerly on the storage register is lost. It is an object of the present invention to provide a separate output from both the count register and the storage register so that either digital quantity may be separately requested and/or monitored without upsetting the reading on the other register. In the present invention the counter-encoder unit accepts a count input (which is used to increment a count quantity held in the unit) and a transfer input, same being used to transfer the count quantity to the storage register. Both inputs can be derived from a switch closure. When a transfer input occurs, the count quantity is reset to zero. However, the count quantity in the present invention may be read without transfer input. Thus, the storage of information over longer time periods is greatly facilitated because it is not disturbed by intermittent count register data transmission.

It is a further object of this invention to temporarily immunize the encoder unit from loss of the stored data when a power failure should occur. A large electrolytic capacitor in the power section of the device provides a sufficient stored charge to prevent data losses in the memory circuitry during a temporary loss of main power. The use of low power COS/MOS logic minimizes power drain.

It is yet another object of this invention to provide a TTL decoder unit which will accept the serial output from the aforementioned encoder and convert same to outputs in the form of [2-bit BCD and a pulse train A three digit decimal output is provided by a visual display which utilizes the BCD information. The BCD data is also suitable for strip line printers.

It is another object of this invention to convert the serial encoder output to parallel BCD inputs suitable for processing by a minicomputer. Thus the centralized monitor facility can keep track of a number of remote installations via the inexpensive "mini-computers which are found in many offices.

Other and further objects of the invention, together with the features of novelty appurtenant thereto, will appear in the course of the following description.

DETAILED DESCRIPTION OF THE INVENTION In the accompanying drawings which form a part of the specification and are to be read in conjunction therewith, and in which like reference numerals are employed to indicate like parts in the various views;

FIG. 1 is a block diagram of the preferred embodiment of the counter-encoder unit;

FIG. 2 is a block diagram of an alternative embodiment of the counter-encoder unit;

FIG. 3 is a block diagram of another embodiment of the counter-encoder unit;

FIG. 4 is a diagram of the encoder signal logic waveforms utilized in the output and control block;

FIG. 5 is an expanded block diagram of the counterencoder of FIG. 1; and

FIG. 6 is a block diagram of the decoder-display unit.

Turning initially to FIG. I, a basic counter-encoder unit is shown therein which can accept two input signals, both of which are derived from switch or electrical contact closures. The count input" appears on line 10 and is used to increment the count quantity held in the count register 14. The value of the count may rise to 999 with succeeding switch closures. The transfer input", on line 15, is used to transfer the count quantity to the storage register 18, which may also retain a quantity up to 999. Quantities within the counterencoder are serially processed as lU-bit binary numbers with a binary to BCD conversion being performed later at the decoder.

In FIG. the weighting counter I2 will advance the count appearing on line It after a preselected number of switch closures have appeared on line 10. For example, the weighting counter 12 may be programmed by the consumer to present an output on line II after I (for example) switch closures have occurred on line 10. Counter 12 is essentially a user-programmable asynchronous counter which needs only one input to function. When a pulse appears on line II, the counter register reading increases one unit. The output of the count register is delivered via line 13 to output and control" block 20, which encodes data presented to it into a pulse width modulated binary output which appears on line 21. Information appearing on line 2] is transmitted by a communications link (not shown) to the decoder (FIG. 6).

Data stored in storage register 18 remains constant until a transfer input, such as a switch closure, appears on line 15. A transfer input causes the data in count register 14 to be delivered to storage register 18 via gate l6, whereupon previously stored data is replaced with count register data and the count register will be forced to a zero or one count state.

The output and control unit 20 may be programmed to transmit data in a number of different modes. The unit will transmit either the count information from line I3 or the storage information appearing on line I9. Al ternately, the unit 20 may transmit both quantities, distinguishing one quantity from the other by transmitting one of the quantities twice. When two separate output lines are provided (as in FIG. 5) the latter is unnecessary.

In FIG. 2 a pulse input which is derived from switch closures is delivered along line 23 directly to count register 14. It is possible to omit the weighting of the count input in this embodiment, however, if desired, a second weighting counter may be interconnected between line 23 and count register I4. In this case the embodiment in FIG. 2 would have the advantages of the embodiment of FIG. I as well, In any event, count information is delivered from the count register via line 25 to the output and control unit 20, which also has its output on line 26.

As is indicated in FIG. 2, weighting counter 12 is interconnected to eliminate the need for an externallygenerated transfer input. A subharmonic of a clock output (generated within output and control unit 20) drives the weighting counter, which eventually outputs a transfer signal on line 27, thereby functioning as a clock divider. Again, the frequency of the timing signal thus generated can be variably programmed on easy manipulation of the jumper connections within the unit. When the weighting counter reaches the count for which it is programmed, a transfer signal will appear along line 27. The count register reading will thus be delivered via gate 16 to the storage register, whereupon the previously described sequence of events will transpire. Thus the outputs appearing along line 26 will contain count information from count register 14, and a counts-per-transfer reading from storage register 18.

In FIG. 3 an external switch input to the device appears along line 27 and is used as a transfer signal rather than a count signal. In this embodiment the count signal is derived by routing one of the clock subharmonic signals from block 20 through weighting counter 12, and from thence through line 29 to the count register 14. Count inputs will thus depend on the weighting counter programming and the clock fre quency and will accordingly occur at regular intervals.

For example, counts may occur once every 6 seconds or once every minute. Each time a transfer input pulse occurs, the count register is reset to zero. Under such conditions, the quantity contained in the count register indicates the time which has elapsed since the last transfer input, while the information in the storage register indicates the time which elapsed between the last two transfer inputs. As before, the storage register I8 derives its data from the count register 14 via gate 16 when a switching signal appears along line 27. The pulse width modulated output of the device in FIG. 3 appears on line 28.

It is important to realize that a user may choose which of the embodiments (depicted in FIGS. I-3l optimizes the utilization of the available data and that by rearranging jumpers within the basic unit each of the three arrangements can be quickly put in operation. Furthermore, the use of an additional weighting counter in FIGS. 2 and 3, added to lines 23 and 27, respectively, will increase the versatility of these units by weighting the input signals. Finally, in all three of the embodiments, the type of output signal desired is controlled via an input to line 30, which will be discussed further in conjunction with FIG. 5.

FIG. 5 is a detailed block diagram of the counterencoder embodiment of FIG. 1. The circuits shown therein are common to FIGS. 2 and 3 as well, requiring only the few minor interconnection changes mentioned above to realize these embodiments. Accordingly, the following discussion will be centered about the arrangement shown.

Data entering the counter-encoder via line 10 is weighted by the combined action of asynchronous counter 41 and count control circuit 42, which together comprise weighting counter 12. Data entering asynchronous counter 41, via line 45, is appropriately weighted and reenters the remainder of the circuitry through line 46.

When a weighted count is delivered by asynchronous counter 41 to count control circuit 42 (via line 46) the latter delivers an add-l" input on line 57 to serial adder 59. This add-l input is synchronized with the shifting of the least significant digit into the serial count register 47, and the necessary timing information is obtained from a clock signal applied thereby from the control counter by line 58. Count control circuit 42 also contains circuitry which generates an electrical pulse from a switch closure (on line 10) as well as conventional filtering circuitry for the removal of count switch chatter. The circuit 56 limits the maximum count number which the serial register may reach to the capability of the output display. When that number is exceeded the serial count register will then be forced to zero.

The count data and stored data are held in serial count register 47 (within count register circuit 14 in FIGS, 13) and serial storage register 50 (within storage register 18, FIG. 5) respectively. Both register 47 and 50 are lO-bit serial shift registers wherein quanti ties are encoded as binary numbers. Shift signals derived from clock 52 enter these registers via lines 53 and 54 and circulate the stored quantities through the registers and associated gates. Control counter 55 (in output and control circuit 20, FIGS. l3) counts the shift pulses delivered to the serial registers and provides indexing signals every ten shift pulses. These indexing pulses mark the end of one -bit serial data word and the start of the next. Also the indexing pulses are delivered to output control circuit 62 via line 60 to properly time the start and stop of the outputs appearing on lines 2l or 21a.

If neither a count nor transfer input occurs during a 10-bit register cycle, the output of serial count register 47 is gated through serial adder 59 via line 63, which recirculates the quantity to register 47 via line 61. Thus the count is circulated in an undisturbed fashion in the absence of an incrementing pulse on line 46. If an incrementing count input does occur during a register cycle, an add-l signal is provided to serial adder 59 by count control 42 during the next processing of the least significant digit. Line 72 provides count data to the output control circuit for encoding.

In the absence ofa transfer command on line 15, the output of storage register 50 is recirculated. Thus, the quantity will enter transfer control circuit 65 via line 64 and reenter block 50 via line 66. On a register cycle following a transfer command, the output of serial count register 47 is delivered by line 68 to transfer control circuit 65 and gated therethrough to the input of storage register 50, reaching same via line 66. During this interval, an output of transfer control circuit 65 is transmitted to serial adder 59 via line 70, thereby forcing the adder to a zero count input. Again shift signals on lines 53 and 54 provide synchronous shifting of register data. Gate 16, in FIGS. 1-3, is located within transfer control circuit 65 and delivers the data in shift register 47 for storage in serial register 50 in response to an appropriate transfer signal appearing on line 15. The signal on line XX controls the start and stop timing of a transfer cycle.

Output control circuit 62 receives data from both serial registers 47 and 50 via lines 72 and 7], respectively. Primary digit clock timing information enters block 62 via line 73. Control counter 55 outputs a signal on line 60 (derived from the clock signal on line 75) which marks the start and end of data word transmissions.

When transmitting, binary digital information will be encoded for either one or two shift register cycles, depending upon orientation of programming jumpers. Following transmission of data, the output will normally remain static for the succeeding register cycle, thereby providing a convenient synchronization scheme for the decoder which will be described later. This output appears on line 21 and/or 21a.

The encoder employs pulse width modulation to transmit binary information. A narrow pulse is used to represent a binary zero, while a wide pulse is employed to represent a binary one. The time interval during which a modulated pulse is outputted by the encoder is divided into three equal parts. During the first of these "sub intervals" the output is always high" and during the third of these sub intervals the encoder output is always low. During the second sub interval the encoder output waveform will be high or low depending upon whether a binary one or zero respectively, is being transmitted by the shift register.

This pulse width modulated timing relationship is seen in FIG. 4. A serial binary shift register, located within either count register 14 or storage register I8, is outputting a series of binary digits which are to be converted to pulse width modulated output by the encoder. The shift register output shown in FIG. 4 corresponds to the binary number lOl it). Thus, during the time interval identified by Roman numerals I, III and IV, the shift register output is high. During time intervals II and V. the shift register output is low.

When the conversion process has been initiated by the application of a transmit command signal, an encoder output will occur. No encoder signal is outputted during timing interval l, notwithstanding the fact that the shift register is outputting a binary one, because the transfer command signal is low.

Each of the timing intervals identified by a Roman numeral is divided into three equal subintervals by the clock within output and control block 20. During each of the first subintervals the encoder output is high, and during each of the third subintervals the encoder output waveform is low. The encoder output waveform will be high or low during a second subinterval depending on whether the shift register is outputting a one or a zero during that time.

Thus, in FIG. 4, the encoder is off during interval I because the transmit command signal is low. During intervals II and V, when the shift register is outputting a binary zero, the encoder output is high during the first subinterval and low for the second and third subinterval. During interval Ill and IV, when the shift register is outputting a one, the encoder output is high during the first two subintervals and low during the third subinterval.

During reconversion of the encoder output signal at the decoder, a convenient timing signal is derived by the transition of the pulse from a low state (subinterval III) to a high state (subinterval l). The timing signal so derived provides synchronization.

The "power of circuit block 79 (FIG. 5) is contained within the output and control circuit and oper ates to sense the removal of primary power from the unit. A large filter capacitor (not shown) retains enough of a charge to operate the unit when power is off. However, in order to conserve energy the output control circuit 62 is turned off. Such as where it is only necessary to preserve the data quantities and not continue counting during the power loss, the power off circuit may also be programmed to turn off the clock generator 52 to conserve additional energy.

The decoder-display unit is shown in block diagram form in FIG. 6. This unit accepts the serial output from the encoder through line 80 (via an intervening communications link) and converts and displays same. When double word transmissions are received, the two words can be compared for error detection. (Circuit 62 in FIG. 5 may be conventionally programmed to output double word transmissions.) The binary number received is converted to parallel BCD outputs by BCD counter 82. Display card 83 contains three sevensegment incandescent readouts. A count output provides a pulse train containing a number of pulses equal to the input plus 1. A hold input on line 8] will delay conversion of an input until after a printer or other equipment is ready to accept a new input. Information processed by the unit is displayed on a three-digit seven-segment incandescent display 83.

Returning to the serial input, the shaper circuit 85 comprises a Schmitt trigger circuit and an exclusive OR gate with the gate being programmable to accept either polarity of input signal. When a 10-bit binary number appears on line 80, ten negative pulses will be delivered by the serial shaper to load control 86 via line 84.

if the counter-encoder has been programmed for a double word output, twenty pulses will make up a complete transmission. Again, narrow pulses will designate binary zeroes while wide pulses will denote binary ones.

Timing information is derived by load control 86 from the leading edge of each input pulse, the change between subinterval [11 and subinterval 1, in accordance with discussion in conjunction with FIG. 4. A pair of timing signals are derived from retriggerable single shot multivibrators (not shown) within circuit 86, one of which is triggered by the first pulse in each digit trans mission. This multivibrators time constant is slightly greater than a digit transmission interval, so that if input pulses occur with proper spacing. the multivibrator will remain in a triggered state until after the last pulse of the transmission. The return of the multivibrator to a normal state provides an end of input signal" which is simultaneously transmitted to the other decoder circuits.

If not inhibited by a signal from conversion control circuit 88, load control 86 will gate the input signals to input register 91 and validation circuit 93 via line 92.

The second single shot multivibrator (not shown) within load control 86 is triggered by the leading edge of a gated through input pulse and returns to the stable state in the center of the second time interval of a digit transmission. This transition to the stable state is used to shift the input into register 91 via line 94 in order to sample the input during the second time interval of each digit.

During the transmission of a second 10-bit word, this input shift signal is also used to trigger the validation circuit 93 arriving on line 95. The validation circuit makes a digit by digit comparison of the second word with the first word, which is stored in input register 91, thereby checking the accuracy of same. The load control also provides reset signals to control counter 87 and the validation circuit 93.

Input register 91 is a 10-bit serial shift register. After a new input has been loaded and validated, the number is circulated through the serial subtractor 97 and the input register and reduced by one per cycle until a zero value has been reached. BCD counter 82 counts the cycles required to reduce this binary number to zero in order to accomplish a binary to BCD conversion.

The conversion control circuit comprises logic cir cuitry as well as a clock generator used to clock the conversion process. An end of loading" signal from the load control circuit starts the conversion clock, however if the block is in a HOLD state, the clock will be immediately turned off and a reset signal will be provided to the load control. The status indicator and output will indicate the validity of the input, but the BCD counter 82 and display 83 will remain unchanged.

When in a run state and without a printer hold input (line 81), the completion of a conversion depends on the conditions of the validation block output. If the input was invalid, the conversion clock is immediately turned off and the load control is reset. The status output will go to or remain in the invalid state. Programming will determine whether or not a print command will be generated. When the validation output indicates a valid input a complete conversion is made.

The gate outputs from the conversion control block drive LED indicators to read out the state of the run, data, status, and print delay lines.

From the foregoing, it will be seen that this invention is one well adapted to attain all the ends and objects herein set forth, together with other advantages which are obvious and which are inherent to the structure.

It will be understood that certain features and subcombinations are of utility and may be employed without reference to other features and subcombinations. This is contemplated by and is within the scope of the claims.

As many possible embodiments may be made of the invention without departing from the scope thereof, it is to be understood that all matter herein set forth or shown in the accompanying drawings is to be interpreted as illustrative and not in a limiting sense.

Having thus described my invention, 1 claim:

1. A digital pulse counter and encoder device having at least one input and at least one output, the device operable to parameterize primary pulses appearing at said input in binary form, the device comprising:

a weighted gate register means having a first input and second input and a first output and a second output therefrom, said first input being interconnected with said primary pulses to be counted at said input to said device, said second input being interconnected with a second source of pulses at the input to said device, said weighted gated register means functioning to produce serial binary data on an output thereof that correlates to a number of counted pulses being inputted to said device;

means for continuously recirculating said serial binary data when a primary pulse does not occur during a predetermined register cycle;

a memory means for storing said binary data, said memory means having an input and an output;

means interconnecting said first output of said weighted gated register means having said serial binary data thereon with said memory means input in response to said second source of pulses;

an output control means for converting input data to an output signal suitable for transmission over a communications link, said output control means having a first, second and third input and an output to said communications link, means interconnecting said first output control input with said memory means output;

means interconnecting said second output control input with said second output from said weighted gated register means, said output control means thereby functioning to effect the transmission of data on the control means output communications link that appears on one of said first and second control means inputs, said transmission occurring upon a preselected condition appearing on said third output control means input and corresponding to the number of primary pulses appearing at the input to said device and the elapsed time between said primary pulses.

2. The combination as in claim 1 wherein said weighted gated register means comprises means for sealing pulses delivered thereto, said scaling means comprising a weighting counter having an input and an output, said weighting counter input interconnected with said pulses to be counted at the input of said device;

means for providing a binary count of pulses delivered thereto, said last mentioned means comprising a count register having an input and a first output and a second output, said count register input interconnected to said weighting counter output, said second count register output corresponding to the output from said weighted gated register means which is interconnected with said second output control input;

means for interconnecting said recirculating means with said count register;

gating means for transferring the data in said count register to said memory means in response to said second source of pulses, the gating means having an output and first and second inputs, said gating means output corresponding to the weighted gated register means output interconnected to said memory means input, said first gating means input interconnected to said first count register means output, and said second gating means input interconnected to said second source of pulses, the counter encoder device thereby functioning to count the number of said primary input pulses and the number of said primary input pulses occurring between said second input pulses.

3. The combination as in claim 2 including means for internally synchronizing the device, said synchronization means comprising a clock means for generating a plurality of clock outputs and means interconnecting said clock outputs with said weighting counter, count register, memory means, and output control means.

4. The combination as in claim 3 including means for converting data inputted to said output control means into an output signal suitable for transmission over an external communications link.

5. The combination as in claim 4 including means for maintaining operating power to said counter register and said memory means in the event of a primary power failure.

6. The combination as in claim 5 including decoding means for converting the data outputted by said device into a BCD encoded output signal.

7. The combination as in claim 6 including means for displaying said BCD encoded output signal from said decoder.

8. The combination as in claim 1 wherein said device comprises a clock means for generating a plurality of clock outputs and said weighted gated register means comprises:

means for internally generating said second source of pulses, said last mentioned means comprising a weighting counter having an input and an output, said weighting counter input corresponding to said second weighted gated register means input and interconnected with one of said clock outputs; means for providing a binary count of pulses delivered thereto, said last mentioned means comprising a count register having an input and a first output and a second output, said count register input corresponding to said first weighted gated register input and interconnected with said primary pulses to be counted at the input of the device, said second count register output corresponding to the output from said weighted gated register means which is interconnected with said second output control input;

means for interconnecting said recirculating means with said count register;

gating means for transferring the data in said count register to said memory means in response to said second source of pulses, the gating means having a first input and a second input and an output, said gating means output corresponding to the weighted gated register means output interconnected to said memory means input, said first gating means input interconnected to said first count register means output, and said second gating means input interconnected to said weighting counter output;

the counter encoder device thereby functioning to count the number of said primary input pulses and the number of said primary input pulses occurring between said internally generated second input pulses.

9. The combination as in claim 8 including means for interconnecting said clock outputs with said weighting counter, count register, memory means and output control means to effect the internal synchronization of the device.

10. The combination as in claim 9 including means for converting data inputted to said output control means into an output signal suitable for transmission over an external communications link.

11. The combination as in claim 10 including means for maintaining operating power to said count register and said memory means in the event of a prim: power failure.

12. The combination as in claim 1] including decoding means for converting the data outputted by said device into a BCD encoded output signal.

13. The combination as in claim 12 including means for displaying said BCD encoded output signal from said decoder means for providing a binary count of pulses delivered thereto, said last mentioned means comprising a count register having an input and a first output and a second output, said count register input corresponding to said first weighted gated register input and interconnected with said primary pulses to be counted at the input of the device, said second count register output corresponding to the output from said weighted gated register means which is interconnected with said second output control input;

means for interconnecting said reicrculating means with said count register;

gating means for transferring the data in said count register to said memory means in response to said second source of pulses, the gating means having a first input and a second input and an output, said gating means output corresponding to the weighted gated register means output interconnected to said memory means input, said first gating means input interconnected to said first count register means output, and said second gating means input interconnected to said weighting counter output;

the counter encoder device thereby functioning to count the number of said primary input pulses and the number of said primary input pulses occurring between said internally generated second input pulses.

14. The combination as in claim 1 wherein said device comprises a clock means for generating a plurality of clock outputs and said wt ighted gated register means comprises:

means for internally generating said second source of pulses, said last mentioned means comprising a weighting counter having an input and an output. said weighting counter input corresponding to said second weighted gated register means input and interconnected with one of said clock outputs.

means for providing a binary count of pulses dclivered thereto. said last mentioned means comprising a count register having an input and a first output and a second output, said count register input interconnected with said weighting counter output. and said second count register output corresponding to the output from said weighted gated register means which is interconnected with said second output control input;

means for interconnecting said recirculating means with said count register;

gating means for transferring the data in said count register to said memory means in response to said second source of pulses. the gating means having a first input and a second input and an output, said gating means output corresponding to the weighted gated register means output interconnected to said memory means input said first gating means input interconnected to said first count register means output, said second gating means input interconnected to said first source of pulses and corresponding to said first weighted gated register means input;

the counter encoder device thereby functioning to measure the time elapsing since the last pulse from said primary source of pulses and the time between the last two of said primary pulses.

[5. The combination as in claim 14 including means for interconnecting said clock outputs with said weighting counter, count register. memory means and output control means to effect the internal synchronization of the device 16. The combination as in claim 15 including means for converting data inputted to said output control means into an output signal suitable for transmission over an external communications link.

17. The combination as in claim 16 including means for maintaining operating power to said count register and said memory means in the event of a primary power failure l8. The combination as in claim 17 including decoding means for converting the data outputted by said device into a BCD encoded output signal.

19. The combination as in claim 18 including means for displaying said BCD encoded output signal from said decoder.

20. A method of counting electrical pulses appearing on a primary input line and determining the number of such input pulses occurring between transfer pulses which appear on a secondary input line, the method comprising the steps of:

inputting said electrical pulses to a weighting counter thereby generating scaled output pulses corresponding to a predetermined number of said electrical input pulses;

inputting said scaled output pulses to a count register for counting said pulses in binary form;

til

recirculating said counted scaled output pulses when a scaled output pulse does not occur during a predetermined register cycle; delivering the binary data in said count register to an output control circuit thereby counting the number of pulses occurring on said primary input line;

delivering the binary data in said count register to a gate;

triggering the gate by applying an externally generated transfer pulse on said secondary input line. thereby transferring said binary data to a storage register thereby recording the data delivered thereto; and

sampling the output of said storage register in an output circuit thereby determining the number of electrical pulses which have appeared on said primary input line between transfer pulses appearing on said second input line.

21. The method as in claim 20, including the further step of converting data delivered to said output control circuit to a signal suitable for transmission over a communications link.

22. A method of counting electrical pulses appearing on an input line and determining the number of such input pulses occurring in a predetermined time interval, the method comprising the steps of:

inputting said electrical pulses to a count register for counting said pulses in binary form; recirculating the binary count generated by said count register when an electrical pulse does not occur during a predetermined register cycle;

delivering the binary count register data to an output control circuit thereby counting the number of pulses occurring on said input line;

delivering the binary count register data to a gate;

internally generating periodic transfer pulses by generating a clock pulse and inputting the clock pulse to a weighting counter; triggering the gate with said transfer pulses, thereby transferring the count register data to a storage reg ister and recording the data delivered thereto; and

sampling the output of said storage register in an out put circuit thereby determining the number of input pulses which have occurred between the last two of said periodic transfer signals.

23. The method as in claim 22 including the further step of converting data delivered to said output control circuit to a signal suitable for transmission over a communications link.

24. A method of measuring the time occurring since an input pulse and determining the elapsed time between the last two of said input pulses appearing on an input line, the method comprising the steps of:

internally generating a periodic count pulse by first generating a clock pulse and inputting the clock pulse to a weighting counter;

counting the periodic count pulses outputted by the weighting counter in a count register; recirculatingthe count generated by said count register when said weighting counter does not output a pulse during a predetermined register cycle; delivering a first output of the count register to an output control circuit to thereby determine the time since the last of said input pulses;

delivering the count register data to a first gate input;

delivering said input pulses to a second gate input;

transferring to count register data to a storage register to record same in response to said input pulses; and

sampling the output of said storage register in an output circuit thereby determining the elapsed time between the last two of said input pulses.

UNITED STATES .--TEL\=TT OFFICE CERTIFICATE OF CGR ECTION Inventor(s) George L. Buenger It: is certirled that error appears in the above-identified Daren: and that said Le ters Patent are hereby corrected as shown below:

' Colu1 nn 8, Claim 1, line 25, "gate" should be -gated Column 9, claim 5, line 40, "counter" Shoo-l d b -count-.

Column 13, Claim 24; line 1, "'to (first occurrence) should Signed and Scaled this twenty-sixth D ay of August 1975 {SEAL} Arrest:

RUTH C. MASON C. MARSHALL DANN Alluring Officer Commissioner of Parems and Trademarks

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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5303279 *Feb 4, 1993Apr 12, 1994Mitsubishi Denki Kabushiki KaishaTimer circuit
US6781923 *Sep 13, 2000Aug 24, 2004Timex Group B.V.Method and apparatus for tracking usage of a multi-functional electronic device
US7187626Jun 22, 2004Mar 6, 2007Timex Group B.V.Method and apparatus for tracking usage of a multi-functional electronic device
US20040223414 *Jun 22, 2004Nov 11, 2004Timex Group B.V.Method and apparatus for tracking usage of a multi-functional electronic device
Classifications
U.S. Classification377/56, 377/32, 377/84, 368/118
International ClassificationG01G23/37, G01G23/18, H03K21/00, G06F7/60, H03K21/08, G06F7/62
Cooperative ClassificationG06F7/62, H03K21/08, G01G23/37
European ClassificationH03K21/08, G01G23/37, G06F7/62