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Publication numberUS3893170 A
Publication typeGrant
Publication dateJul 1, 1975
Filing dateSep 3, 1974
Priority dateSep 18, 1973
Also published asDE2346934A1
Publication numberUS 3893170 A, US 3893170A, US-A-3893170, US3893170 A, US3893170A
InventorsKellner Josef, Kowalczyk Hans
Original AssigneeSiemens Ag
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Digital phase control circuit
US 3893170 A
Abstract
A digital phase control circuit for the production of a rectangular wave oscillation, synchronized with the aid of data pulses, in which a counter is operative to count pulses of a counter pulse train, counting from a constant initial value to an adjustable final value, with such final value determining the frequency of the rectangular wave oscillation and the final value being adjusted, on the arrival of a data pulse, in dependence upon the contents of the counter, characterized by such counter being in the form of an up-down counter which counts pulses upwardly until a final value is reached and then downwardly to the original initial value, in which the final value is increased or reduced, following the arrival of a data pulse, by a fraction of the final value, while the counter correspondingly counts upwards or downwards, and if the content of the counter is not greater than half the final value, the rectangular wave oscillation being derived at the output of a bistable trigger stage, which is set or reset when the counting content of the counter is correspondingly smaller or greater than half the final value.
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United States Patent 1 Kellner et al.

[ DIGITAL PHASE CONTROL CIRCUIT [75] Inventors: Josef Kellner; Hans Kowalczyk,

both of Germering, Germany [73] Assignee: Siemens Aktiengesellschaft, Berlin & Munich, Germany Primary Examiner-Vincent P. Canney Attorney, Agent, or Firm-Hill, Gross, Simpson, Van

Santen, Steadman, Chiara & Simpson 51 July 1,1975

[ ABSTRACT A digital phase control circuit for the production of a rectangular wave oscillation, synchronized with the aid of data pulses, in which a counter is operative to count pulses of a counter pulse train, counting from a constant initial value to an adjustable final value, with such final value determining the frequency of the rectangular wave oscillation and the final value being adjusted, on the arrival of a data pulse, in dependence upon the contents of the counter, characterized by such counter being in the form of an up-down counter which counts pulses upwardly until a final value is reached and then downwardly to the original initial value, in which the final value is increased or reduced, following the arrival of a data pulse, by a fraction of the final value, while the counter correspondingly counts upwards or downwards, and if the content of the counter is not greater than half the final value, the rectangular wave oscillation being derived at the output of a bistable trigger stage, which is set or reset when the counting content of the counter is correspondingly smaller or greater than half the final value.

21 Claims, 6 Drawing Figures 1 DIGITAL PHASE CONTROL CIRCUIT BACKGROUND OF THE INVENTION The invention is directed to a digital phase control circuit for the production of rectangular wave oscillations, synchronized by means of data pulses, in which a counter is provided which counts pulses of a counter pulse train of adjustable frequency from a constant initial value to an adjustable final value, with the final value determining the frequency of the rectangular wave oscillation and the final value being set in dependence upon the contents of the counter at the arrival of the data pulse.

In data transmission from a data transmitter to a data receiver, it frequently is necessary to produce, in the data receiver, timing pulses which are synchronized with data pulses of the data transmitter. Problems here occur that, as a result of variations in parameters with respect to time in the data transmitter. the data pulses have a frequency which varies relative to time. Further, the data pulses may be received only incompletely as a result of interference. Such interference may consist of interference pulses occurring between data pulses or that one or more data pulses fail to appear.

An example of a data transmission device which is subject to the above-mentioned problems is a magnetic tape store for the storage of binary signals in which the binary signals are stored in conjunction with a selfpulsing recording operation. A conventional, selfpulsing recording process for magnetic tape stores, currently employed, is the phase encoding recording process in which the binary signals are stored on the magnetic tape as changes in direction of the magnetic flux. Thus, the binary signal 1 is represented by a change from negative to positive magnetic flux, and the binary signal is represented by an oppositely directed change. These changes in the magnetic flux representing a binary signal are generally termed bit flux changes. It will be appreciated that with the utilization of flux changes to designate the binary signals, it is necessary to insert an auxiliary flux change between two adjacent bit flux changes when two identical binary signals successively follow one another.

In the read-out of magnetic tape which has been so recorded upon, the read-out signals are induced in a magnetic head, and from such read-out signals a digitalization circuit derives rectangular data pulses which are referred to as bit" or auxiliary" pulses in dependence upon whether they are produced by bit or auxiliary flux changes.

In order to derive the stored binary signals from the read-out signals, the bit pulses must be separated from the auxiliary pulses, which operation is effected by means of a rectangular wave oscillation which is referred to as "read-out window." The read-out window is always open (binary I) when a bit pulse arrives and is always closed (binary 0) during the period when an auxiliary pulse can arrive.

The recorded binary signals are preceded and followed by synchronization signals in order to so set the read-out window that it will always possess a correct phase state and the correct frequency for the read-out of the binary signals.

As the intervals between the data pulses can fluctuate about a theoretical value because of changes in the speed of the magnetic tape, the frequency of the readout window must be constantly matched or adapted to the frequency of the bit pulses. Further, the phase of the read-out window must be so synchronized that the bit pulses occur, insofar as possible. in the center of the open read-out window, and the auxiliary pulses occur, insofar as possible, in the middle of the closed read-out window. Further, changes in the intervals between the data pulses as a result of the auxiliary pulses which occur and displacements of individual read-out signals through the magnetic properties of the magnetic tape and the magnetic head (peak-shift) must nott be permitted to disturb the synchronization between the data pulses and the read-out window. In other words, the read-out window must, even in the case of a temporary drop-out of the data pulses, due to interferernce and the like, maintain the previously existing frequency to enable the synchronization to be again continued with correct phase at the end of the drop-out period.

Synchronization circuits are already known in the form of control circuits which utilize a phase detector and a voltage controlled oscillator which are constructed with components such as employed in analog circuit technique. A disadvantage of such circuits is the dependence upon component tolerances, environmental conditions and supply voltages. Further, such circuits frequently have additional disadvantages in that they involve components which require adjustments which must be made and often are very difficult to change over to other data pulse frequencies.

A phase control circuit has heretofore been proposed which can be exclusively constructed from integrated digital modules and in which the voltage controlled oscillator is replaced by a first dual counter, which counts up from a constant initial value to an adjustable final value of the pulses of a counter pulse train of constant frequency, and which is subsequently reset to its initial value. With each resetting a timing pulse is produced and emitted at the output of the phase control circuit. The frequency of the timing pulses can be altered by means of the final value and is inversely proportional to the final value. In such a phase control circuit, the final value is calculated, by means of a calculating unit, from the contents of the first dual counter upon the arrival of a data pulse, and from the contents of a second dual counter in such manner that the frequency of the timing pulses is, insofar as possible, equal to the frequency of the data pulses, and that the timing pulses occur, insofar as possible, in the middle of the interval between the data pulses. Such proposed phase control circuit has the disadvantage that both the bit pulses and the auxiliary pulses are utilized for phase control and thus because of the changing pulse intervals does not have a constant control function. It also has the further disadvantage that the final value of the first dual counter is so set that it is proportional to its content on the arrival of a data pulse even when the frequency of the data pulse remains constant and individual data pulses are displaced by single phase jumps.

SUMMARY OF THE INVENTION The present invention has as its objective to provide a phase control circuit which has a low degree of sensitivity to non-recurring phase jumps of individual data pulses.

The desired objective, in a phase control circuit of the type described is, in accordance with the invention. achieved by the utilization of an up-down counter which is operative to upwardly count until the final value is reached and thereafter counts downward to the initial value, with a control circuit including a device which increases or reduces the final value after the arrival of a data pulse, by a fraction of the final value at the time when the data pulse arrives, while the counter counts upwards or downwards, and the contents of the counter are no greater than half the final value. A first bistable trigger stage is provided which is set or reset when the contents of the counter are either smaller than or greater than half the final value and which supplies the rectangular wave oscillation at its output.

The phase control circuit of the invention has the advantage of a high resistance to faults, as all the pulses, arriving while the contents of the counter are greater than halfthe final value, are inactive with respect to the control function, and as the final value is not set proportional to the contents of the counter upon the arrival of a data pulse, but is adjusted, in each case, by a fraction ofthe stored final value. It also has the further advantage that it can be constructed with a very low cost outlay exclusively from integrated digital modules which are commercially procurable.

Likewise with suitable design, the final value of the counter may be altered without the use ofa calculating unit and with a low cost outlay by suitable circuit design, i.e., if the device in the control circuit which in creases or reduces the final value contains a final value counter which stores the final value, if the final value counter is in the form of the up-down counter, ifa dif ference counter is included and the final value is in creased or reduced by a number of counter pulses which are applied to a first counter input and a second counter input, respectively, of the final value counter,

and if the difference counter counts off the number of the counter pulses at one of the counter inputs of the final value counter.

A uniform degree of sensitivity, which is independent of the magnitude of the final value, is achieved if the number of counter pulses atone of the counter inputs of the final value counter is equal to a fraction, preferably one sixty-fourth of the final value.

The counting of the counter pulses can be achieved with a relatively low outlay, if during each rectangular wave oscillation, the difference counter is set at a frac tion. preferably one sixty-fourth of the final value and that with each counter pulse supplied to one of the counter inputs of the final value counter. counting is effected downwards to a value of 0.

If a second bistable trigger stage is provided which is set when the contents of the counter are equal to the final value and is reset when the contents ofthe counter are equal to the initial value, the counter device of the counter may be advantageously so switched over that the counter will count downward and upward when it is correspondingly set and reset.

If only the phase and not the frequency of the rectangular wave oscillation is to be altered when a data pulse arrives displaced by a small amount from its theoretical time of arrival, it is advantageous to adjust the final value only when a data pulse arrives outside an expectation period. Such expectation period may be derived with a low outlay by providing a comparator which :ompares the contents ofthe counter with a reference value, preferably one thirty secorid of the final value and which sets and resets a third bistable trigger stage when the contents of the counter become smaller than or greater than the respective reference values.

In order to speed up the control process and to insure the stability of the phase control circuit, it is advantageous to reset the counter at its initial value when a data pulse arrives within the expectation period and/or to provide, in the control circuit devices which cancel out a change in the final value by means ofa data pulse. when the next data pulse to arrive, while the contents of the counter are lower than half the final value, occurs in the expectation period.

In effecting the desired phasing the phase control circuit may be rapidly set to the frequency and the phase of the data pulses by the provision of having the final value counter, during a synchronization sequence after the arrival of a synchronization pulse, count upward with half the counter pulse train frequency until the next synchronization pulse arrives, and if the counter is set, by means of such synchronization pulse, to the initial value.

If, in connection with the recovery of the binary signals stored on a magnetic tape, by means of the phase encoding recording method, the phase control circuit is employed to separate the bit and auxiliary pulses produced by bit and auxiliary flux changes, a constant control function will be achieved by selection of the fre quency of the rectangular wave oscillation equal to the frequency of the bit pulses and with the control circuit containing an AND gate which links the data pulses with the rectangular oscillation and employs, for control purposes, the signals at the output ofthe AND gate instead of the data pulses.

BRIEF DESCRIPTION OF THE DRAWINGS in the drawings wherein like reference characters indicate like a corresponding parts:

FIG. I shows a chart illustrating the relationships involved in the recording of binary signals on a magnetic tape;

FIG. 2 is a block circuit diagram of a digital phase control circuit employing the invention;

FIG. 3 is a diagram illustrating various signals of a digital phase control circuit;

FIG. 4 is a schematic diagram, in block form, of a frequency divider circuit;

FIG. 5 is a schematic diagram, in block form, of a readout window generator; and

FIG. 6 is a schematic diagram, in block form, of a control circuitv DETAIEED DESCRIPTION OF THE INVENTION Referring to the drawings and in particular to FIG. 1, the line BS represents a plurality of binary signals 0 or I, recorded on a magnetic tape. In connection with the recording thereof, in accordance with the phase encoding recording method, the binary signals BS are designated by a curve of the magnetic flux MP in the longitudinal direction of the magnetic tape as illustrated in FIG. 1 with the length unit s being plotted in the abscissa direction. It will be noted that the spacing between the flux changes on the magnetic tape varies in dependence upon the recorded binary signals BS by a factor of 2, and that an auxiliary flux change is inserted between two adjacent bit flux changes when identical binary signals follow one another. FIG. 1 also illustrates the read-out signals LS which are induced in a mag netic head upon readout of the magnetic tape which has been recorded upon the above-described manner, with the time unit t being plotted in the abscissa direction. A digitalization circuit is also provided which, at the respective times at which the read-out signals LS exhibit peaks. produces rectangular wave data pulses DI, which data pulses are assigned to the bit flow changes, and are designated as bit pulses, which are represented in FIG. 1 by wide pulses while the data pulses DI which are assigned to the auxiliary flux changes, referred to as auxiliary pulses, are represented in FIG. I by narrow pulses.

Also illustrated in FIG. 1 is the read-out window LP by means of which the bit pulses are separated from the auxiliary pulses. As will be apparent from a reference to FIG. 1 whenever a data pulse DI arrives while the read-out window is open (binary l such pulse is recognized as a bit pulse, and whenever a data pulse DI arrives while the read-out window is closed (binary 0), such pulse is recognized as an auxiliary pulse. When the read-out signal LS is positive, the binary signal I is recognized as the read-out binary signal BL, and whenever the read-out signal LS is negative, the binary signal 0 is so recognized.

The synchronization signals preceding or following the recorded binary signals may, for example, comprise a predetermined number of regularly changing binary signals 1 and 0, and on read-out these synchronization signals produce a sequence of synchronization pulses which consists of bit pulses and contains no auxiliary pulses. In FIG. 1, the first five binary signals of the sequence of binary signals BS can be considered to be synchronization signals.

The circuit diagram of FIG. 2 illustrates, in block form, a digital phase control circuit utilizing a pulse generator IG, a control circuit RS, a frequency divider FT and a read-out window generator LG. The read-out window generator LG and the frequency divider FT, taken together, represent the control path of the phase control circuit. At a first input the frequency divider FT is supplied with a counter pulse train ZT which is produced by the pulse generator IG. The frequency divider FT is operated to divide the frequency of the counter pulse train ZT in accordance with a variable division ratio and contains a counter which by means of the counter pulse trains ZT constantly count up from an initial value of O to an adjustable final value E, at which the counter begins to count down to the initial value of 0V The final value E is applied to a second input of the frequency divider FT a phase signal PS is supplied to a third input of the frequency divider for effecting a resetting of the counter to 0. The signal ZR appears at the output of the frequency divider FT and indicates the counting direction of the counter while the count Z appears at another output of the frequency divider, which count can be considered as a digitally represented triangular wave oscillation. The final value E can be utilized in adjusting the frequency thereof, and the phase can be varied by resetting the counter by means of the phase signal PS.

Utilizing the count Z and the final value E, the readout window generator LG produces the read-out window LF. The generator LG may contain a comparator which compares the count Z with half the final value and when the Z is equal to half the final value and the counter counting downward or upward, a bistable trigger stage is set or reset in accordance therewith. The output signal of the bistable trigger stage represents the read-out window LF and possesses the same frequency as the triangular-shaped oscillation and its phase is displaced in relation to the reversal points of the triangular-shaped oscillation by The read-out window LF is conducted to the control circuit RS and to a decoder circuit (not illustrated) and by means of the read-out window LF recovers the recorded binary signals BS from the data pulses DI. The control circuit RS thus produces the final value E and the phase signal PS in dependence upon the times at which the data pulses DI arrive. Likewise, by means of the final value E and the phase signal PS, the phase and the frequency of the read-out window may be so altered that a bit pulse arrives, insofar as possible, in the center of an open read-out window LF and an auxiliary pulse occurs, insofar as possible, in the center of a closed read-out window LF.

If a bit pulse arrives while the counter is counting upwardly, it signifies that the frequency of the triangular wave oscillation is too great and in this case the control circuit RS increases the final value E and thus causes a reduction in the frequency of the triangular wave oscillation. In like manner, the final value E is correspondingly reduced if a bit pulse arrives while the counter is counting downwardly.

In addition to the above, an expectation period EB for the bit pulses is produced in control circuit RS. The employment of an expectation period EB serves to speed up the control operations. insuring the stability of the phase control circuit and rendering the phase control circuit insensitive to small fluctuations in the bit pulses about their theoretical states. Consequently, if a bit pulse arrives within the expectation period E8, the final value is not altered but only the phase signal PS is produced. In order to increase the stability. in addition thereto. a previous alteration of the final value E is cancelled out when a bit pulse arrives within the expectation period EB.

To prevent auxiliary pulses occurring at irregular intervals from affecting the control processes, such pulses are, by means of the read-out window LF, gated out in the control circuit,

FIG. 3 illustrates various signals occurring during the operation of the phase control circuit illustrated in FIG. 2, with the time units t being plotted in the abscissa direction and the amplitudes of the signals being plotted in the ordinate direction. The count Z is represented by a triangular wave function in analog form. In addition, FIG. 3 also illustrates the data pulses DI which are produced in the digitilization circuit from the peaks of the read-out signals LS. Again, the bit pulses are represented by wide pulses while the auxiliary pulses are represented by narrow pulses. For the purposes of illustration, it will be assumed that between the times H and t6, the frequency of the data pulse DI is constant and equal to the nominal frquency and that at the time 14, a phase jump occurs, while between the times 16 and I7, the frequency is likewise constant but greater than the nominal frequency. FIG. 3 also illustrates the readout window LF and the expectation period EB for the bit pulses. Further details of FIG. 3 will be described in conjunction with the circuit diagrams shown in FIGS. 4 to 6, illustrating portions of the digital phase control circuit.

In the exemplary embodiment illustrated in FIG. 4, the frequency divider FT contains an eight digit dual counter ZA which counts upwards when the counter pulse trains ZT are present at its input U] and which counts downward when the counter pulse trains ZT are present at its input D1. The frequency divider also contains an eight digit comparator V] which compares the count Z at the output of the counter ZA with the final value E, a bistable trigger stage UD being provided which determines whether the counter ZA is to count upward or downward and is operatively connected to two NAND gates N1 and N2.

The frequency divider FT is supplied with the counter pulse trains ZT having a constant frequency equal to 256 times the nominal frequency of the bit pulses. If the bistable trigger stage UD is set, the counter pulse train ZT is conducted over the NAND gate NZ to the counter input UI and the counter ZA counts upwards. The final value E, present as a dual number at the frequency divider FT, is compared with the count Z, and in the event of identity, the comparitor Vl emits a pulse to the bistable trigger stage UD.

Upon the next counter pulse train ZT, the bistable trigger stage UD is reset and the counter pulse train ZT is now supplied over NAND gate N1 to the counter input Dl whereby the counter ZA counts downwards. When the counter reaches the initial value 0, a negative signal 80 is emitted at its output B] which again sets the bistable trigger stage UD, and the counter ZA again counts upward to the final value E, etc.

it will be noted from the count Z, represented in FIG. 3 in analog form. as a triangular wave oscillation, that the frequency of the triangular wave oscillation is inversely proportional to the size ofthe final value E. The phase of the triangular wave oscillation is established by means of the phase signal PS at the reseting input R of the counter ZA, which signal sets the counter to the initial value 0.

The read-out window generator LG illustrated in FIG. 5 contains a bistable triger stage FE and compara- [or V2 which compares the count Z with half the final value. As the final value E is in the form ofa dual num- Jer, it is possible to readily derive the final value, with- )ut additional circuitry outlay, by displacement by one iual position to the right. Upon equality between the :ount Z and half the final value. a pulse is emitted from he comparator V2 to two AND gates Al and A2, and f the identity occurs while the counter ZA is counting lownward, the signal AB releases the AND gate Al vith such pulse being operable in conjunction with the text counter pulse train ZT to set the bistable trigger tage FE. On the other hand, if the equality occurs vhile the counter ZA is counting upwards, the signal \UF releases the AND gate A2 and the pulse, in con unction with the next counter pulse train ZT resets the iistable trigger stage FE. The signals AUF and AB thus :orrespond to the signal ZR designating the counting lirection in FIG. 2. The read-out window LP is sup ilied at the output of the bistable trigger stage FE. The ialf final value is illustrated in FIG. 3 as a dash-dot line. t will be noted that the read-out window is a binary l .5 long as the count Z is lower than the half final value nd is a binary 0 as long as the count Z is greater than ialf final value.

in the exemplary embodiment of the control circuit 1S, illustrated in FIG. 6, binary switching elements are mployed in the production of the expectation period EB and for changing the final value E, and a final value ounter E2 is provided in which the final value E is tored.

The final value counter E2 is set at the frequency of the synchronization pulses during the sequence of the latter. The frequency of such pulses can be measured by means of the final value counter EZ by counting of the number of the counter pulse trains ZT between two synchronization pulses. As the counter ZA and the frequency divider FT counts upward and downward between two bit pulses. the final value counter EZ need store only half the number of counter pulse trains ZT, and in FIG. 3 it is assumed that synchronization pulses arrive at the times [l to !4. Thus at the time 11 the final value counter E2 is supplied with a pulse train ET which is produced from the counter pulse trains ZT by having the frequency.

The phasing pulse train ET is supplied to the counter input U2 of the final value counter EZ over an AND gate A3 of the control circuit R8. The final value counter EZ, like the counter ZA, is an eight digit dual counter which counts upwards and downwards when pulses are supplied at the respective counter inputs U2 and D2. The counter EZ counts upward until the time r2 at which the next cynshronization pulse arrives. At the same time with the synchronization pulse which arrives at the time T2, the counter ZA is set, over the reset input R, to the initial value 0. The times t] and [2 can be two arbitrary points of time at which synchronization pulses arrive. For reasons of security, it is advantageous to select two synchronization pulses in the middle of the sequence of such pulses.

As the frequency of the counter pulse train ZT is equal to 256 times the nominal frequency of the bit pulses, the final value counter EZ counts up to the final value of 128 as a result of the phasing pulse trains ET.

The counter ZA, after the time 12, is again caused to count upwardly and when its count Z is equal to half the final value E/2 64, the bistable trigger stage FE in the read-out window generator LG is reset and the readout window LF assumes the binary value 0. The counter ZA counts up to the final value E 128, and then again counts downward. When the downward count Z is again equal to half the final value E/2 64, the bistable trigger stage FE is again set and the readout window LF assumes the binary value 7.

Upon arrival of the next synchronization pulse at the time 13. when the count Z 0, it arrives within the expectation period EB and the phase signal PS is supplied over a NAND gate N3 to the counter ZA, but as such counter already has a count of Z 0, the phase signal PS has no additional influence. For the production of the final value period EB, the control circuit contains a comparator V3, a bistable trigger stage F5 and two AND gates A5 and A6. The production of the final value period EB is achieved in a manner similar to that of the read-out window LF, with the comparator V3, however, being supplied with one thirty-second of the final value E instead of half the final value. For this purpose, the final value E is conducted to the comparator V3 displaced five dual positions to the right. The ex pectation period E8 is a binary or 2 when the counter ZA is respectively smaller than or greater than one thirty-second of the final value. Upon the counter ZA reaching the initial value of O, the negative signal BO supplies one sixty-fourth of the final value to the inputs of the difference counter DZ, which likewise is a dual counter.

When the count Z is again equal to one thirty-second of the final value, the expectation period EB becomes a binary O and when the count is again equal to half the final value E/2, the read-out window LF is likewise a binary 0. The counter ZA counts up to the final value E and back down again to the initial value 0, etc.

It is assumed that at the time [4, as a result of a phase shift, a bit pulse occurs so prematurely that although it arrives within the open read-out window LF, it arrives before the expectation period EB. The bit pulse thereby sets an AND gate A7. a bistable trigger stage F2 and a bistable trigger stage F3, the latter stage indicating that the final value E must be reduced as the bit pulse arrived while the counter VA was counting downward, while the bistable trigger stage F2 is storing the information that the bit pulse did not arrive during the expectation period EB. Upon the setting of the bistable trigger stage F2, a further bistable trigger stage F4 is set which stores, until the arrival of the next bit pulse, the information that the final value counter EZ has previously counted downward.

Upon the counter ZA again reaching the count Z=O, one sixty-fourth of the final value E is again written into the difference counter DZ and as the count Z is again greater than half the final value and the read-out window LF has assumed a binary value 0, counter pulse trains ZT are supplied over AND gate A8 and NAND gate N4 to the counter input D2 of the final value counter DE and the latter therefore counts downward. At the same time, counter pulse trains are also supplied over gate A9 to the counter input D3 of the difference counter DZ and the latter likewise counts downward. When the contents of the difference counter is 0, there appears at the output B thereof a negative signal which resets the bistable trigger stage F3 and thus terminates the downward counting of the difference counter DZ and of the final counter EZ.

As the contents of the difference counter DZ was one sixty-fourth of the final value E, the final value counter EZ can at the maximum be reduced by one-fourth of its content. It is of no importance at which count Z of the counter ZA between half the value and one thirtysecond of the final value E the bit pulse arrived. In the illustration of FIG. 3, the final value E has been re duced by two counter units.

An auxiliary pulse arrives between the two bit pulses arriving at the times [4 and t5. To prevent such auxiliary pulse from affecting the control, it is gated out in an AND gate A4 by means of the read-out window LF.

As the frequency of the bit pulses has not changed, the next bit pulse arrives at itd theoretical time t5 and although it arrives within the expectation period EB, it does not arrive within the count Z=O as the final value E has been reduced with the previous bit pulse. The phase signal PS which resets the counter ZA to O is again supplied over the NAND gate N3. A bistable trigger stage F1 is also set over a NAND gate NS and the bistable trigger stage F2 is reset over an AND gate A10. The bistable trigger stage Fl supplies counter pulse trains ZT over NAND gate N6 and AND gate A3 to the input U2 of the final value counter EZ, which thus counts upward. In this way the adjustment of the final value counter EZ, as the result of the phase jump at the time 4, is cancelled out.

It has been assumed that the frequency of the bit pulses betqeen the times 16 and :7 of FIG. 3 is constant and greater than the nominal frequency. Consequently, the final value E must be reduced with each bit pulse in order to match the frequency of the read-out window LP to the frequency of the bit pulses. For this purpose the final value E is reduced with each bit pulse in the same manner as described with respect to the phase jump at the time t4.

The final value E is increased correspondingly when the frequency of the bit pulses becomes lower than the nominal frequency. In this case the final value E is increased in that the bistable trigger stage Fl. instead of the bistable trigger stage F3 is set, with the bistable trigger stage F4 being reset. and the counter pulse trains ZT supplied over the NAND gate N6 and AND gate A3 to the counter input U2 of the final value counter EZ.

As a result the final value E is increased or reduced with each bit pulse to effect a matching of the frequency of the readout window LF to the frequency of the bit pulses. The final value E thus is reduced with each bit pulse in the same manner as in the case of the phase jump at the time t4.

The final value E is correspondingly increased when the frequency of the bit pulses becomes lower then the nominal frequency. In this case, the final value E is increased as the bistable trigger stage F1 is set instead of the bistable trigger stage F3, the bistable trigger stage F4 is reset and the counter pulse trains ZT are supplied over NAND gate N6 and AND gate A3 to the counter input U2 of the final value counter EZ.

It will be appreciated that the frequency of the readout window LF is thus matched to the frequency of the bit pulses irrespective of the changes that may take place.

lt will be understood that various modifications can be made to the described embodiments without departing from the scope of the present invention.

We claim as our Invention:

1. In a digital phase control circuit for the production of a rectangular wave oscillation in which synchronization of the rectangular wave oscillation is effected with the aid of data pulses, in which a counter is operative to count pulses of a counter pulse train, counting from a constant initial value to an adjustable final value, with such final value determining the frequency of the rectangular wave oscillation and the final value being adjusted on the arrival of a data pulse, in dependence upon the contents of the counter, the combination of such counter being in the form of an up-down counter which counts pulses upwardly until a final value is reached and then downwardly to the original initial value, a control circuit operatively connected to said counter, having means for increasing the final value or reducing the same, following the arrival of a data pulse, by a fraction of the final value, while the counter correspondingly counts upwardly or downwardly and if the content of the counter is not greater than half the final value, and a bistable trigger stage, at the output of which the rectangular wave oscillation is derived, operatively connected for seting or resetting when the counting content of the counter is correspondingly smaller or greater than half the final value.

2. A digital phase control circuit according to claim 1, wherein said means in the control circuit. which increases or reduces the final value, comprises a final value counter in which the final value is stored, and a difference counter, said final value counter likewise being an up-down counter, the final value of which is increased by a number of counter pulses applied to a first counter input, of such final value counter, or reduced by a number of pulses applied to a second counter input thereof the difference counter being connected to count the number of counter pulses at one of said counter inputs of said final value counter. and operatively connected to selectively end downward counting of the final counter.

3. A digital phase control circuit according to claim 2, wherein means is connected to one of the counter inputs of the final value counter operative to supply a number of counter pulses thereto with is equal to a fraction, preferably one sixty-fourth of the final value.

4. A digital phase control circuit according to claim 3, wherein said difference counter is so constructed that during each rectangular wave oscillation it is set a fraction, preferably one sixty-fourth of the final value, and with each counter pulse at one of the counter inputs of the final value counter it counts down to O.

5. A digital phase control circuit according to claim 4, comprising in further combination, a second bistable trigger stage, and means for setting such stage when the contents of the first-mentioned counter is equal to the final value and for resetting the same when the content of the first-mentioned counter is equal to the initial value, to selectively respectively effect a downward or upward counting therein.

6. A digital phase control circuit according to claim 5, comprising in further connection. means for producing an expectation period, and means responsive thereto for adjusting the final value when the data pulse arrives outside such expectation period.

7. A digital phase control circuit according to claim 6, wherein the means for producing the expectation period comprises a third bistable trigger stage. and a comparator for comparing the contents for the firstmentioned counter with a reference value, preferably one thirty-second of the final value, operative to set or reset such third bistable a trigger stage when the content of the counter becomes smaller than or greater respectively than the reference value, the output of said stage determining the expectation period.

8. A digital phase control circuit according to claim 7, comprising in further combination, means for effecting resetting of the counter to its initial value when a data pulse arrives within the expectation period.

9. A digital phase control circuit according to claim 8, comprising in further combination, means in the control circuit for canceling a change in the final value by a data pulse when the next arriving data pulse arrives in the expectation period while the content of the first-mentioned counter is lower than half the final value.

[0. A digital phase control circuit according to claim 9, comprising in further combination, means operable during a synchronization sequence, after the arrival of a synchronization pulse to effect a counting in the final value counter with half the pulse train frequency until the next synchronization pulse arrives, and means for setting the first-mentioned counter, with such synchronization puEse, to the initial value.

11. A digital phase control circuit according to claim 10, for use in a magnetic tape store in which binary sig nals are recorded with the aid of the phase encoding recording method and in which on the read-out of a mag netic tape, the bit and auxiliary pulses produced by the bit and auxiliary flux changes are separated from one another, wherein means are provided for supplying counter pulse trains having a frequency which is so selected that at a given final value, the frequency of the rectangular wave oscillation is equal to the frequency of the bit pulses.

12. A digital phase control circuit according to claim ll, comprising in the control circuit, an AND gate linking the data pulses with the rectangular wave oscillation, with the signals at the output of the AND gate forming control pulses which are fused for the control instead of the data pulses.

[3. A digital phase control circuit according to claim 1, comprising in further combination. a second bistable trigger stage, and means for setting such stage when the contents of the first-mentioned counter is equal to the final value and for resetting the same when the content of the first-mentioned counter is equal to the initial value. to selectively respectively effect a downward or upward counting therein.

14. A digital phase control circuit according to claim 13, comprising in further combination, means operable during a synchronization sequence, after the arrival of a synchronization pulse to effect a counting in the final value counter with half the pulse train frequency until the next synchronization pulse arrives, and means for setting the first-mentioned counter, with such synchronization pulse, to the initial value.

15. A digital phase control circuit according to claim 1, comprising in further connection, means for producing an expectation period, and means responsive thereto for adjusting the final value when the data pulse arrives outside such expectation periodv 16. A digital phase control circuit according to claim 15, wherein the means for producing the expectation period comprises a third bistable trigger stage, and a comparator for comparing the contents for the first mentioned counter with a reference value, preferably 1/32 of the final value, operative to set or reset such third bistable a trigger stage when the content of the counter becomes smaller than or greater respectively than the reference value, the output of said stage determining the expectation period.

17. A digital phase control circuit according to claim 16, comprising in further combination, means for effecting resetting of the counter to its initial value when a data pulse arrives within the expectation period.

18. A digital phase control circuit according to claim 16, comprising in further combination, means in the control circuit for canceling in the final value by a data pulse when the next arriving data pulse arrives in the expectation period while the content of the firstmentioned counter is lower than half the final value.

19. A digital phase control circuit according to claim 2, comprising in further combination, means operable during a synchronization sequence, after the arrival of a synchronization pulse to effect a counting in the final value counter with half the pulse train frequency until the next synchronization pulse arrives, and means for setting the first-mentioned counter. with such synchronization pulse, to the initial value.

20. A digital phase control circuit according to claim 1, for use in a magnetic tape store in which binary signals are recorded with the aid of the phase encoding recording method and in which on the read-out of a mag netic tape, the bit and auxiliary pulses produced by the bit and auxiliary flux changes are separated from one another, wherein means are provided for supplying counter pulse trains having a frequency which is so selected that at a given final value, the frequency of the LII tion with the signals at the output of the AND gate forming control pulses which are fused for the control instead of the data pulses.

Patent Citations
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US3631424 *Jul 22, 1969Dec 28, 1971Honeywell IncBinary data detecting apparatus responsive to the change in sign of the slope of a waveform
US3736582 *Mar 20, 1972May 29, 1973Leach CorpGalloping base line compensating circuit
US3737896 *Oct 27, 1971Jun 5, 1973Diablo Systems IncApparatus for recovery of recorded bit information on a magnetic recording medium
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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4158436 *Jul 25, 1977Jun 19, 1979Amp IncorporatedVariable timing circuit for card readers and the like
EP0129836A2 *Jun 19, 1984Jan 2, 1985Siemens AktiengesellschaftCircuit for the retrieval of the data contained in binary signals
EP0129836A3 *Jun 19, 1984Mar 12, 1986Siemens AktiengesellschaftCircuit for the retrieval of the data contained in binary signals
Classifications
U.S. Classification360/42, G9B/20.39, 360/51
International ClassificationH04L7/00, G11B20/14
Cooperative ClassificationG11B20/1419, H04L7/00
European ClassificationH04L7/00, G11B20/14A1D
Legal Events
DateCodeEventDescription
Oct 11, 1991ASAssignment
Owner name: SIEMENS NIXDORF INFORMATIONSSYSTEME AG, GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:SIEMENS AKTIENGESELLSCHAFT A GERMAN CORP.;REEL/FRAME:005869/0374
Effective date: 19910916