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Publication numberUS3898435 A
Publication typeGrant
Publication dateAug 5, 1975
Filing dateMar 11, 1974
Priority dateMar 11, 1974
Also published asCA1033824A1, DE2510314A1
Publication numberUS 3898435 A, US 3898435A, US-A-3898435, US3898435 A, US3898435A
InventorsMctamaney Louis S, Pritchard John N
Original AssigneeFmc Corp
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Memory device for an egg grading machine
US 3898435 A
Abstract
A memory device for use with an egg grading machine which includes a single lane conveyor carrying uniformly spaced eggs past a series of packing stations where the eggs are delivered directly into pocketed containers in accordance with predetermined weight grades. The memory keeps track of each egg on the conveyor and not only causes it to be discharged at the proper packing station but also causes it to be discharged at the correct position to sequentially fill the container at the packing station. The memory generally comprises solid state circuitry which includes a shift register carrying the grading information for the eggs on the conveyor at any particular time. In order to effectively process the information in the memory and condition the various packing stations the register is cycled a considerable number of times during the movement of the conveyor through a distance equal to the egg spacing thereon, and phasing pulses derived from the conveyor drive are used to periodically update the information in the register in accordance with the movement of the conveyor in order to maintain tracking control of the eggs as they move downstream to the packing stations.
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United States Patent [1 1 Pritchard et al. 1 Aug. 5, 1975 I MEMORY DEVICE FOR AN EGG GRADING MACHINE [57] ABSTRACT [75) Inventors: John N. Pritchard; Louis A memory device for use with an egg grading machine n y, both of Sim 1086, which includes a single lane conveyor carrying uni- Cfl ifformly spaced eggs past a series of packing stations [73] Assignce: FMC Corporation. San Jose, Calif. where, the ,eggs am delivere,d directly pockted containers in accordance with predetermined weight [22} Filed: Mar. 11. 1974 grades. The memory keeps track of each egg on the [21 APP!- Nu: 449,871 conveyor and not only causes it to be discharged at the proper packing station but also causes it to be discharged at the correct position to sequentially fill the l l 235/92 235/92 235/92 PK; container at the packing station. The memory gener- 5/ 2 209/74 0 ally comprises solid state circuitry which includes a [5i 1 Int. Cl. G06m 7/00 shift register arrying the grading information for the 1 i Field of 92 92 eggs on the conveyor at any particular time. In order 3; 74 to effectively process the information in the memory 198/39; 340/ 1 3 R and condition the various packing stations the register I is cycled a considerable number of times during the [561 References Cited movement of the conveyor through a distance equal to UNITED STATES PATENTS the egg spacing thereon, and phasing pulses derived 3.022.004 2/1962 Reading 235/92 PK from dfive are f F Periodically U" 114154 7/1964 Burkhardt 209/73 X date the information in the register in accordance with 3156900 11/1964 Mum",21 e 340 173 R the movement of the conveyor in order to maintain 335L145 11/1967 Mumma 177/50 X tracking control of the eggs as they move downstream Primary 1;'.\umim'r-- loseph M. Thcsz Jr. Attorney, Agent, or FirmC. E. Tripp; R. S. Kelly to the packing stations.

25 Claims, 3 Drawing Figures zo- CLOCK n PRIMARY TIMING PULSE MEMORY REGISTER POSITION COUNTER 22 ENCODER AND MULTIPLEXER CIRCUITS L A 2 INCH PULSES -1B|NARY TO DECIMAL 0EcoDER|-- Q 8 I I I I 1 5 I I -troALL I 5 PACK STATIONS I mcn PULSES] PACK #STATION PACK# STATION I I I0 -7 3 I SOL-5 SOL-3 SOL-l some \SOL-4 \soL-2\ DROP sotamellllil n,

EGG CARTON MEMORY DEVICE FOR AN EGG GRADING MACHINE BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention pertains to memory devices, and more particularly, it pertains to memory devices for use in an egg grading machine wherein eggs are assigned various grades (e.g., by weight), conveyed from the grading area to a packing area in the machine, and selectively discharged at various separate packing stations in accordance with their assigned grades.

2. Description of the Prior Art Automatic egg grading machines in commercial use today can generally be said to fall into one of two cate gories. First, these are those machines wherein eggs of diverse grades are carried past a series of individual discharge, or packing, stations and wherein the eggs are selectively discharged at the different stations in accordance with a grading measurement (e.g., a weight measurement) made at each discharge station. These machines do not require any memory means since the conditions for discharging an egg are determined at the point where the egg is actually discharged.

A second class of egg grading machines, however, determines the grades of all of the eggs in one part of the machine and thereafter conveys the eggs to the various separate packing stations wherein the eggs are selectively discharged in accordance with the predetermined grading information. This latter type of egg grading equipment requires some type of memory means (either mechanical, electromechanical, or electronic) which is operatively associated with the conveying mechanism that moves the eggs from the grading portion of the machine to the discharge stations. The efficient operation of the memory devices in these machines is, of course, essential to their acceptance for commercial use.

An egg grading machine of the latter type is disclosed in U.S. Pat. No. 2,895,274 to Harold J Mumma. In the machine disclosed in that patent, eggs are weighed at a plurality of weighing stations, deposited in individual egg carriers on a single file conveyor, and conveyed past a plurality of packing stations where the egg carriers are selectively activated to cause the eggs to be dropped off into underlying cartons or filler flats in accordance with the weight grades assigned thereto. This egg grading machine includes an electromechanical memory device which generally comprises an endless chain belt driven in timed relationship with the egg conveyor so that various sectors of the belt move past fixed sensing means in correspondence with the movement of the egg carriers past the various egg discharge stations. Information is placed on the belt, which includes a plurality of shiftable pins. by solenoid-actuated pin-setting mechanisms, and this mechanically recorded information is then conveyed in the orbital path of the belt to locations where sensing switches sense the actuated pins and provide discharge signals to actuate solenoids causing the selected egg carriers on the egg conveyor to open and discharge their eggs in the proper position to bereceived by the underlying egg cartons or filler flats.

Electromechanical memory devices. such as described, have been subject to some objections. In the first place. they are bulky and result in an increase in the required size of the egg grading machine which factor is oftentimes a determining factor in the decision of an egg packer to use or not use a particular egg grading machine. Secondly, the prior art electromechanical mechanisms are highly complex devices and the various components thereof are not only costly but are difficult and expensive to assemble. Finally, such mechanisms consume large amounts of power which factor is becoming of increasing importance in the light of the present and predicted future power shortages.

One obvious answer to the aforedescribed electromechanical memory devices is a solid state, low power memory device which utilizes a shift register, in place ofthe endless mechanical belts, and logic circuitry in place of the various solenoids and electromechanical relays. Such memories have been utilized in sorting machinery and have received an increasing acceptance by the various segments of the sorting industry. The conventional and obvious approach to adapting such solid state memory devices to the egg grading problem would be to shift the register in timed relationship with movement of a conveyor carrying the eggs to be sorted. Such an approach can, however, be costly where a number of different discharge locations for the eggs are required and where the register must be of a considerable length (i.e., with a large storage capacity) in order to provide for all of the various selective operations which are to be performed upon the eggs.

SUMMARY OF THE INVENTION The present invention is concerned with a solid state memory device for an egg grading machine of the type shown in the aforementioned prior US. Pat. No. 2,895,274 to Harold J Mumma. The memory deviceis used with an egg grading machine which includes an egg conveyor for conveying a series of eggs from an egg grading station to a plurality of egg discharge stations. The eggs are placed in linearly arranged egg carriers on the egg conveyor at the grading station and are assigned speciflc grades, e.g., weight grades. The graded eggs are then selectively discharged from the egg conveyor at the appropriate discharge station by means of mechanismswhich, acting through signals from the memory device, serve to cause the ejection of an egg from a particular egg carrier at a particular point in its travel path.

The circuitry of the memory device of the present invention basically comprises a serial shift register having a number of sectors or register positions. The information in the register is serially shifted from one sector to the adjacent sector and from the last sector thereof to the first sector thereof, and the register is cycled, i.e., the information therein is shifted entirely through the register, in a relatively short period of time. This cycling time of the register is entirely independent of the rate of movement of the egg conveyor, and it occurs in such a short period of time that information can be taken out of the register and placed in the register during any one cycle thereof without any appreciable movement of the eggs carried on the egg conveyor. Thus, all decisions to be made with regard to the proper discharge of eggs at any given time can be made without regard to the time required to sequentially monitor the register. A counting means is associated with the clock for serially shifting the register in order to correlate the information in the register at any given time with the position of the eggs on the conveyor. andphasing pulses are derived from the egg conveyor representing the movement of the conveyor through a short distance of predetermined length in order to update the information in the counting means so that the movement of the eggs on the conveyor is tracked as they move through said short distances of predetermined length. In the preferred embodiment of the invention said short distances of predetermined length represent the centerto-ccnter spacing between adjacent egg carriers on the conveyor.

By the foregoing circuitry a rather simplified memory device can be utilized with the egg grading machine of the present invention which does not require costly assembling and wiring of a shift register to permit continuous readouts at different register positions in a manner similar to that of the prior art electromechanical memories as described in the aforementioned prior U.S. Pat. No. 2.895.274. Nevertheless. all of the necessary information is continually processed during short increments of movement of the egg conveyor so that the eggs can be selectively discharged at precisely the right locations to cause them to be received. for example. in pockets in the conventional egg cartons or filler flats.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagrammatic illustration of the egg grading machine of the present invention showing, in block diagram form, the various functions performed by the egg memory device.

FIG. 2 is a schematic diagram of the circuitry of the egg memory device of the present invention.

FIG. 3 is a schematic diagram of the circuitry of one of the several packing stations in the egg grading machine of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now more particularly to the drawings, FIG. 1 shows in diagrammatic form an egg grading machine including, particularly, the circuitry forming the memory device of the present invention. All of the mechanical details of this egg grading machine are disclosed in the aforementioned prior U.S. Pat. No. 2,895,274 to Harold J Mumma. The disclosure of this patent is specifically incorporated by reference herein for a further detailed description of all of the various mechanical elements of the egg grading machine and their method of operation.

The subject egg grading machine, as disclosed in U.S. Pat. No. 2,895,274, generally comprises a single lane egg conveyor (FIG. 1) which is arranged to be continuously driven at a uniform speed and to receive individual eggs E directly from a plurality of scales 16 upon which the eggs are weighed. The scales are positioned directly adjacent to the conveyor at spaced positions therealong so that the eggs can be transferred to the conveyor immediately after they are weighed. These scales, which are designated as Scale No. IScale No. 6 in the diagrammatic illustration of FIG. I, are each provided with means to close one of a plurality of switches which permits the transmission ofan electrical signal therethrough representative of the weight of the egg being weighed. During the weighing of the eggs on each of the scales, a scale switch timer 18, which comprises a conventional cam switch operating mechanism mechanically connected to the drive mechanism for the conveyor 10, is utilized to provide a short timing pulse at that time when the weight of the eggs can be read from the scales. This timing pulse is transmitted by means of a line 17 to a primary memory unit 20. The signals indicating the designated weight grades from each of'these scales are transmitted to encoder and multiplexer circuits 22 wherein they are coded and sequentially transferred into the primary memory unit in a predetermined sequence and at predetermined times as will be explained in greater detail hereinafter.

Once the eggs have been weighed and the correct weight signals transmitted out of the scale units 16, the eggs are discharged from the scales into individual egg carriers. or buckets, 12 on the underlying egg conveyor 10. The conveyor will be seen to comprise an endless chain formed of a continuous series of interconnected egg carriers. These carriers are each of the clam shell type so that they may receive eggs dropped vertically from overhead. Each egg carrier includes two hinged members supporting the egg which members are arranged to be selectively pivoted open by a solenoidactuated lever arm to drop an egg at the correct discharge position.

It should be noted that in the machine described in the aforementioned U.S. Pat. No. 2,895,273, the six scales therein shown deposit the eggs in every seventh bucket, or egg carrier. along the egg conveyor 10. In the diagrammatic illustration of FIG. I, the scales are shown as transferring the eggs into six consecutive buckets of the egg conveyor. While this distinction between the structure shown in U.S. Pat. No. 2,895.274 and the presently described structure requires a change in the order in which the eggs are transferred into the egg conveyor it makes no difference with regard to the construction of and operation of the memory device of the present invention as will be made more apparent from the following description.

' Once the eggs are received on the conveyor I0 they are carried downstream past a series of discharge or pack stations 23. In the illustrated embodiment of the invention there are ten separate egg pack stations with only the furthest downstream pack station (pack station 10) being shown in full in FIG. 1. Each of the pack stations operate in the same manner. The memory device of the present invention will cause one of six drop solenoids (denoted by the designations SOL-1 through SOL-6 to be selectively activated to extend an actuating lever arm which forces the hinged members of a selected egg carrier 12 to open and drop the egg supported thereby into the proper pocket in an underlying egg carton C. In the diagrammatic illustration of FIG. 1, it will be seen that the solenoid SOL-6 has just been energized to cause the aligned egg bucket 12 on the conveyor 10 to discharge an egg into the last pocket of the underlying egg carton C to complete the filling of a row of eggs in the carton. It will be noted that each of the pact stations 23 continuously receive information as eggs are conveyed therepast'by the conveyor so that eggs which are to be discharged at a particular pack station will, through the memory device of the present invention, cause a signal to be transmitted to the pack station to activate the proper solenoid to drop the egg.

It will further be noted that each pack station 23 must not only operate to cause the discharge of the correct eggs but it must also operate to drop each egg in the correct position with respect to the fixed location ofthe pack station. This is because the eggs are to be discharged from the egg conveyor I0 directly into an underlying egg carton C or egg filler flat. As is conventional, both the egg cartons and egg filler flats have rows of six eggs each. Thus, each packing station must provide means for dropping eggs into any one of six longitudinally spaced positions. This requires that there be six solenoid actuated lever arms which are spaced longitudinally along the conveyor. It will be noted, however, that the spacing of the solenoids SOL-1 to SOL-6 is less than the spacing of the egg buckets 12 on the conveyor. This is because the spacing of the eggs in the egg cartons, or filler flats, is less than it is on the conveyor since the conveyor necessarily includes conveying support mechanisms between each pair of egg buckets. In the egg grading machine of the present invention, the spacing of the egg buckets is at 2 /2 inch intervals while the spacing of the eggs in the containers (and hence the spacing of the solenoid-actuated lever arms) is at 1 /3 intervals. Thus, signals are provided by the memory device at the pack station not only to cause the correct eggs to be discharged but also to cause each egg to be discharged in the proper position so that it will fall directly into an empty pocket of the underlying egg container.

As will also be apparent from FIG. 1, the egg machine is operated so that eggs are dropped into the underlying egg containers in a sequence starting with the furthest downstream egg pocket and moving upstream. That is to say, the drop solenoids are actuated in sequence starting with solenoid SOL-l and moving upstream to solenoid SOL-6 when the sixth egg is discharged. Once a complete row of an egg carton or egg filler flat has been filled, a special signal is transmitted to cause a carton conveyor (not shown) to shift the egg carton C laterally with respect to the movement of the egg conveyor 10 to position a new row beneath the buckets 12 of the egg conveyor. If the entire egg carton is filled with eggs, this carton is moved away from the conveyor, and an empty carton or filler flat is moved into position to receive eggs.

It might be mentioned, before proceeding with the description of the novel egg memory device of the present invention, that the machine disclosed in the aforementioned U.S. Pat. No. 2,895,274 included means whereby eggs were graded according to the quality thereof as well as according to their weight with information with regard to both of such grading characteristics being transferred to the electromechanical memory of the prior art apparatus so that final sorting at the pack stations was made in accordance with both the quality and the weight of the eggs. The present invention will be described only with respect to the sorting ofthe eggs with regard to their weights since the principles and circuitry involved in sorting the eggs with regard to any other characteristic, or to any combination of characteristics, remains essentially the same. That is to say, further grading separations can be made with the memory of the present invention merely by increasing the inputs to the memory and, if necessary, the number of discharge or pack stations.

Other operations. such as blood spot detecting and cracked shell detecting, which have been heretofore used in automatic egg grading machines, can also be provided with the egg grading machine of the present invention. For example, in addition to the six scales 16, an egg blood spot detector and a cracked shell detector could be positioned downstream of the scales to inspect all of the eggs on the conveyor 10 and transmit 'a special signal to the memory if a defective egg were detected so as to cause such defective eggs to all be discharged at a special pack station. The processing of such signals from an egg blood spot detector or cracked shell detector would be handled in the same manner as those signals from the scales l6.

Returning now to the description of the memory device, it will be recalled that it was stated that information with regard to the weights of the eggs delivered to the egg conveyor 10 was transmitted to the primary memory unit20 (FIG. I) under the control of timing pulses on the line 17. This primary memory unit basically comprises the conventional serial shift register within which information is stored and serially shifted by means ofa free running oscillator, or clock, 24. One of the primary features of the present invention is the fact that the transfer of information within the primary memory unit 20 is entirely independent of the movement of the eggs E on the egg conveyor. This is in direct contrast to the operation of the electromechanical memory in the aforementioned prior U.S. Pat. No. 2,895,274 wherein a memory belt which stored all grading information was moved in direct timed relationship with the movement of eggs on the conveyor. In the memory device of the present invention, the memory register is shifted at a much faster rate than the rate of transfer of the eggs through any appreciable distance, and these two rates are not at all related. That is to say, the speed of the conveyor 10 can be increased or decreased with the frequency of the clock 24 remaining constant without having any effect upon the operation of the machine. Conversely, an increase or decrease in the frequency of the clock 24 will have no effect upon the transfer of the eggs if the egg conveyor speed remains constant.

As stated, therefore, information is arranged to be transferred within the memory at a much faster rate than any incremental rate of movement of the egg conveyor 10. In fact, information in the memory register is completely cycled therethrough, i.e., information in the first position in the register is shifted position by position through the entire register and then back to the first position thereof, at a cycling rate which is considerably faster than the movement of the conveyor through a linear distance equal to the center-to-center spacing between two adjacent egg carriers 12. Consequently, a complete cycling of information in the memory is obtained in a time which is short enough so that the conveyor, in effect, stands still" during such information transfer time. In this manner, the entire contents of the memory at any given time can be reviewed and logic decisions can be made with regard to all of the information in the memory without the simultaneous occurrence of any appreciable movement in the egg conveyor.

In order then that the memory can still be used to track the eggs on the conveyor, it is an important feature of the present invention that a register position counter 26 be operated in conjunction with the memory. This counter 26 is driven by the clock 24 which shifts the memory register and is arranged to sequentially and repetitively count up to a number exactly equivalent to the number of sectors or positions in the primary memory register. Phase pulses are produced by circuitry 28 at predetermined time intervals, by means of a mechanical connection with the egg conveyor 10, so that these phase pulses represent certain fixed increments of movement. of the conveyorv Certain of these phase pulses are transmitted to the register position counter 26 at a pulserate equivalent to a 2 /2 inch movement of the conveyorlO, i.e., a phase pulse is transmitted each time that the conveyor moves through a distance equal to the center-tocenter spacing between a pair of adjacent egg buckets 12. Between any consecutive pair of such phase pulses, hereinafter denoted as 2% inch phase pulses, the numbers designated by the output lines of the counter 26 will indicate that the memory output is presenting information with regard to a particular egg bucket along the length of the conveyor. The next 2%. inch phase pulse increases the count in the counter by one unit and, thus, has the effect of shifting all the information in the memory register by one egg bucket length along the conveyor. Information is then extracted from and placed into the register only when the counter indicates that the register is in a position to take or transmit information with regard to the egg bucket at a particular egg input or discharge location. This procedure and the specific circuitry for accomplishing it will be explained in greater detail hereinafter particularly with regard to the more detailed depiction of the circuitry of the present invention given in 'FIG. 2.

Having reference again to FIG. I, it will be noted that information from the primary memory unit is transmitted through a binary to decimal decoder and then is transmitted to the various pack stations 23. During the reading of the primary memory unit, between each pair of consecutive phase pulses, information is transmitted through the decoder 30 to the various pack stations in accordance with the numbers indicated by the output lines of the register position counter 26. Each pack station has a particular number assigned thereto which number represents the number of egg buckets between that pack station and Scale No. l, i.e., the furthest upstream grade input station. Furthermore, in addition to the 2% inch phase pulses there are also produced a series of /5 inch phase pulses at a rate equivalent to the incremental movement of the conveyor 10 through distances of one-eighth of an inch. These so-called 7 8 inch phase pulses are transmitted to the pack stations where they are used to cause variable delay in the time of discharge of an egg relative to the timing of the 2% inch phase pulses so that the egg can be sequentially discharged into the underlying egg cartons C in positions to fill the pockets in the cartons.

FIG. 2 shows, in detail, the circuitry of the major portion of the memory device of the present invention. As is illustrated, each of the scales 16 is designed to provide an output signal upon one of eight separate lines to the encoder and multiplexer circuits 22. The circuitry for providing this weight reference signal is shown in detail only with respect to Scale No. 1, it being understood that the circuitry of Scale No. 2, Scale No. 3, Scale No. 4, Scale No. 5 and Scale No, 6 is similar. In the manner set forth in the aforementioned prior US. Pat. No. 2,895,274 one of the eight grading output lines associated with each scale will be closed by a switch 31 indicating the proper weight grade for the egg being weighed on the scale at that time. These different weight grades have been given the designations WT-A through WT-H in the embodiment of the invention shown in FIG. 2.

The encoder and multiplexer circuits 22 will be seen to comprise six separate decimal-to-binary encoders 32 each being arranged to receive the eight-input decimal weight signal from an associated scale I6 and to code such signal intoa fourbit binary code. Only the encoders 32 for Scale No. l and Scale No. 6 are shown in FIG. 2, it being understood that similar encoders are present to transfer information from Scale No. 2- Scale No. 5. Each of the individual decimal-to-binary encoders 32 transmit their coded data to the multiplexer 34. This conventional digital logic unit comprises a six BCD input multiplexer with a single BCD output. Switching within the multiplexer is controlled by the select code lines 35 which transmit a coded binary signal from a decimal-to-BCD encoder 36. This latter encoder is enabled. in a manner to be explained further hereinafter. to selectively activate the multiplexer to accept the input from one of the scales 16 when a particular register position in the memory unit 20 is in position to accept information.

The output from multiplexer 34 is transmitted to a second multiplexer 42 which comprises a portion of the primary memory unit 20. Multiplexer 42 is a conven tional quad two-input multiplexer which is wired to accept either the four input line weight grade signal from multiplexer 34 or the four input line signal from the last register position, or sector, of the primary memory register 44. As shown in FIG. 2 the memory register 44 comprises a conventional storage register having two hundred register positions, or sectors, each ofa four bit data width. Thus, all of the pertinent weight grade information (i.e., whether an egg is weight A, weight B,

- etc.) as well as further grading information can be handled within the four bit data width of this register. The register 44 is serially shifted by means of the two-phase clock 24 in a conventional manner with information being transferred serially from one register position to the adjacent register position upon the reception of each clock pulse. As noted hereinbefore, the information in the last sector of the register is normally transferred through the multiplexer 42 into the first position of the memory register upon the reception of each clock pulse; however, when a select line 45 is activated the multiplexer 42 will block the transfer of information from the last register position and will allow the binary coded data from the multiplexer 34 to be passed into the memory register. The select line45 is activated by means of a signal from an AND gate 46 which, in turn, is enabled by a signal on the previously mentioned line 17 emanating from the scale switch timer 18. This signal, which is provided when the eggs are being weighed, passes through an AND gate 38 where it is anded with an output decode enable signal. This latter signal, which is produced in a manner to be described hereinafter, permits weight grade information to be transferred into the register 44 on only one register cycle, namely the first register cycle, after the generation ofa 2% inch phase pulse. For the remaining approximately 79 cycles of the memory register prior to the generation of the subsequent 29% inch phase pulse. there will be no output decode enable signal to allow information to be transferred from the multiplexer 34, and hence, all grading information will continuously cycle through the register. During this time, while the conveyor is moving through virtually the entire 2% inches of travel between successive egg positions, no information can be transferred into or read out of the register. As explained previously the length of the output decode enable signal is deliberately set for a short period of time as compared to the length of time between successive 2 /2 inch phase pulses so that the conveyor will move through only an extremely small, and therefore negligible, distance during the time that information is placed into and read out of the register. In this manner, differences in time between the reading of different register positions will have no effect upon the operation of the system. This is important since the eggs must be dropped off of the conveyor 10 at precisely the right positionsin order to be received in the confining pockets of the underlying egg cartons C.

Multiplexer 42 also is provided with means to apply a disabling signal which will cause all of the lines out of the multiplexer to go to zero on the subsequent shift pulse. The presence of four zeros in any register position will therefore indicate the absence of an egg in the egg carrier 12 which corresponds to that register position, and the disabling signal will, in effect, erase the information being transferred into the first position of the memory register from the last position thereof. This disabling signal is provided from one of the various pack stations 23 after an egg has been discharged so that the egg grading information will not be carried through the register to effect the operation at any downstream pack station.

One of the key elements in the circuitry of the present invention is the register position counter 26 which counts continuously and repetitively from to I99 and which is adapted to be driven by the clock pulses from clock 24 which also serve to shift the information in the register. This counter 26 can be formed by conventional logic block elements including the serially connected combination of two decimal-decade counters and a flip-flop. The counter will therefore have three separate groups of outputs with one (and only one) output line in each group being energized at any one time. These groups include (l) outputs on ten lines indicating unit counts of 0 through 9, (2) outputs on ten additional lines indicating decade counts of 00 to 90, and (3) two outputs on a hundreds line indicating counts of 000 to 100. It will be noted that the memory register has 200 positions, i.e., exactly the same number of positions as the maximum number to be counted by the register position counter 26. Thus, a selection of one line from each of the three groups of lines out of the register position counter provides a composite signal indicating that a particular register position in the memory register is being counted. As will be apparent from FIG. 2, the counter is activated by a shift pulse signal from the clock 24 acting through an OR gate 47.

In accordance with the described embodiment of the present invention, the egg bucket I2 which is aligned to receive an egg from the furthest upstream scale (Scale No. I immediately after it has been weighed is assigned the first register position (register position 0) at the time that the grading information for that egg is transferred into the memory register 44. Thus, the egg bucket which receives an egg from scale No. 2 at the same time. and which is spaced 2% inches on down the conveyor, will be assigned the second register position (register position I) when the information with regard to that egg is transferred into the memory register. In a similar manner. weight grade information for the eggs transferred from scales 3, 4, and 6 will be transferred into register positions 2, 3, 4 and 5 on the next successive clock pulses from clock 24. After the delivery of six eggs to the conveyor and while the conveyor is moving through 2% inches of travel, these register positions will remain constant (as indicated by the output of counter 26) even though the memory register is cycled many times. That is to say, the register position counter will indicate a 0 on its output lines (0, 00 and 000) when the information from Scale No. I is transferred through the multiplexers 34 and 42 into the memory register. Similarly, the register position counter will indicate a l on its output lines (I. 00. 000) when the grading information from Scale No. 2 is transferred through the multiplexers 34 and 42 into the memory register, As the counter then continues to count up to I99 and returns to the first count or zero" count, the information will regard to the egg transferred from Scale No. I will be transmitted from the last sector in the memory register to the first sector thereof. In the same manner that information was transmitted into the register, information can be read out of the register from the last sector thereof when the counter 26 provides count output signals which represent the egg bucket spacing of the various discharge or pack stations 23 from Scale No. 1. Thus, at any time during the subsequent memory register cycles prior to the generation of a new 2 /2 inch phase pulse. the output from the register position counter at any time will indicate information with regard to an egg in an egg busket spaced by some particular egg bucket length increment from the furthest upstream scale. i.e.. Scale No. I. Since the memory register has 200 register positions. or sectors. the apparatus obviously is capable of receiving eggs and discharging the eggs over a conveyor length equivalent to 200 bucket lengths. i.e.. 200 X 2V2 inches.

The manner in which the register position counter enables the multiplexer 42 to permit the transfer of weight grading informationinto the memory register 44 is shown in FIG. 2. AND gates 50, 52 and 54 are arranged to provide output signals upon counts 0", I and 5, respectively, from the counter. Similar AND gates (although not shown) are used to provide output signals for the counts 2, 3", and 4 out of the counter. Upon an output signal from one of the gates 50, 52 and 54, a signal is transmitted through an OR gate 48 to enable the AND gate 46, and a signal is simultaneously transmitted to the decimal-to-BCD encoder 36 in order to provide the proper select code on the lines 35 controlling the transfer of information through the multiplexer 34.

Thus far, only the transfer of information into the register with regard to the weight grades of the eggs on the egg conveyor has been explained in detail. It will also be recognized, of course, that the information with regard to the eggs on the conveyor must be monitored each time that the egg conveyor 10 moves through two and a half inches of travel to enable decisions to be made at each of the various pack stations 23 to decide whether or not an egg should be dropped at these stations. Although the specific circuitry of the pack station control logic will be described in detail hereinafter with respect to the circuitry shown in FIG. 3, it is pointed out that each of the various pack stations will have assigned thereto a specific read-out number which number will represent the spacing in terms of egg bucket lengths (i.e., 2% inch increments) from the furthest upstream egg input point (Scale No. I). During the time that the output decode enable signal is provided, not only will the weight grade information be transferred into the memory register through multiplexer 42 but also the information will be read out of the memory register through the binary-to-decimal decoder 30 and transmitted to the various pack station logic circuits to allow the right eggs to be dropped at the right pack stations. As shown in FIG. 2, the output decode enable signal therefore also enables the binaryto-decimal decoder 30.

The output decode enable signal is produced by means ofa pair of AND gates 56 and 58, and AND gate 59, and a conventional R-S flip-flop 60. Immediately after the reception of a 2% inch phase pulse signal, on a line 57, the AND gate 59 will be enabled and a signal will be transmitted from this gate upon the subsequent output of an indicated count 199 from the counter 26it being recognized that this count represents the fact that the last sector in the register is then in position to transfer information to the binary-to-decimal decoder 30. This signal from gate 59 sets the flip-flop 60 and initiates the output decode enable signal. The output decode enable signal therefore sets up the register so that upon the subsequent shift pulse from clock 24, scale grading information, if it is present, can be tramsitted into the memory register. The register position counter then continues to count from through to permit the register to receive any weight grading information which may be transmitted at that time. From register position counts 6 through 197, signals are provided at appropriate times to the pack station logic circuits in order to cause the right eggs to be subsequently dropped at the pack stations -if, of course, there are eggs in position to be dropped. Upon the indicated count of 198 out of the register position counter 26, AND gate 58 will provide an output signal to reset the flip-flop 60 and terminate the output decode enable signal. In this manner, the transfer of information into and out of the memory register is prevented for the remaining approximately 79 cycles of the memory register until the reception of the next 2% inch phase pulse on line 57.

It is important, of course, that the position of the eggs on the conveyor be continuously tracked as they are moved therealong. In order to accomplish this function, the 2% inch phase pulses on line 57 enable an AND gate 61. A pulse produced on the second phase of the clock 24 immediately thereafter provides an output signal from AND gate 61 which is transmitted through the OR gate 47 so that an additional count is placed in thee register position counter 26. This count signal will never overlap with the count signal corresponding to the shift pulses in the memory register since such shift pulses are provided only upon the first phase of the clock. Hence. an extra count pulse has been transmitted to the register position counter and all counts out of the counter have been, in effect, shifted with respect to the information in the register by one register position. This means that binary coded information in the register which was previously transferred into the register at register position 0 (to indicate the grade of an egg transferred to the first egg bucket from Scale NO. 1) will now indicate the characteristics of the egg in the second egg bucket on the conveyor. Each time that an additional 2% inch phase pulse is generated the weight grade information will be associated with the egg transferred by one bucket length down the conveyor. Thus, if there is a discharge position, for example, some 61 egg bucket lengths (i.e.. 6] X 2% inches) from Scale No. 1, then the weight grade information which will cause a discharge of an egg at that pack station will be transmitted to the logic circuitry for that pack station when the number 61" is indicated by the counter 26 exactly 6] X 2% inches of conveyor travel after that weight grade information was placed in the memory. In this manner, the memory tracks all of the eggs even though the memory register itself is shifted at a rate which is considerably faster than the incremental movement of the conveyor and wholly independent thereof.

All of the pack stations 23 are provided with the same logic circuitry for causing the selective discharge of eggs in accordance with the predetermined grading information which is placed in the primary memory unit 20. FIG. 3 shows the specific circuitry for pack station 10, i.e., the last pack station on the conveyor, which receives a signal through an AND gate when the number l 61 is indicated by the counter 26. Thus, pack station 10 is located 161 egg bucket lengths (I61 X 2% inches) from Scale No. 1. As shown in FIG. 3 the AND gate 70 provides an enabling signal when the lines from the 1", 60" and I00 outputs of the counter are activated. This will, in a manner explained previously, signal that weight grading information is at the register output for the egg which is at that time at pack station 10. The circuitry of the pack station also includes the eight inputs from the binary-to-decimaldecoder 30 which indicate the correct weight grade of the egg at the output, i.e., the last sector of the memory register 44. These will, of course, only be activated during the time of the output decode enable signal which is to say for only one register cycle between each consecutive pair of 2% inch phase pulses. Each pack station also has associated therewith a selector switch 74 which can be manually rotated to select the particular .weight grade of egg to be packed at that station. As shown in FIG. 3, the selector switch 74 has been set to pack weight grade D at pack station 10. The selector switch transmits the signal from the binary to decimal decoder 30 to an AND gate 72. Thus, when both the correct weight grade signal and the correct signal from the AND gate 70 are activated there is positive indication that an egg of weight grade D is at pack station 10 and ready to be packed. At this time AND gate 72 gencrates an output signal to start the sequence of events in the pack station logic circuitry which will ultimately result in the discharge of an egg from the conveyor.

. Ifall eggs of weight grade D are to be packed at pack station 10, then the signal from AND gate 72 could be transmitted directly to an R-S flip-flop 78 to enable AND gate 80 the output of which is connected to one end of a 16 bit shift register 82. This secondary shift register is utilized to create a variable time delay as the signal is shifted in the register in order to enable the egg to be dropped at precisely the right position to be received in the correct pocket in the underlying egg carton C. However, it is frequently necessary in egg grading machine operations that certain weight grades be packed at more than one station since there may be more eggs of one or two weight grades than of any other. Hence. the circuitry of the present invention includes the combination of a toggle flip-flop 75 and an AND gate 76 which operate to permit either zero percent, 50 percent or I00 per cent of the selected weight grade of eggs to be packed at any pack station. In order to effect this function, the output from AND gate 72 (which indicates that an egg of the correct weight grade is'at the pack station) provides the clock input to the toggle flip-flop 75. lf neither of the clear or preset inputs to the flip-flop are activated, the output of the flip-flop will go high on every other clock input pulse. This output of the flip-flop 75 is anded" with the output of the AND gate 72 through and the AND gate 76. Thus, it will be recognized that AND gate 76 will pass only fifty percent of the signals out of the AND gate 72 meaning that only fifty percent of the correct weight grade of eggs passing pack station will be packed. Another pack station located downstream from pack station 10 (not shown in the present embodiment of the invention) can then be used to pack the remaining 50 percent of the eggs. If it is desired to pack 100 percent of the eggs at any pack station, the preset input to the toggle flip-flop 75 is set to force the 0 output of the flip-flop high whereby AND gate 76 will provide an output each time that an output signal is transmitted through AND gate 72. Finally, if it is desired to block the discharge of eggs at any pack station, the clear input to the toggle flip-flop 75 is activated to force the Q output low wherein no signal can ever be transmitted out of the AND gate 76 to set the flip-flop 78.

Each time that the flip-flop 78 is set to start the sequence of events which will result in the dropping of an egg at a particular pack station, a line from the output of AND gate 76 provides a signal to the disabling input to the multiplexer 42 in the primary memory unit to cause the multiplexer to transfer four zeros into the memory register 44 and, in effect, erase the weight grade information for the egg which is about to be dropped at the pack station.

Flip-flop 78 enables an AND gate 80 which then waits for a signal, denoted as the adjustable position signal", out of a divider circuit 84. This divider circuit receives phasing pulses designated as /8 inch phase pulses which, in a manner similar to the 2% inch phase pulses, are derived from the egg conveyor drives means. These pulses are synchronized with the 2% inch phase pulses but they occur at a higher frequency, i.e., at intervals equivalent to the movement of the conveyor through but one-eighth inch of travel. This distance was chosen as a minimum distance within which tolerances can be made in the dropping of eggs from the conveyor. That is to say. the eggs can be dropped from the conveyor within tolerances of up to about one-eighth of an inch without adversely affecting the egg packing operation. The /-1 inch phase pulse frequency is therefore twenty times greater than the frequency of the 2% inch phase pulses.

Since the position of the egg conveyor 10 when the egg scale information is read will not necessarily coincide with the correct egg conveyor position to allow an egg to be dropped into an egg container pocket, a delay of a predetermined fixed time must be provided between the time that the egg grade information is transferred to the pack station logic circuitry and the time that the egg is actually dropped. This fixed time delay corresponds to the time between the reading of scale information and the time when the egg bucket associated with a particular station is in position to drop an egg into the furthest upstream pocket of the underlying egg container, that is to say, the position of the egg bucket when solenoid SOL-6 is activated as shown in FIG. 1. This fixed delay is provided by the divider circuitry 84 which transmits an output pulse after a predetermined (and adjustable) number of 541 inch phase pulses have been received. For example, if solenoid SOL-6 in pack station 10 is to be activated at a time equivalent to one inch of conveyor travel from the position where the scale readings are taken, then the di-. vider circuitry 84 would divide the Vs inch phase pulses by eight in order to provide an output signal on the adjustable position signal line after eight phase pulses had been received. This signal is anded with the signal from the flip-flop 78 in the AND gate 80 which causes a positive input to the first bit in the sixteen bit shift register 82. The divider circuit 84 may also be adjusted to create a different delay after the egg grading machine has been in operation for a long period of time in order to compensate for any accumulated stretch in the egg conveyor 10.

The 16 bit shift register is used to sequence the dropping of eggs so that six eggs can be dropped into the underlying egg carton C in the proper order. The shift pulses for the shift register are derived from a divideby-five logic circuit 86 which also receives the aforedescribed inch phase pulses. Thus, a pulse output from the divider circuitry 86 is provided for every fiveeighths inches of conveyor travel. When information is shifted into the register 82, an erase signal from the first bit thereof is provided to reset the flip-flop 78 in order to prevent spurious discharge signals from being transmitted through the register. Then, as will be noted from FIG. 3, output signals are provided after each three successive serial shifts in the shift register, and these output signals are transmitted through AND gates 88 and amplifiers 90 to sequentially activate the solenoids SOL-1 through-SOL-6. It will be recognized that these output signals will be provided after each l /a inches of travel of the egg conveyor which represents the spacing between the eggs in the underlying egg carton C.

The AND gates 88 are enabled by signals from a drop solenoid counter 94 which counts from zero to five and then recycles. Counter inputs are provided through an OR gate 92 from the outputs of all of the AND gates 88. The counter 94 is originally set so that the first count indicated thereby (the 0" count) will be transmitted to activate the AND gate 88 associated with the first egg to be dropped at pack station 10. It will be noted that this AND gate is at the very end of the shift register and thus information must be shifted entirely through the register to activate this AND gate which will, in turn, activate solenoid SOL-1 to cause the egg to be dropped at the furthest downstream position into the last pocket of the underlying egg carton C. The output signal from this AND gate 88 then also transmitted through the OR gate 92 to increase the count in the counter 94 by one so that when the next egg to be dropped at pack station 10 causes a signal to be shifted into the shift register 82, the AND gate 88 connected with the thirteenth bit of the shift register will be enabled to activate solenoid SOL-2 and cause an egg to be dropped lVB inches upstream from the first egg to thereby fill the second pocket in the underlying egg carton. In this manner, each of the egg pockets in the egg carton is filled as the counter 94 counts up to five and ultimately activates the AND gate 88 connected to the first bit of the sixteen bit shift register 82. This is the signal which, as previously pointed out, activates solenoid SOL-6 to drop the final egg in a row in the egg carton. At this time. a special signal out of this AND gate 88 is transmitted through a time delay circuit 96 and an amplifier 98 to activate an index solenoid SOL-7 whcih either causes the underlying egg carton C to be shifted laterally to allow a new row of eggs to be packed or causes the carton (if filled) to move away from the conveyor to be replaced by a new carton. The structure and operation of the apparatus for accomplishing these functions are described in detail in the aforementioned prior US. Pat. No. 2,895,274, such details not being at all critical to an understanding of the present invention.

With the egg grading machine of the present invention, it can be seen that a solid state memory device is provided which will accurately and efficiently cause eggs to be discharged from an egg conveyor at various discharge stations in accordance with predetermined egg grading information. The memory, as is common in devices employing solid state circuitry, utilizes a conventional serial shift register to store the egg grading information. However, it is not necessary that such shift register provided outputs at each sector or register position thereof. Instead, only one position in the register need be monitored, and a counting means is utilized to track the various eggs on the egg conveyor as they move from the furthest upstream egg input station to the furthest downstream egg discharge station. This arrangement permits a simplified and less expensive register to be used and also permits the register to be shifted at a frequency which is entirely independent of movement of the egg conveyor.

Although the best mode contemplated for carrying out the present invention has been herein shown and described, it will be apparent that modification and variation may be made without departing from what is regarded to be the subject matter of the invention.

What is claimed is:'

l. A memory device particularly adapted for use in an egg grading machine which includes an egg conveyor for receiving eggs from a plurality of spaced eggs grading stations and for carrying said eggs to a plurality of spaced discharge stations where said eggs are selectively discharged in accordance with the grades assigned thereto at said grading stations, said egg conveyor comprising a plurality of linearly arranged and uniformly spaced egg carriers adapted to be moved from said grading stations to said discharge stations, said memory device comprising:

a storage register comprised ofa plurality of information carrying sectors arranged in serial fashion with the number of sectors in said register being at least as great as the number of egg carriers from the furthest upstream grading station to the furthest downstream discharge station;

means providing a continuous series of shift pulses at a first rate for serially shifting information through said register from each sector thereof to an adjacent sector and from the last sector thereof to the first sector thereof;

means for providing phasing pulses at a second rate corresponding to the movement of the conveyor through a linear distance equal to the center-tocenter spacing between a pair of adjacent egg carriers, said first rate being faster than said second rate by a factor whereby information in any sector in said register is transferred sequentially through all of the sectors in said register a considerable number of times between each pair of consecutive phasing pulses;

means for transferring information from each of said grading stations into one of the sectors in said register in accordance with the grades of the eggs reeeived by said conveyor;

means for transferring informationfrom one of the sectors of said register to said discharge stations to cause the selective discharge of said eggs in accor- .dance with said information; counting means connected to said means for shifting said register for correlating the information in said register at any given time with the position of the eggs on the conveyor; and means connecting said phasing pulse providing means with said counting means so that the count in said counting means is increased by one each time that a phasing pulse is produced whereby the movement of the eggs on the conveyor is tracked.

2. A memory device according to claim 1 wherein said counting means is arranged to repeatedly and continuously count said shift pulses up to a number directly corresponding to the number of sectors in said storage register, means for providing output signals from said counting means at certain predetermined counts, said last name being connected to said means for transferring information to said register in order to effect the transfer of said information at times when said counting means indicates certain predetermined counts.

3. A memory device according to claim 2 including logic circuit means connected to said output signals from said counting means, said logic circuit means being arranged to provide an enabling signal to permit the transfer of information into and out of said register only during one complete cycle thereof during the interval between two consecutive phasing pulses, the duration of said enabling signal being very short as compared with said interval between two consecutive phasing pulses.

4. A memory device according to claim 3 wherein said enabling signal is both initiated and stopped when said counting means indicates a number greater than the number of egg carriers from the furthest upstream grading station to the furthest downstream discharge station.

5. A memory device according to claim 3 wherein said output signals from said counting means are connected to each of said discharge stations, and means at each discharge station for comparing information representative of a predetermined grade of egg with the information transferred out of said register at a time corresponding to an indicated count in said counting means associated with that discharge station whereby eggs of said predetermined grade will be discharged at said discharge station when they reach the proper discharging position on said egg conveyor.

6, A memory device according to claim 5 including manual switching means for changing said predetermined gradc information at each of said discharge stations.

7. A memory device according to claim 5 including means for causing only a predetermined percentage of said predetermined grade of egg to be discharged at any one discharge station.

8. A memory device according to claim 5 including means for creating a variable delay in the time between thetransfer of egg grade information to a discharge station and the discharge of an egg at that station so that 17 eggs will be discharged at different positions at said station to fill a row of pockets in an egg container.

9. A memory device according to claim 8 wherein said means for creating a variable delay comprises a secondary serial shift register associated with each discharge station, means operatively associated with said phasing pulse providing means for serially shifting information in said secondary serial shift register, means for monitoring the output of certain cells in said secondary serial shift register, and secondary counter means for comparing a count dependent upon the number of eggs discharged at a discharge station with the secondary serial shift register output monitoring means to cause said eggs to be discharged consecutively at linearly spaced positions.

10. A memory device according to claim 8 including means for adjusting said variable delay time.

11. In an egg grading machine which includes an egg conveyor for receiving eggs from at least one egg grading station and carrying said eggs to a plurality of spaced discharge stations where said eggs are selectively discharged in accordance with the grades assigned thereto at said grading station, said egg conveyor comprising a plurality of linearly arranged egg carriers adapted to be moved continuously at a uniform speed from said grading station to said discharge stations, the improvement comprising a memory device which includes, in combination:

a storage register comprised ofa plurality of information carrying sectors arranged in serial fashion;

means providing a continuous series of shift pulses at a first rate for serially shifting information through said register from each sector thereof to an adjacent sector and from the last sector thereof to the first sector thereof; means for providing phasing pulses at a second rate corresponding to the movement of the conveyor through a predetermined short linear distance, said first rate being faster than said second rate;

means for transferring information from said grading station into one of the sectors in said register in accordance with the grades of the eggs received by said conveyor; means for transferring information from one of the sectors of said register to said discharge stations to cause the selective discharge of said eggs in accordance with said information, both of said means for transferring information being operative only with respect to the sectors at the ends of the register;

counting means connected to said means for shifting said register for correlating the information in said register at any given time with the position of the eggs on the conveyor;

and means connecting said phasing pulse providing means with said counting means so that the count in said counting means is increased by one each time that a phasing pulse is produced whereby the movement of the eggs on the conveyor is tracked as they move through said short linear distances.

12. A memory device according to claim ll wherein said counting means is arranged to repeatedly and continuously count said shift pulses up to a number directly corresponding to the number of sectors in said storage register. means for providing output signals from said counting means at certain predetermined counts, said last named means being connected to said means for transferring information to said register in order to effeet the transfer of said information at times when said counting means indicates certain predetermined counts.

13. A memory device according to claim 12 includ ing logic circuit means connected to said output signals from said counting means, said logic circuit means being arranged to provide an enabling signal to permit the transfer of information into and out of said register only during one complete cycle thereof during the interval between two consecutive phasing pulses, the duration of said enabling signal being very short ascompared with said interval between two consecutive phasing pulses.

14. A memory device according to claim 13 wherein said output signals from said counting means are connected to each of said discharge stations, and means at each discharge station for comparing information representative of a predetermined grade of egg with the information transferred out of said register at a time corresponding to an indicated count in said counting means associated with that discharge station whereby eggs of said predetermined grade will. be discharged at said discharge station when they reach the proper discharging position on said egg conveyor.

15. A memory device according to claim 14 including means for creating a variable delay in the time between the transfer of egg grade information to a discharge station and the discharge of an egg at that station so that eggs will be discharged at different positions at said station to fill a row of pockets in an egg container.

16. A memory device according to claim 8 wherein said means for creating a variable delay comprises a secondary serial shift register associated with each discharge station, means operatively associated with said phasing pulse providing means for serially shifting information in said secondary serial shift register, means for monitoring the output of certain cells in said secondary serial shift register, and secondary counter means for comparing a count dependent upon the number of eggs discharged at a discharge station with the secondary serial shift register output monitoring means to cause said eggs to be discharged consecutively at linearly spaced positions.

17. An egg grading machine comprising:

an egg conveyor including a plurality of linearly arranged and uniformly spaced egg carriers;

an egg grading station for sensing the grades of a series of eggs and sequentially delivering said eggs to said egg conveyor;

a plurality of spaced egg discharge stations positioned adjacent to said egg conveyor downstream of said grading station;

means for causing the selective discharge of said eggs at said discharge stations in accordance with the grades of the eggs sensed at said grading station;

means for moving said conveyor from said grading station to said discharge stations;

a storage register comprised ofa plurality of information carrying sectors arranged in serial fashion;

means providing shift pulses at a first rate for serially shifting information through said register from each sector thereof to the adjacent sector and from the last sector thereof to the first sector thereof;

means for providing phasing pulses at a second rate corresponding to the movement of the conveyor through a short linear distance, said first rate being faster than said second rate; means for transferring information from said grading station into one of the sectors in said register in accordance with the grades of the eggs received by said conveyor; means for transferring information from one of the sectors of said register to said discharge stations to cause the selective discharge of said eggs in accordance with said information; counting means connected to said means for shifting said register for correlating the information in said register at any given time with the position of the eggs on the conveyor; and means connecting said phasing pulse providing means with said counting means so that the count in said counting means is increased by one each time that a phasing pulse is produced whereby the movement of the eggs on the conveyor is tracked as they move through said short linear distances. 18. An egg grading machine according to claim 17 wherein said counting means is arranged to repeatedly and continuously count said shift pulses up to a number directly corresponding to the number of sectors in said storage register, means for providing output signals from said counting means at certain predetermined counts, said last named means being connected to said means for transferring information to said register in order to effect the transfer of said information at times when said counting means indicates certain predetermined counts.

l9. An egg grading maching according to claim 18 including logic circuit means connected to said output signals from said counting means, said logic circuit means being arranged to provide an enabling signal to permit the transfer of information into and out of said register only during one complete cycle thereof during the interval between two consecutive phasing pulses, the duration of said enabling signal being very short as compared with the interval between two consecutive phasing pulses whereby information in any sector in said register is transferred through all of the sectors in said register a considerable number of times between each pair of consecutive phasing pulses.

20. An egg grading machine according to claim 19 wherein said conveyor is moved at a continuous and uniform rate of speed, said predetermined short linear counting meansindicates a number greater than the number of egg carriers from said grading station to said furthest downstream discharge station.

22. An egg grading machine according to claim l8 1 wherein said output signals from said counting means are connected to each of said discharge stations, and means connected with said selective discharge means fat each discharge station for comparing information representative of a predetermined grade of egg with the information transferred out of said register at a time corresponding to an indicated count in said counting means associated with that discharge station whereby eggs of said predetermined grade will be discharged at said discharge station when they reach the proper discharging position on said egg conveyor.

23. An egg grading machineraccording to claim 22 including means for causing only a predetermined percentage of said predetermined grade of egg to be discharged at any one discharge station.

24. An egg grading machine according to claim 17 including means for creating a variable delay in the time between the transfer of egg grade information to a discharge station and the discharge of an egg at that station so that eggs will be dropped at different positions at said station to fill a row of pockets in an egg container.

25. An egg grading machine according to claim 24 wherein said means for creating a variable delay comprises a secondary serial shift register at each discharge 'station, means operatively associated with said phasing pulse providing means for serially shifting information in said secondary serial shift register, means for monitoring the output of certain cells in said secondary serial shift register, and secondary counter means for comparing a count dependent upon the number of eggs discharged at a discharge station with the secondary scrial shift register output monitoring means to cause said eggs to be discharged consecutively at linearly spaced positions.

- UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION PATENT NO. 1 3,898,435

DATED August 5, l975 INVENTOR(S) John N. Pritchard et al It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:-

Column 4, line 23: change "2,895,273" to --2,895,27 4-. Column 5, line l8: after l 7/8 insert -inch- Column 7, line 6: after "to (second occurrence) insert a hyphen. Column l0, line 26: change "busket" to --,-bucket--.

Column ll line 22: change "tram-" to --transline 23: change "sitted" to -mitted--;

line 48:- change "thee" to --the--;

- line 60: change "N0. to --No.--. 'Column l3, line 6l after "particular" insert --pack--.

Column l6, line 24: change "name" to --named--;

line 24: after "named" insert --means--.

Signed and Scaled this Fourth of January 1977 [SEAL] Attest:

RUTH C. MASON C. MARSHALL DANN Allefling ff Commissioner oj'Parenrs and Trademarks UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION PATENTNO.: 3,898,435

DATED August 5, l975 INVENTOR(S) John N. Pritchard et al It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below: v

. Column 4, line 23: change "2,895,273" to --2,895,27 4--.

Column 5, line l8: after "l 7/8" insert --1'nch Column 7, line after "to" (second occurrence) insert a hyphen. Column l0, line change "busket" to ---bucket--.

Column ll line 22: change "tram-" to -transline 23. change "sitted to --m1'tted--;

line 48: change "thee" to --the--;- 7 line 60: change "NO." to --No.--.

Column l3, line 6l after "particular" insert -pack--.

Column l6, line 24: change "name" to --named--;

line 24: after "named" insert --means--. J Signed and Scaled this Fourth Of January 1977 [SEAL] Attest:

RUTH c. MASON c. MARSHALL DANN Arresting ff Commissioner ofParents and Trademarks

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Classifications
U.S. Classification377/17, 377/22, 209/513, 377/54, 177/50, 209/565
International ClassificationB65B57/10, B07C5/16, A01K43/00, B65B57/00, B65B35/30, B65B35/46, B07C5/00
Cooperative ClassificationB07C5/16
European ClassificationB07C5/16