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Publication numberUS3898448 A
Publication typeGrant
Publication dateAug 5, 1975
Filing dateSep 26, 1973
Priority dateSep 26, 1973
Publication numberUS 3898448 A, US 3898448A, US-A-3898448, US3898448 A, US3898448A
InventorsClark James M
Original AssigneeClark James M
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Spiral scan generator
US 3898448 A
Abstract
A spiral scan generator utilizes a read-only memory having stored therein a sequence of binary signals representing the +/- DELTA X and +/- DELTA Y values obtained by calculating the positional changes required to move from one end to the other along a particular spiral path. The binary signals are converted to a corresponding number of pulses which define intermediate locations, and these pulses are fed to up and down counters whose recorded counts are converted into analog voltages for controlling, for example, a directional antenna. By reversing the direction of memory read-out and by selectively changing the sign of the DELTA X values, additional spirals of similar shape are formed.
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Description  (OCR text may contain errors)

United States Patent Clark Aug. 5, 1975 SPIRAL SCAN GENERATOR [76] Inventor: James M. Clark, 50 Clara Pl., Cedar m E'wm,1er Malc Olm Momson Grove NJ. 07009 Ass/stunt E.\'am1nerDav1d H. Malzahn 2 t. 26, l 7 [2 Med Sep 9 3 57 ABSTRACT [21] Appl' 40l014 A spiral scan generator utilizes a read-only memory having stored therein a sequence of binary signals rep- [52] U.S. Cl 235/152; 340/324 A resenting the MX and :AY values obtained by calcu- [51] Int. Cl. .1 G06f 1/02 lating the positional changes required to move from [58] Field of Search 235/152, 151.11, 197; one end to the other along a particular spiral path. 340/324 A The binary signals are converted to a corresponding number of pulses which define intermediate locations, [56] References Cited and these pulses are fed to up and down counters UNITED STATES PATENTS whose recorded counts are converted into analog volt- 3 254 ()3 5/1966 Kveim 735/152 ages for controlling. for example, a directional an- 'g 3/1968 tenna. By reversing the direction of memory read-out 3,493,732 2/1970 Zeheb 235/152 x and y Selectively Changing the Sign Of the AX values, 3,573,738 4/1971 Bottles et a1... 235/151,] 1 X additional spirals of similar shape are formed. 3,763,363 10/1973 Saita et al. 235/l52 3,763 364 10/1973 Deutsch 235/152 7 Clam, 4 Drawmg Flt-lures 1107.0 REEET I SYNC. SYNC V R v /H R R" '6 +8 +256 g F E COUNTER UP/DWN. F/F /F DWN. CLK-A CLK-B e BITS y-sYM x-SYM |o RE'figMcgNLY Y 8 A i 256 WORDS OF 8 BITS l Ax-MAG Ax-SIGN c.c. -B RATE GEN. :3

CODE-CONTROLLED RATE-GEN.

W0 R R U/D COUNTER COUNTER 2s 28 U ll D A D A COM 29\ I CONV' ABSOLUTE 30 EW A ELEVATION SCAN saw PATENTEI] AUG 51975 SHEET PATENTEBAUB 3.898.448

SHEET 2 9 HOI D REEET 8 I SYNC. SYNC.

l4 ll I5 l6 R R R R +8 +256 F F 3 COUNTER UP/DWN. /F IF 1 MN. CLK-A CLK-B 8 BITS y-SYM x-SYM l; Io READ ONLY MEMORY B A i l 256 WORDS oFsslTs K m/E 24 Ax-MAG l I M AYE: 2 AX-SIGN ADDITION I LOGIC I l siL 22 I \P 25 I V REGISTER I l T.E I c.c. 4- I l 2 RATE GEN. L' l J AySIGN CODE-CONTROLLED RATE-GEN.

I9 20 I I I I U/D 1 R I R V U/D COUNTER COUNTER II II D A D A CONV. CONV.

ABSOLUTE 3O SECANT l 3| ELEV I MP. ELEVATION l BEARING SCAN scAN Fig.2

PATENTEBAJB 3,898,448

SHEET --7 Z/TIME ACTUAL PATH I I l I o X I CLOCK W AX-RATE l l D I Ay-RATE W TIME 0 2 3 4 5 e 7 s Fig. 3

SPIRAL #2 I #4 #2 F256+| I UP DWN UP DWN UP A X I REVERSE SIGN I A X I REVERSE Fig. 4

SPIRAL SCAN GENERATOR The present invention relates generally to apparatus for and methods of generating spiral scanning signals and, more particularly, to a spiral scanning generator for controlling a directional antenna so as to have it move through a plurality of similar spiral paths.

There are numerous communication and detection systems which require the spiral scanning of a directional antenna to acquire a remote radiation or reflection source. In one particular satellite communication system, this acquisition must be accomplished provided the antenna is initially pointing no further than 6 from the satellite. To achieve this with a 2 diameter beam width, the antenna is moved in a spiral scanning path which is calculated to bring the antenna within O.8 of every point in a 5.2 radius circle centered at the starting point.

The mathematical complexity of this spiral introduces the same degree of complexity in the various scan signals that must be generated to control the antenna. To produce these signals with analog circuits would require elaborate electronic circuitry and would involve complementary problems relating to circuit accuracy and stability.

If a digital design is utilized, the mathematical complexity is easily accommodated; likewise, the circuit accuracy is readily controlled, and there is no problem of stability.

It is, accordingly, a primary object of the present invention to provide a spiral scan generator which can be utilized to control the movement of a directional antenna.

Another object of the present invention is to provide a spiral scan generator which requires a memory of relatively low capacity but which, nevertheless, develops a relatively high number of points along a spiral path so as to accurately and smoothly control the movement of a scanning antenna.

Another object of the present invention is to provide a spiral scan generator which stores only sufficient digital code information for a single spiral and which processes this information to form three more similar spirals.

Another object of the present invention is to provide a spiral scan generator for developing a first spiral which may be, selectively, rotating about the X or Y axis to produce other similar spirals.

Another object of the present invention is to provide a spiral scan generator wherein the change of coordinate positions from one point on the spiral to the next is stored, and intermediate points are computed along the straight line representing this change of points.

Briefly, and in general terms, the above objects of invention are accomplished by initially computing a series of points along a pre-selected spiral path and then converting this data into a digital code sequence which is stored in a read-only memory. A scan generator sequentially reads these positions, develops additional intermediate positions and converts all data to X and Y analog signals.

The computation of the spiral is a part of the design process and is not a function of any of the circuits employed. Hence, this computation may be readily accomplished with a digital computer. Only data for one spiral is stored in the memory, and additional digital logic is arranged to reverse the sign of this data at appropriate times, thus, transforming this one spiral into others which are rotated about the X and Y axis. as desired. This feature allows the memory to be four times smaller than would be required if data for each spiral had to be independently stored. The digital logic is arranged to read the memory in either a forward or backward sequence corresponding to traversing the spiral from the innermost to the outermost point or vice versa.

If only a few points along a spiral are stored then the scan motion becomes a series of relatively large jumps. These jumps are hard for the antenna control circuits and motors to follow. Also, the smooth curve of the spiral is only approximated by the sequence of straight lines connecting the scan positions stored in the memory. This causes further deviations from the desired scan path. Filtering of these signals can make this motion somewhat smoother, but this processing causes the actual scan to drag towards the inside of the true curve. Also, when the satellite is detected and the scan is stopped, the filtering causes the actual scan to slide past the true point of stopping.

Storing more points along the spiral, of course, produces a smooth path requiring less filtering and, thus, minimizing the undesirable effects just mentioned. The present invention produces a sufficient number of points for this purpose yet requires a comparatively small memory. This reduction of circuit cost, power and space is realized by storing the change of X and Y called AX and AY from one point on the spiral to the next instead of the X and Y values. The AX and AY values are smaller numbers than X and Y and, in general, require only half as much memory. Intermediate points are computed along the straight line representing this change by a code control rate generator which produces, in one preferred embodiment, eight scan points for each change of X and Y stored. Thus, with a readonly memory capable of storing 256 pairs of AX, AY values, approximately 2,000 points are generated to define each spiral. This technique allows the memory to be 16 times smaller than would normally be required to accommodate this information.

Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings wherein:

FIG. 1 of the drawings shows the four spirals that can be generated by the apparatus of the present invention;

FIG. 2 is a schematic diagram showing the scanning generator and the manner in which it controls a tracking antenna;

FIG. 3 illustrates how the intermediate points along a particular segment of a spiral are developed; and

FIG. 4 are wave forms helpful in understanding the operation of the system.

Referring now to FIG. 1 of the drawings, reference character 1 identifies a spiral scanning path which, if followed, will bring an antenna with a 2 beam width within 0.8 of every point in a 5.2 radius circle centered at the starting point. The equations for this spiral are:

x r cos 0,

y r sin 0, where r and 6 are specified by:

r=gn forO s n s n r= g V n (2nn for n, s n s N =0,,+ b forusnsN where n varies linearly with time over the range given, and g, and n are specified by:

The path velocity is constant for the outer 2 turns of the spiral and decreased toward the center for the inner one turn of the spiral to minimize the peak acceleration of the spiral. In case the satellite is not detected during the first spiral, the usual practice is to return to the starting point and to repeat the scan. Failure to so acquire the satellite may occasionally happen due to tracking error motions. Instead of returning viathe same spiral, a smooth return and additional scanning may be achieved by following spiral 2 shown in this FIG. This brings the antenna within 08 of every point within a 6 radius from the starting point. The second spiral, it will be appreciated, is obtained by rotating the first spiral about the X axis.

Additional assurance that the satellite will be acquired may be achieved by adding a third and fourth spiral obtained by rotating the first two spirals about the Y axis. These spirals correspond to spirals 3 and 4. FIG. 1, thus, depicts the combined paths of all four spirals, and this continuous scanning motion brings the antenna within 0.4 of every point in a 6 radius circle.

The spiral as mentioned hereinbefore was computed from the mathematical equations set forth above and, in one particular embodiment of the invention, 256 points were chosen along the spiral spaced such that the time to travel from one chosen point to the next is one two-hundred and fifty-six-hundredths of the time required to traverse the complete spiral. The values representing each of these points were rounded off to obtain the nearest grid point. The sequence of AX and AY' values was then obtained by subtracting one pair of X, Y values from the next pair along the spiral. These AX and AY values, which fell in the range from -7 to +7, were represented by a four-bit binary code, one bit designating the sign and the other 3 bits, the magnitude. The coded AX, AY values were accommodated in a read-only memory which had a size of 256 X 8 or 2048 bits.

Referring now to FIG. 2 of the drawings, these precalculated AX and AY values, which are stored in readonly memory 10 are periodically read out of this memory by an up and down address counter 11 advanced by clock oscillator 12. This oscillator, as is well known, provides highly accurate timing pulses at a pre-selected pulse repetition rate. These pulses pass through a gate 13, which may block their passage, when HOLD is activated and then to a divide-by-8 counter 14 before being applied to the up and down address counter ll. In this manner, address counter 11 is operated, either up or down depending upon the signal state at its down signal input terminal once for every eight pulses of clock B.

When address counter 11 counts upwardly, the 8-bit code from this circuit, which is applied to the address inputs of read-only memory 10, reads this memory in a forward direction, and the AX, AY read out values are appropriate for traversing spiral 1 from the inner end to the outer end. By the same token, when address counter counts down, the memory is read in a reverse order and the read out signals correspond to those values appropriate for an inward motion of the spiral.

When address counter 11 reaches either the upper or lower limit of its count, a signal is produced therefrom which is applied to flip-flop l5, and the output of this flip-flop is applied back to the counter to reverse its direction of count for the next spiral. Thus, as shown in FIG. 4, flip-flop 15 is effective to reverse the direction of memory reading and the direction of travel on the spiral whenever an end of the spiral is reached.

The divide-by-8 counter 14, as mentioned hereinbefore, causes the address counter 11 to count 8 times more slowly than the pulse rate of clock B from oscillator 12. Thus, eight clock pulses appear between successive AX, AY words read from memory 10.

Associated with this memory are a pair of codecontrolled rate generators generally represented by reference characters 17 and 18. These rate generators derive their inputs from the 3 bits of the AY and AX codes that represent the magnitudes of these quantities. These three portions of the code are indicated by the vertical arrow having the legend M. The fourth bit which identifies the sign and which is not utilized in the code-controlled rate generators, is applied to up and down counters l9 and 20 to control their direction of count for purposes which will be explained hereinafter.

The details of the codecontrolled rate generators and their precise manner of operation are set forth in applicants co-pending application, Ser. No. 401,016, Filing Date Sept. 26, 1973. However, for purposes of explaining the operation of the present invention, the following general description is presented:

Each rate generator such as 17 is made up of an arithmetic logic 21 which has an n-bit capacity. However, in its operation, it is required at times to add two n-bit numbers. Since an n I bit capacity is usually needed for this purpose, the output signal S that this arithmetic logic produces is not always the true sum signal but may differ therefrom by 2" whenever it is equal to or is larger than this value.

If M is one of the inputs and A the other, whenever M A is larger than or equal to 2", an overflow bit is produced from the arithmetic logic and the number S is 2" smaller than the correct sum. Thus, only part of this sum S M A 2 is sent to the accumulator register 22, and this action occurs when the trailing edge of the next B clock pulse appears at the transfer terminal of this register. The output of accumulator register 22 is connected to the input of arithmetic logic 21 in a feedback manner so that when each new A is at the arithmetic logic, it will cause a new S to be generated. Because of this, the above transfer must be completed before S changes to a new value.

The overflow bit from the arithmetic logic 2] is fed to an AND gate 23 which has as its other input clock pulses from oscillator 12. Consequently, an output pulse is generated from the clock pulses each time an overflow bit occurs. This pulse train corresponds to the AY rate.

If accumulator register 22 had the capacity to store the complete sum then the input code M would be added repeatedly. Thus, if the initial content of the register was after K input pulses, the register would accu mulatethesum O+M+M+M...+M=KM.

However, since the register can accommodate only n-bits, it can store only numbers in the range 0 s A 2", and as noted above, whenever the sum equals or exceeds this range, 2" is subtracted by not being transferred into the accumulator register 22. Whenever 2' is subtracted, the overflow signal is a 1 which causes an output pulse to be produced via AND gate 23. If'L output pulses are produced for the K input pulses then L 2" have been subtracted and the actual sum in the accumulator register is a KM L 2". From this equation, we get The limited range ofA has the effect of causing the second term A/2' to be smaller than 1 no matter how large L and K are. Therefore, the output pulse rate M/2 X f where M is the input code andf the pulse repetition rate of clock 12. In the present case, n is 3 and the input code M may be changed after every K 8 input pulses so that equation (8) becomes L M A/8. But since A must be 7 or less, A must return to zero during this interval because L must be an integer. Thus, L M output pulses are generated for every input code M and K 8 input pulses. (If A were originally non-zero, it would still return to the original value, and M output pulses would still be generated, although with a slightly different time schedule.)

The code-controlled rate generators, thus, produce a number of pulses corresponding to the magnitude of the AX and AY codes read out of memory 14. For example, if AY is or +5 then five of the eight clock pulses are selected. The AY rate signal, consequently, produces as many pulses in the interval between successive addressing of the memory as the magnitude of the AY code, and the same is true with respect to the AX rate signal.

The manner in which a typical segment of one of the spirals is generated may be best understood by considering FIG. 3 which correlates this segment with the two pulse trains developed by code-controlled rate generators 17 and 18. The 25th segment of the first spiral starts at point X= l2 and Y +7. Its next calculated point is X 15, Y= +2. AX is, therefore, 3 and AY is 5. These are the values, it will be appreciated, that are stored in the read-only memory at this location. Thus, the AY code input to arithmetic logic 21 is 5 and the sign associated therewith negative. The AX code input to arithmetic logic is 3 and the sign associated with it negative.

Assume now that the count stored in accumulator register 22 is 2, for example. Then the counting sequence with a three-bit arithmetic capacity will be as follows: 2,7 4 1,6 3 0,5 2. After this, of course, the sequence repeats itself. Since each arrow represents a case where the arithmetic logic reached eight or above and eight was subtracted therefrom, these arrows correspond to the presence of an overflow bit, and the production of an output pulse at the AY rate. Since eight additions were performed, one for each clock pulse, then, as indicated hereinbefore, the code-controlled rate generator 17 has produced five pulses corresponding to the value M fed thereto.

By the same analysis, it can be shown that a codecontrolled rate generator 18 during the same interval will generate only three pulses, and these pulses correspond to the AX magnitude.

The AY rate signal which appears in the output of the AND gate 23 is fed to an up and down counter 19 whose direction of count is determined by the sign signal read out of memory 10 on line 24. In the case under discussion, as shown in FIG. 3, the five pulses constituting this train, which occur in the time intervals shown, decrease the count registered therein by five. By the same token, the three pulses making up the AX rate produced by rate generator 18 go to up and down counter 20 and depending upon the sign associated with the AX and the condition of an exclusive OR gate 25, either increase or decrease the count registered therein by this number. The exclusive OR gate 25 is controlled by a second flip-flop 16 cascaded to flip-flop 15 and depending upon the signal conditions at the output of this second flip-flop, either changes or does not change the sign that is read out of memory 10 and applied to up and down counter 20.

As shown in FIG. 3, the combination of the AX rate and AY rate pulse trains causes the spiral to move along the path I, 2, 3, 4, 5, 6, 7, 8, which approximately follows the straight line shown.

The digital counts in the up and down counters l9 and 20 are converted to analog voltages by appropriate digital to analog converters 26 and 28. The output of converter 26 goes to an elevation scan circuit 30 of the antenna, while the output from the digital to analog converter 28 is sent to a secant amplifier 29 and then to the bearing scan circuit 31 of the antenna.

The purpose of flip-flop l6 and exclusive OR gate 25 is to reverse the AX signs each time the spiral reaches its outer limit. Thus, when spiral 1 reaches point 70, address counter 11 commences to read memory 10 in a downward direction to bring the spiral back to the origin, the AX signs are reversed so as to produce spiral 2. When this spiral is completed at the origin, address counter 11 now reads the memory upward, but the signs associated with AX are maintained in reverse and spiral 3 is produced. When this spiral reaches point 71, the AX signs are again reversed, and spiral 4 is formed. These signs stay reversed until spiral l attains point and so forth.

FIG. 4 illustrates the mode of operation of the address counter 11 and the condition of the sign of the AX values as each successive spiral is formed. The wave forms shown, it will be appreciated, are developed at the outputs of flip-flop l5 and 16.

It would be pointed out in connection with the operation of the above system that the scanning action may be interrupted and stopped at any desired point by simply operating HOLD circuit 9. This effectively prevents the application of B clock pulses to the address counter and other parts of the circuit. Likewise, there is a RESET provision 8 for restoring all of the various counting devices to the counts corresponding to the origin of the spirals. It would be noted that clock A, which is the signal appearing at the output of oscillator 12, is free running, but clock B at the output of gate 13 is stopped when the HOLD circuit is activated. The synchronous circuits forming part of these features delay the transitions of the HOLD and RESET so as to have them synchronous with clock A. This insures that all of the subcircuits will stop, start or be reset in unison and, thus, never fall out of step with each other.

It would also be pointed out that while the first spiral stops at the X axis, it could stop at any axis location. In this connection, it will be recalled the Y-sym signal available at the output of flip-flop causes inward and outward spirals to alternate and the signal X-sym at the output of flip-flop 15 causes the third and fourth spiral to be the mirror image of the first and second spirals.

What is claimed is:

1. Apparatus for controlling a displacable means so as to have it move along a spiral path comprising a memory having stored therein a sequence of n-bit binary signals designating the :AX and MY values obtained by calculating the positional changes between pre-sclected adjacent locations along a spiral path that has one end thereof at the origin of a coordinate system and the other end at a remote location therefrom;

means for periodically addressing said memory so as to read out the sotred iAX and iAY signals as either a forward sequence which corresponds to an expanding spiral or a reverse sequence which corresponds to a contracting spiral;

means for converting the MX and iAY signals so read out to a pair of pulse trains whose pulse repetition rates are determined by the numerical values of said :AX and :AY signals;

a pair of up and down counters;

means for feeding each pulse train to a different one of said counters whereby the count registered therein changes in the interval between successive read outs of said memory by amounts equal to the numerical values of said i-AX, :AY signals,

the direction of each change of count being determined by the sign associated with said iAX and :tAY signals; and means for converting the counts registered in said up and down counters to X and Y analog voltages, said analog voltages controlling the movement of said displacable means. 2. In an arrangement as defined in claim 1 wherein said means for addressing said memory automatically operates to read out said fix and said :L-AY signals as a first forward, a second reverse, a third forward and fourth reverse sequence; and means for reversing the signs of the MX signals read out of said memory during said first reverse and said second forward sequence whereby said displacable means moves along four different spirals with each having one end thereof at said origin.

3. In an arrangemnt as defined in claim 1 wherein the remote end of said spiral path is at a preselected X axis location; and

wherein said means for periodically addressing said memory automatically reads out said :tAX and iAY signals as a first forward complete sequence followed by a second reverse complete sequence; and means for reversing the sign of the iA signals read out of said memory during said first reverse sequence whereby said displacable means moves along a first spiral path of an expanded radius, and when it reaches said remote location, thereafter, moves along a second spiral path of contracting radius back to said origin, said second spiral path being a mirror image of said first spiral path. 4. In a system for controlling the movement of a displacable means so as to have it travel along a chosen path comprising a read out memory having stored therein binary signals designating the magnitude and sign of the AX and AY values obtained by calculating the positional changes required to move from one location to another along said path commencing at one end thereof which is at a particular point in a rectilinear coordinate system and terminating at the other end thereof which is remote therefrom; means for reading out of said memory said AX and AY binary signals;

means for producing from each AX signal so read out a number of pulses indicative of the magnitude of said AX signal and for producing from each AY signal so read out a number of pulses indicative ofthe magnitude of said AY signal;

a pair of up and down counters;

means for feeding the pulses produced from each AX signal and AY signal to different ones of said counters;

means for controlling the direction of count of said counters in accordance with the sign of the corresponding AX and AY signals; and

means for converting the counts recorded in said up and down counters to X and Y analog voltages, said analog voltages being utilized to control the movement of said displacable means.

5. In an arrangement as defined in claim 4 wherein said means for reading out of said memory automatically reverses the direction of said reading when an end of said path is reached.

6. In an arrangement as defined in claim 4 wherein the AX and AY binary signals which are read out of said memory are read out in equal time intervals; and

wherein the calculated locations along said path are such that said movable means travels between adjacent locations in equal time intervals.

7. In an arrangement as defined in claim 4 wherein said path has theshape of a spiral; and

wherein said displacable means corresponds to a directional antenna.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,898,448 Dated g st 5, 1975 James M. Clark Inventor (s) It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

The assignee should read United States of America as represented by the Secretary of the Navy Signed and Emalcd this fourth D 3) 0f November I 975 [SEAL] Arrest:

RUTH C. MASON C. MARSHALL DANN Arresting Officer Commissioner of Patents and Trademarks

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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4023027 *Nov 10, 1975May 10, 1977Rockwell International CorporationCircle/graphics CRT deflection generation using digital techniques
US4225936 *Aug 10, 1978Sep 30, 1980Siemens AktiengesellschaftFunction generator with storage matrix
US4267579 *Jul 13, 1979May 12, 1981Norlin Industries, Inc.Digital waveform generator having constant signal to noise ratio
US4719592 *Oct 26, 1983Jan 12, 1988International Computers LimitedSequence generator
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Classifications
U.S. Classification708/270
International ClassificationH01Q3/08, G06F1/03, G06F1/02, H01Q3/10
Cooperative ClassificationH01Q3/10, G06F1/03
European ClassificationG06F1/03, H01Q3/10