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Publication numberUS3904856 A
Publication typeGrant
Publication dateSep 9, 1975
Filing dateDec 5, 1973
Priority dateDec 6, 1972
Also published asDE2360212A1
Publication numberUS 3904856 A, US 3904856A, US-A-3904856, US3904856 A, US3904856A
InventorsLouis Monpetit
Original AssigneeSopromi Soc Proc Modern Inject
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Control method for internal combustion engines
US 3904856 A
A control system and method for the ignition and fuel system of an internal combustion engine of a vehicle in which certain operating conditions of the engine and vehicle are sensed and converted into coded information which can be processed by the computer controlling the system.
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Description  (OCR text may contain errors)

United States Patent Monpetit Sept. 9, 1975 [54] CONTROL NIETHOD FOR INTERNAL 3,713,427 1/1973 Adler 123/32 EA COMBUSTION ENGINES 3,714,590 1/1973 Freeman et a1. 340/347 AD 3,742,920 7/1973 Black 123/32 EA Inventor: Louis Monpetit, g 3,757,755 9 1973 Carner 123 32 EA France [73] A Soc t d Pr ed M d FOREIGN PATENTS OR APPLICATIONS ssignee: 1e e es 0c es 0 ernes d,lnjection p y, France 1,939,611 2/1970 Germany 132/32 EA [211 APPL NOJ 422,062 7 Williams: Electronic Fuel Injection, Electronics, September 11, 1972, Vol.45, No. 19, pp. l2ll25.

[30] Foreign Application Priority Data Primary Examiner Felix D- Gmber Dec. 6, 1972 France 72.43329 Attorney Agent or Firm Darby & Darby June 4, 1973 France 73.20169 June 6, 1973 France 73.20514 [57] ABSTRACT [52] F' 235/ izah g i ig i A control system and method for the ignition and fuel [51] 235 6 2 150 21 system of an internal combustion engine of a vehicle [58] me d 0 g f 1 in which certain operating conditions of the engine l l and vehicle are sensed and converted into coded information which can be processed by the computer [56] References Clted controlling the system.

UNITED STATES PATENTS 3,591,785 7/1971 Miller 340 347 AD 28 Clams 21 Drawmg Flgum SPEED PRESS.



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sum 2 5- COUNT 2'2 couNk 2-3 I BUF AND 434 A i- AND 3.8



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X1 X 3 4 5 x X8 NAND PATENTEU 5 3,904,856

sum 6 H NAND 9.7 S b 51% COUNT DIV 2 NAND '6- couN T\ COUNTER 01v 2 9.10 H

PATENTED 91975 3,904,856

SHEET 7 11.6 Jig/1(a) 11.7 (6K 11. 2

PATENTED W975 3,904,856

SHEET 8 (FROM 11.28 FIG) F; iiOM 116 FIG I!) 12.7

12.5 12.5 NAND COUNTER MONOSTABLE "7' 12.23 ,LWL 1250 MONOSTABLE NAND. -Myw 12.18 12.40

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SHEET 1 1 l F7 A n J Tr N m CONTROL METHOD FOR INTERNAL, COMBUSTION ENGINES This invention concerns a control method for internal combustion engines, particularly for car engines.

It is known that improvements can be made in the riding comfort, safety, performance, and pollution control of motor vehicles by the use of electronic circuits. These circuits are used to check and/or to control, the operation of certain elements, or to inform the driver of the vehicle about the respective conditions of such elements. These circuits use techniques which are generally known in the field of information or industrial process computers.

In vehicles equipped with an electronic control sys tem, the computer receives information in various forms from sensors which constantly monitor the operating conditions of the vehicle or of a certain part of the vehicle. Starting from this information produced by the sensors, one can work out a complex function depending on the variables sensed by the sensors to control elements of the vehicle or simply to make the value of the said function visible or audible to the driver. In either case, it is frequently advantageous to use numerical (i.e. digital) techniques, which can now be readily processed due to the existence of integrated circuits.

The object of the'invention is to provide a simple system for producing information supplied by the sensors in numerical, that is in coded digital form and ways to transform and utilize this coded information.

The present invention concerns a control method and system for internal combustion engines and is characterised in that the coded information supplied by the sensors measuring physical operating quantities of the engine are produced at a certain frequency, the socalled sampling frequency. The coded information is produced in the form of a number of word segments comprising a limited number of digits and the means valve of several samplings of the word segments is representative of the mean value of the corresponding physical quantity, since the word segments are grouped to form a complete first word. The first word is converted by a programmed memory into a second word and the second word is converted by a transformation circuit into a function whose mean value is representative of the mean value of a desired regulating function. This regulating function is converted into a control quantity for the engine.

Other characteristics of the invention will become apparent from the following description with reference to the attached drawings where:

FIG. 1 shows a schematic diagram of a circuit for forming the sampling frequency and the signals at various points of the circuit;

FIG. 2 shows a schematic diagram of a coding circuit for a frequency measurement with interpolation and displacement'of zero in the case where the sampling frequency is lower than the measured frequency;

FIG. 3 shows a schematic diagram of a coding circuit for a frequency measurement to eliminate the stroboscopic effect in the case where the sampling frequency is of the same order of magnitude as the measured frequency;

FIG. 4 shows a schematic diagram of a frequency measuring circuit for retention of the first numbers of the measured quantity;

FIG. 5 shows a schematic diagram of a circuit for forming a sawtooth signal and its utilization with a comparator;

FIG. 6 shows a schematic diagram of a circuit for producing a numerical code in response to a voltage;

FIG. 7 shows a schematic diagram of a circuit for forming a linear function;

FIG. 8 shows a schematic diagram of a circuit for the formation of a linear function from coded information;

FIG. 9 shows a schematic diagram for forming the mean value of a linear function in a numerical form;

FIG. 10 shows a schematic diagram of a circuit for transforming a voltage into a time duration;

FIG. 11 shows a diagram of the arrangement of a speed sensor (11a), of the structure of the sensor (1 1b), and (11c) of a circuit, incorporating this sensor, for forming a doublefrequency signal;

FIG. 12 shows a schematic diagram of a circuit for forming two signals in the particular case of ignition control of the engine;

FIG. 13 shows a block diagram of a complete circuit for system and method according to the invention;

FIG. 14 shows a schematic diagram of a circuit for numerical counting used for measuring a physical quantity by sampling;

FIG. 15 is a timing diagram of a circuit for converting a linear into a non-linear function;

FIG. 16 shows a curve representing the variation of the cyclical ratio in accordance with one embodiment of the invention;

FIG. 17 shows a curve representing the variations of the cyclical ratio according to another embodiment of the invention;

FIG. 18 shows a schematic diagram of a simplified electronic circuit for the formation of the function represented in FIG. 3; and

FIG. 19 shows a diagram of output signals of the circuit of FIG. 18 for the different values of the cyclical ratio.

Within the framework of the invention, the signal supplied by a sensor is translated into a numerical digital) form. The sensors used inan automobile or other vehicle are of different type and of different nature. They translate their measurements in the form of a variation of a measured electric quantity. This information can exist directly in numerical digital form, for example, the position of an element provided with a digital enloder. This type of sensor does not present any particular problems.

The information can also be represented by pulses of variable frequency called, for example, f,. This is the case, for example, in a sensor of the type detecting the proximity with regard to a gear provided with teeth. In this case we measure, as shown in an example below, either the frequency of the pulses or their repetition cycle. We will generally choose these among two possibilities, depending on the respective problem and particularly on criteria discussed below.

If it is necessary, as it frequently happens, to form the mean value of an electrical signal to represent the mean value of a physical quantity varying about a given posi tion, it is advisable, if the operation is to be representative, that the response of the sensor be linear.

The signal of the sensor can also be in the form of a voltage. In this case we can proceed by using known voltage-frequency converters, for example, to periodically compare the sensor voltage with a variable (sawtooth) voltage and measure the number of pulses supplied by a clock, while the sensor voltage is lower (or higher) than the reference voltage. This is a technique which is well] known, for example, for use in electronic voltmeters.

Finally, the sensor can deliver its information the form of variations of a resistance, inductance or electric capacitance. These variations can be easily transformed into variations of voltage or pulse frequency.

The part of the computer provided for the acquisition of data from the sensors must furnish periodically at a given frequency, called the sampling frequency, coded information in the form of digits such that the mean value determined after a sufficient number of samplings is representative of the mean value of the physical input quantity to the sensor.

Referring to FIG. 1, which shows a circuit for controlling the sampling frequency, the quantity or quantities from the sensors are measured during a time T. The time T is obtained, for example, by dividing pulses produced by a clock circuit H.

The clock H directs pulses of a frequency l/T to a divider 1 whose intermediate outputs are represented by A A A,, At the output A,- the frequency of the pulses is equal to the clock frequency, divided by 2 By means of the AND gates 2, 3 and and of an inverter 4 connected to the clock and the divider the following quantities are formed at the gate Outputs:

S SyAyl-I (A is the inverted state of A The sampling period is, for example, T 2" T,, which is found in the S S or S, outputs, as indicated in the diagram adjoining FIG. 1.

Measurement of a frequency.

The measurement of a frequency, produced as previously described, is simple. It suffices to count, for example, how many pulses are produced by the quantity being measured as expressed by a frequency during the time T.

If we take into account the conditions listed above, the problem becomes more complex. I

In order to facilitate the understanding assume, for example, that the frequency of the clock pulses from H is 1 mI-Iz (T, seconds). Assume further that we have effected a division by 2 (n 10), that is, T 512 microseconds (the division by a power of 2 is not obligatory). Finally, assume that a pulse frequency to be measured varies between 0.4 and 0.8 MHZ.

If the method described above is applied, the number of pulses counted will be between:

We realize then that a counter with at least 9 digits (2 512) is required to count the number of pulses received with an accuracy of 1 pulse. The counter will always have to start at at least 204.

In order to eliminate this inconvenience, a circuit according to FIG. 2 is used. Element 2.1 is a NAND gate as is 2.5. Element 2.4 is an AND gate while elements 2.2, 2.3 and 2.6 are binary counters. Element 2.7 is a transfer unit, such as a buffer storage registerv which can store the count operation of the circuit of FIG. 2 as described as follows. The gate 2.1 forwards the pulses whose frequency f I is to be measured during a time T 2""1, which; is less than a time A2 high,

that is, inthe highest example 512 2 X 1 510 microseconds. It follows that during .a sampling time, N pulses with N between 0.4 X 5. 1X10 204 and 0.8 X 5.1 X 10 408 pulses will pass through gate 2.1.

The counter 2.2 is connected as a divider to divide by D so that the number of pulses leaving 2.2 and entering counter 2.3 and gate 2.5 is N/D. These pulses are applied to counter 2.3 and the outputs of certain stages of 2.3 are applied to the inputs of AND gate 2.4, so that the output of 2.4 is high only when the outputs from 2.3 appearing at the input of 2.4 are all high, that is, when 2.3 has counted a certain number of pulses. The output of AND 2.4 is applied back to a special input of 2.3, which blocks the counter when the certain count is reached, and also to gate 2.5. The pulses from counter divider 2.2 thus traverse gate 2.5 to counter 2.6, only when counter 2.3 has attained the value fixed by the selection of its outputs which are connected to AND 2.4.

At the end of the sampling period T, 2.6 marks a number N N D/N n, if n is the number selected by the output coding of 2.3 applied to AND 2.4 Assume, for example, that D and f, is 0.4 MHz so that N/D 2.04.

This indicates that two pulses are produced by counter 2.2 during T and that at the end of T counter 2.2 has counted 4. If we assume that n 2, this means that at the end of T, if all counters were at zero at the start, the situation would be as follows:

number of pulses 204 counter 2.2 at the end of T 4 counter 2.3 at the end ofT 2 counter 2.6 0.

Let us assume that the cycle starts again after it has been effected by S (see FIG. 2) applied to the suitable inputs of the counters 2.6 and 2.3 from the circuit of FIG. 1 during the time S, but without resetting counter 2.2 to zero.

At the end of the second sampling we have then:

At the end of three samplings we have 2.6 O and so forth, at the end of 25 samplings we have:

This means that the device of FIG. 2 performs two operations:

1. it interpolates the values 2. it eliminates the numbers below a cutain value, and

if we want, it displaces the Zero value of the input pulses.

In other words, the circuit of FIG. 2 is suitable to produce an output count of 0 for N less than 200, an output count of l for N 300, an output count of 4 for N 700.

If a value of N is between 200 and 300, 204 for example, the output counter 2.6 marks for (x y) samplings, x times 0 and y times 1, so that that is, the interpolation is effected simply by the frequency of two numbers surrounding the value of N, so that the numerical value is equal to the coded value which would have to be attributed to N.

Buffer 2.7 receives signal S, from the circuit of FIG. 1 and under the order from S transfers in each cycle the value received at its inputs to its outputs for further use. The circuit of FIG. 2 permits the elimination of useless numbers (saving of digits) and also the interpolation between values, provided the frequency of f, is high relative to the sampling frequency. If the latter is not the case, the circuit of FIG. 3 is used.

The circuit of FIG. 3 can perform operation similar to those of the circuit of FIG. 2, but on the theory that the frequency f to be measured is not very high compared to the sampling frequency. The problem is then that in order to know the value of the frequency f it suffices in principle to count the pulses during a sufficient period of time to obtain the desired accuracy. In the case of a computer for vehicles, it is desirable to know at a relatively high frequency the values close to the frequency to be measured so as to be able to express it by a number counting a few digits. The measurements are made so that the mean value of the displayed values is equal to the measured value. Taking into account these conditions, we can accept, as in the case of the circuit of FIG. 2, a period for resetting to or holding at zero during which there is no counting. In fact, there is a risk of ending up with a wrong result, due to the stroboscopic effect. If the frequency to be measured, is, for example, equal to 4 times the sampling frequency, the counter will have an output count of 3 or 4, depending on the relative phase of the sampling scale and of the pulses of f,. A solution consists in counting the pulses f constantly.

The operation of the circuit of FIG. 3 is described below. The pulse at the start of the sampling (5,) is applied to one of the inputs of a flip-flop circuit (RS type) 3.1, which has the effect of bringing the output of 3.1 connected to one of the inputs of an AND gate 3.6 to the high level. This also has the result that the complementary output of 3.1, connected to an input of an AND gate 3.5, is brought at the same time to the low level. The pulses f, arrive at the other inputs of gates 3.5 and 3.6. This has the result that when 3.1 flips into operating position at the start of the appearance of S,, the f, pulses can pass through gate 3.6 in this condition, while they are blocked from passing through gate 3.5. The appearance of a pulse f, is thus transmitted to a flip-flop (RS type) 3.3 through gate 3.6 and changes this flip-flop circuit into the operating state. The output of flip-flop 3.3 connected to one of the input of an AND gate 3.4 goes high.

To the other input of gate 3.4 is applied S, (S inverted) by an inverter 3.2, so that the output of gate 3.4 goes high when:

a. its input connected to 3.3 is high, that is, when the pulse f from gate 3.6 has been counted and b. its input connected toS, is high, that is, during the dead time of S,.

The output of gate 3.4 is connected to the zero reset inputs of flip-flops 3.1 and 3.3 to cause the flipping back of 3.3 and 3.1 to the opposite states this causes the opening of the gate 3.5 and closing of gate 3.6. A counter 3.7, AND gates 3.8 and 3.9, counter 3.10 and buffer 3.11; are elements respectively corresponding to 2.3, 2.4, 2.5, 2.6 and 2.7 of FIG. 2 with the same functions, (elimination of the pulse count below a selected number) of counting and resetting to zero (by S and data transfer (by 8,). By a suitable arrangement of inputs and polarities, the circuit elements of FIG. 3 can be so arranged that the flipping of 3.3 is counted or not. If it is not counted, we obtain directly the elimination of the first number. The counting by the circuit of FIG. 3 is permanent, the counting element is generally 3.10. During the dead time of S,, or 8 and until the first f, pulse following the start of 8,, the counting element (of 1) consists of 3.3 (and 3.1). This presupposes naturally that the time when S, is high is smaller than the minimum period of f which is practically always the case (low frequency of f In the opposite case, we can replace 3.3 by AND gate 3.9 and count several pulses before opening the principal counter 3.10.

FIG. 4 shows a circuit which is simpler than that of FIG. 3 and which performs a similar function. A flipflop circuit 4.1 (RS type) receives at its working input the signal S, which makes the output connected to an AND gate 4.2 go high and the output connected to an AND gate 4.7 go low. This has the result that the pulses f, can pass gate 4.2 and not 4.7. Element 4.3 is a counter similar to 2.3 and blocks the first pulses below a selected number. When, after the start of sampling, a number of pulses equal to that selected and coded by counter 4.3 and an AND gate 4.4 (as explained for elements 2.3, 2.4 in FIG. 2) has traversed gate 4.2, the output gate of 4.4 goes high. This has the effect of returning flip-flop 4.1 into its rest condition and consequently of blocking gate 4.2 and opening gate 4.7. The counting is continued then by a counter 4.5 which has been reset during S, to zero by signal S The count of 4.5 is transferred to a buffer 4.6 and it is outputted from 4.6 by the 8;, signal.

Measurement of a voltage The measurement of a voltage from a sensor is effected by counting pulses during a given time, such as the linear portion of a sawtooth wave. A circuit for accomplishing this is represented in FIG. 5.

The signal S, is applied to the base of a transistor 5.6 to discharge a capacitor 5.2 which is connected between the transistor collector and its emitter. Capacitor 5.2 is recharged through a resistor 5.5 and is connected across the inverted input and the output terminal of an operational amplifier 5.1. The non-inverting input of the amplifier is biased by a voltage divider 5.3, 5.4. This well-known circuit produces a highly linear sawtooth at the output of 5.1.

The sawtooth voltage is compared by a comparator 5.7 with the amplitude of the voltage to be measured. The output of 5.7 is low, while the sawtooth voltage is higher in amplitude than the voltage to be measured, and the output is high in the opposite case.

If the sawtooth voltage is designated by V,,, then V is translated from the end of the S, by the expression V Va kt where V and k depend on 5.3, 5.4 and 5.5.

The flipping time of comparator 5.7 is such that .1 V where Te (V110 The measuring time is, for example, the sampling time minus S, and Te, hence in the case described above,

2" "T, 2T, T,. A BV where A and B are constants.

The circuit of FIG. 6 is similar to that of FIG. 2 and shows the measuring arrangement. The output of comparator 5.7 is applied to an AND gate 6.1. When the output of comparator 5.7 is high (after flipping of the comparator) and S, is low, I being applied to AND gate 6.1, the gate 6.1 forwards the clock pulses H to a counter 6.2. The pulses are counted by 6.2, which reduces the number (interpolation or division) and transmits them to another counter 6.3 which is programmed by a gate 6.5, as explained above, for 2.4 for the elimi nation of the pulse count below a certain number. This permits, once the certain number is reached a counter 6.7 to count the pulses transmitted by 6.2 when a gate 6.4 has become conditioned to pass signals by counter 6.3 and gate 6.5. At the end of the cycle (S, high), the counting is stopped since 6.1 is closed. S resets counters 6.3 and 6.7 to zero. S ensures the transfer of data from the buffer register 6.8. Counter 6.2 is not reset to zero for the reasons indicated above.

Decoding utilization.

With the means indicated above we can transform the signals supplied by one or more physical quantity sensors into one or several numbers, which generally vary with each sampling, so that the mean value represents the value of the measured physical quantity. As a result, each quantity is expressed at the end of each sampling by a binary number which comprises, as required, a given number of digits.

To facilitate the understanding of the invention, assume that we want to form a regulating function depending on four variables L M N 4). Assume that the quantity L is expressed by 3 binary bits '(8 possible numbers), the quantity M by 4 bits (16 possible num ber), M by 2 bits (4 possible numbers) and d) by 1 bit (2 possible numbers). This means that the result of the sampling can be written in the form of a binary number with (3 +4+2+ l)= lObits, or

L1 2 3 1 2 3 4 1 2 1 where the values L, M, N, d) are or 1. The first word segment consists of L, L L the second word segment of M, M M M,, the third word segment of N, N and the fourth of ab.

O l 1 1 O O 1 l O 1 means that for this word we have the variable L with a numerical value of 3.

have the variable M with a numerical value 9 have the variable N with a numerical value 2 have the variable (i) with a numerical value 1 The total number of possible words is 8 X 16 X 4 X 2 1,024 (2 According to a well-known technique of programmed memories, we can associate with each of these 1,024 words a number which is representative of the value which we want to give the function of L M N d), at the point under consideration. The word point is here understood in a broad sense, because we are evidently not dealing here with a geometric point, since it has five dimensions.

In the course of the sampling the word varies if each quantity does not correspond exactly to a ,fixed value of L M N 5, which corresponds to the interpolation function explained above. It follows that the associated value varies likewise since its mean value is equal to the mean value of the linear form as a function of L M N 1) passing through fixed points.

To facilitate the understanding, we assume that L is between L, and L,- M between M,- and M,-,,, N between N,, and N and d) between (1), and (15 If we designate with 2,, the quantity and designate then the weight of the quantity F,- 1 associated with L M,, N and is:

That i+11 1+1 k+1i 1+1 is L' M' N That of i+l, as 2,, (PE 2 4 1-2,) and so forth.

The mean point of the function F, an associated function, is the barycenter of these points having the indicated loads.

These numbers F are expressed by a binary code comprising the digits defined by the accuracy to be obtained, namely, X,, X X Iffis the selected number of digits, X, is the highest load digit,'and X, the lowest load digit.

Decoding The formation of a linear voltage is described. We assume that f is less than (n-l the number of pulse train outputs of the divider 1 of the circuit of FIG. 1. If this is not the case, we can always add one or more elements to the circuit of FIG. 1, and use only (n-l) to form the sampling time indicated above.

We form the quantity:

In the course of a sampling, the value of the cyclical ratio high/(high low) of this function is representative of F and independent of the frequency.

To facilitate the understanding, We assume that we have In the course of a sampling period the quantity is:

a, A} is 256 times high and 256 times low a A, K is 128 times high while a, is low a A, A is 64 times high, while a, and a are low a, A, A A 1?, is 32 times high, while a,, a and a are low a A, A A A, is 16 times high, while a,, a a

and a, are low a, A A A A, A A, is 8 times high while a,, a

a a, and a,, are low a A, A A A, A A A is 4 times high while a,

through a,, are low a,, A, A A A, A A A A 2 times high while a, through a, are low It follows that the ratio of the high signal to the total sampling time of S is We can thus write R 2F/5 12). This means that the value of sampled F is expressed 2 times per sampling time T. If we had on the other handf= n-l, a single exploration would correspond to each sampling.

Since we are dealing here with a cyclical ratio, this value is independent of the clock frequency and of the sampling frequency.

FIG. 7 shows the circuit of a decoder. The circuit, uses by way of example, only the NAND gates. The first gate forms the quantity: A17, =3, The second gate forms the quantity: A A X a The 8th gate forms the quantity: A A A X E.

The final gate formszm a +a a S. In order to obtain an analagous voltage representation of F, it suffices therefore to place at the output of S a filter (passive or active) of the RC-type.

Other method of forming-the voltage. FIG. 8.

Another example of a decoding circuit for forming a voltage from the code recorded in a memory is shown in FIG. 8. To facilitate the understanding of the forego ing considerations, we assume that the problem consists here too in expressing in the form of a voltage the means value ofa regulating hypersurface depending on 4 parameters L M N qb, translated at each moment by a code with several digits X,-. By any or several of the methods described above for sampling information, we direct at each moment numbers L M N (1) to the inputs of a programmed memory 8.1. The system can be arranged without a latches circuit, or buffer, such as 2.7, 3.11, 4.6 or 6.8, between a number representative of the measuring state of one of the quantities and the memory.

To show this method of forming the circuit, there is represented in FIG. 8(b) an arrangement, assuming for example, that the translated quantity L is measured by means of a circuit, such as that of FIG. 6. The quantity M by a circuit such as that of FIG. 4, the quantity N by a circuit such as that of FIG. 3 and the quantity d by a circuit such as that of FIG. 2. This choice is simply made by way of illustration. Also assume that the counting capacity of these circuits has been necessarily limited by the choice of the counters.

Blocks 6.7, 4.5, 3.10 and 2.6 represent the circuit elements of FIGS. 6, 4, 3 and 2 respectively from which the connections are made to the programmed memory 8.1. This means that these elements have been connected directly to 8.1, eliminating the buffers 6.8, 4.6, 3.11 and 2.7 respectively.

In this arrangement the bits Ll change continually during sampling at the inputs 8.1.10 to 8.1.19 of the programmed memory 8.1. This produces variations at the outputs X,- of the memory 8.1, called the code gate. In fact, the outputs X, of 8.1 are connected to the inputs of a preselection counter 8.2. The outputs of this counter are connected to a NAND gate 8.3. The counter 8.2 also receives a transfer signal at another of its input, called the charge input 8.9, with each pulse at the end of the sampling, such as signal S described above. When all the inputs of gate 8.3 are high, the output at 8.7 is low, which has the result that the clock pulses H applied to the input 8.5 of a NAND gate 8.4

can arrive at the counting input 8.8 of 8.2. The second input 8.6 of 8.4 is low in this case and the output of 8.4 is therefore always high. On the other hand, if at least one of the outputs of 8.2 is low, the output of 8.7 is high and consequently 8.4 forwards the clock pulses H to 8.8 and the counter 8.2 can count.

The method of operation of the circuit of FIG. 8 is described as follows. When the brief transfer pulse 8;, is applied to 8.9, the counter 8.2 is charged to a number n, such as:

This represents exactly the value of the sampling at the time of measurement.

Assume that the counter 8.2 has 8 digits and that its counting capacity ranges therefore from O to 255. It follows therefore that 8.7 is high, except when n 255. Consequently, the pulses H arrive generally over 8.4 (unblocked) at 8.8. As soon as S stops, the counter 8.2 counts starting from n: (n l), (n 2) When it attains 255, all outputs are high, 8.4 is blocked, 8.7 goes low and the counter remains in the state 255 up to the next impulse S Assume also that the repetition period of S in n,.H, that is equal to n times the clock period H, which period is simply obtained by dividing the clock frequency by n by means of a well-known device. Also assume that S has a duration equal to n H, that is n times the clock period. The output 8.7 is then high during a time I where 2,, n I-I (255n)l-l, or more generally, I n H (255n)H. If N is the capacity of 8.2, the ratio I divided by the repetition frequency of the phenomenon is thus:

It follows that the simple filtering of the output 8.7 of 8.3 yields a voltage which is a linear fiinction of n and, consequently, that its mean value is equal to the mean value of the desired regulation.

Formation of the numerical mean.

Referring to FIG. 9, the following is the procedure to obtain the mean value of the function F in numerical form. The clock pulses that exist while S (FIG. 7) is high are counted for a certain number of samplings, for example, for 2, and we use for the representation of the value of F only the number of pulses divided by 2". That is, we use only the (b 1 first digits of the counter.

The pulses S of the divider of FIG. 1 are directed to a divider 9.1 which divides by 2" (FIG. 9) which brings the output of a NAND coding gate 9.2 inverted by inverter 9.3 to the high level when it has received 2" pulses (or another code).

This inverted output from inverter 9.3 is applied to one of the inputs of each of NAND gates 9.4, 9.5, 9.6. To the gate 9.4 is applied at a second input the signal 5, so that a low pulse of duration S appears at its output for all 2" samplings. This low pulse is applied to one of the inputs of a NAND gate 9.7, which also receives the clock pulses H and the signal S of FIG. 7.

It follows that H is present at the output of 9.7 if S is high (decoding) and if the output of 9.4 is high. Gate 9.7 is blocked for a duration 8,, for all 2" samplings. The transmitted pulses are counted by the counter 9.8 which divides their number by 2" and transmits a signal to a counter 9.10 once every 2 pulses.

It follows that the counter 9.8 marks a number N from a zero at the start of a cycle after 2 samplings The gates 9.5 and 9.6 permit, according to an already described connection, the conditioning of 9.8 and 9.10 at each mean cycle by S and 9.5 and the transfer of data from the buffer register 9.1 1 by gate 9.6 and signal S Transformation of the voltage (or code) into a dura tion.

It can happen that we want to transform the signal S of FIG. 7 coded by modulating the cyclical ratio into a time duration, which is, the time of the fuel injection, for example. A circuit for accomplishing this is shown in FIG. 10.

To the base of a transistor 10.1 is applied a positive release signal (connected, for example, to the fuel injection release control mechanism), which makes tran sistor, 10.1 conductive to discharge a capacitor 10.5 through a current limiting resistor 10.4, to the emitter potential of 10.1. The emitter potential fixed by the voltage divider 10.15, 10.14 is stabilized by a capacitor 10.16.

The discharge of capacitor 10.5 reduces the voltage at the non-inverting input of an amplifier 10.6 and the output signal of 10.6 increases. This signal is applied to one of the inputs of a NAND gate 10.9, which receives at its other input the release signal inverted by an inverter 10.17 so that, though the output of 10.6 is high, the output of NAND 10.9 is high up to the end of the release signal, which thus does not have to be accurate in duration. At the end of this signal the output of NAND-gate 10.9 becomes low until the output of amplifier 10.6 goes low.

The foregoing is the case when the voltage of 10.5 is higher than the voltage applied to the non-inverting input of 10.6 from a transistor 10.2. The latter voltage is obtained by an RC filter 10.12, 10.11, connected to the collector of 10.2, which receives at its base the signal S of FIG. 7.

The response of the circuit of FIG. 10 is exponential. That is, for a given variation of V according to the absolute value of the latter, the variation of the time is different. This is frequently of interest for an injection circuit, for example, but it is evident that the response can be linearized by replacing 10.3 by a constant current generator.

Transformation into angles.

It can happen that we want to transform the signal S into an angle. This is obtained easily by a circuit similar to FIG. 10, except that the resistance 10.3 is replaced by a generator which furnishes a certain amount of voltage each time an angular mark is counted. To facilitate the understanding of this arrangement, we will show in detail how these signals are formedin a specific and rather complex case, from which simple cases can then be deduced. The selected problem is given below.

It is desired to deliver a signal twice per revolution of a motor, for example, signals which will be substantially in diametral opposition, but with an angular position. These signals are a multi-dimensional function of several parameters and are to be delivered, for example, over two different paths. This would be the case, for example, in an ignition system for four-cylinder engines without distributor, each signal releasing the ignition in two cylinders controlled simultaneously by the same coil.

The angles can be marked, for example, by counting the teeth of the starting gear of the motor. To this end, as indicated in FIG. 11(a), a sensor is placed opposite said teeth. This sensor can be of any type, optical, with a blocking oscillator, electromagnetic, etc. The gear 1 1.1 carries a toothed starting ring 1 1.2 opposite which is placed a proximity sensor 1 1.3 which delivers signals at its output 1 1.4. Also provided is a hole or a slot 1 1.5, which can be sensed by a sensor 1 1.6, called a synchronization sensor, which delivers a signal once per revolution. The slot 11.5 is put in place before the mechanical balancing of the wheel.

In the case under consideration, an operation is to be effected every half revolution of the engine. The number of teeth 11.2 of a starting device is, in general, a prime number and hence non-divisible by two. It is convenient to first obtain a double frequency, that is a signal each time an angle equal to half the angle of successive teeth is traversed. To this end an evident solution, not shown here, consists in placing two sensors, such as 11.3, displaced relative to each other by (n+l/2)a. Here, a is the angle which separates two consecutive teeth and n is any integral number. The outputs of the two sensors, after adaptation of the impedance if necessary, are coupled to an OR gate, and at the output of this gate appears the signal with the desired frequency.

The same method can be used to obtain a signal with a frequency k times higher than that which is naturally produced by the teeth by displacing k sensors, such as the sensor 11.3, relative to each other by angles (n, (i-1)/k)a, with i=- l,2,3 (k1 The first sensor is numbered zero and taken as the origin of the displacements. This permits obtaining a resolving power which is'k times more accurate than the natural frequency produced by the teeth.

In the particular case of the selected example, where k 2, we can obtain a satisfactory solution with a single sensor, such as 11.3, by selecting a sensor of the magnetic type with variable reluctance. This sensor, shown in FIG. 11(1)), comprises a magnetic armature 1 1.8 carrying a double-ended pole piece spaced in an interval equal to that of two consecutive teeth of the wheel. A coil 11.9 is placed around the pole piece and one end is connected, for example, to ground, while the other end 11.4 is free.

The sensor of FIG. 11(b) is inserted into the electronic circuit shown in FIG. 11(0). The coil 11.9 is supplied current through a resistance 11.10 connected to the positive voltage terminal of the installation. The passage of the teeth of 11.2 of the gear produces variations of voltage at the coil 1 1.9. The voltage produced varies in correspondence substantially as the minimum and the maximum reluctance condistions of the sensor 11.3, that is, substantially when the teeth face each other and when the teethare in maximum angular phase displacement. This undulating voltage is transmitted directly through a resistor 11.11 to one of the inputs of a sum-and-difference amplifier 11.15. The mean, or average, value of this voltage is applied to the other input through a resistor 11.14, this value being obtained by an RC filter consisting of a resistor 11.2

and the capacitor 11.13. The amplifier 11.15 passes then from a high state, for example, to the low state, when the teeth oppose each other, and from the low state to the high state when the teeth are in maximum phase displacement.

The change in state of 11.15 from low to high is derived by an RC circuit 11.20, 11.26 and is transmitted over a diode 11.24 to the base of a transistor 11.28 which is normally blocked by the voltage across a resistor 11.27. A resistor 1 1.21 permits the discharge of capacitor 1 1.20 when the output 1 1.16 of amplifier 1 1.15 is low. It follows that a short duration low signal is produced at the collector of transistor 11.28 with each change of voltage from low to high at 11.16.

The signal at 11.16 is inverted by a transistor 11.19 applied to its base by resistor 11.17. The signal at 11.16 produced at the collector of 11.19, which is supplied voltage by a resistor 11.18, goes positive each time 11.16 passes from high to low. This signal is used like the direct signal of 11.16, that is, it is derived by an RC circuit 11.29 and applied by a diode 11.23 and a resistor 11.25 to the base of a transistor 11.28. The resistor 11.22 serves to discharge capacitor 11.29, while 11.16 is high. It follows that a short duration low signal is produced when 11.16 passes from high to low. Finally there is produced on the collector of transistor 11.28 a signal with double the frequency of the natural frequency, which is the objective to be achieved.

FIG. 12 shows how the preceding information is used to solve the problem in question. The double frequency pulses formed as in FIG. 11 are applied to the input 12.1 of the circuit shown while the synchronization pulses (assumed negative and of an angular width of less than /2) from sensor 1 1.6 are applied to the input 12.6 of the same circuit. Element 12.2 is a counter with p digits with a counting capacity of (2 1), when (2 l) is greater than 211, where v designates the number of teeth 11.2.

Element 12.3 is a gate type circuit which delivers to its output 12.41 a negative (low) signal when the outputs of the counter 12.2 pass through a number representing a number predetermined by the internal connections of 12.3. Element 12.4 is similar.

Element 12.3 is coded for a number equal to 211. If A is the signal produced by 12.3 at 12.41 and B that applied to a gate 12.5 by the synchronization sensor 1 1.6, a signal C is present at the output of a gate 12.5, where:

C=K=K+E It follows that signal C becomes high, whether A or B or both become low. This high signal applied to the proper input of counter 12.2 ensures its resetting to zero.

Since the frequency of B after one revolution of the motor, that is, 211 pulses to 12.1, is the same as that of A (12.3 wired for 21/) the resetting of 12.2 to zero after at most one revolution of the motor is such at any time that the number appearing at the output of 12.2 is equal to twice the number of teeth passed by after the passage through the position of the slot or hole 11.5 of FIG. 11(a) in front of the sensor 11.6. The output 11.7 of sensor 11.6 is connected to 12.6 as mentioned above.

The signal A is negative and extremely brief, since it causes the resetting of 12.2 to zero and thereby causes its own disappearance over the element 12.3. This negative signal flips an RS type flip-flop circuit consisting of the NAND gates 12.8 and 12.9, this flipping brings the level of 12.8 high. At the first pulse following the resetting to zero of counter 12.2, the output of its least significant bit (2) passes from low to high. This signal (2) is applied to an inverter 12.7 which is connected to the second input of NAND 12.9 and causes the flipflop circuit RS to flip back. It follows that at each revolution of the motor, starting from the angular position of resetting to zero, if we take it as the origin, the output 12.8 moves to high during an angle equal to a/2.

The device 12.4, similar to 12.3, is coded to a value equal to v, which has the result that after u impulses, after the resetting to zero, its output moves down and remains there, until 12.2 counts (11 1), that is, during an angular development equal to 04/2. This signal is inverted by the inverter 12.12.

This inverted signal and the signal issuing from 12.8, formed as described above, are applied over diodes 12.13 and 12.14 to the base of a transistor 12.15 so that the latter is made conductive from the position 0 to the position a/2 and from the position to the position (180 04/2). This has the effect of discharging a capacitor 12.28 substantially to the potential of the emitter of 12.15, a potential formed by a divider 12.21, 12.20 stabilized by a capacitor 12.19.

To a 12.18 of the transistor 12.17 are applied over a resistor 12l18 from terminal 12.16 rectangular signals whose cyclical ratio is representative of the regulation, for example, those originating from the output 8.7 of 8.3 of FIG. 8(a).

This transistor is applied voltage at its collector by a resistor 12.22 connected to the positive terminal of the circuit. An RC filter 12.23, 12.14 supplies the output of 12.17 through a resistor 12.25 to the non-inverting input of an operational amplifier 12.35. The output voltage of 12.17 has a value between the circuit supply voltage applied by a resistor 12.22 and the voltage applied to the emitter of 12.17 from transistor 12.15 and is representative of the mean cyclical value of the signals applied at 12.16.

The discharge of capacitor 12.28 causes, as mentioned above, the downward passage of the inverted input of amplifier 12.35 and consequently the upward passage of its output. This state remains as long as 12.15 is conductive, that is, during an angle 01/2. The capacitor 12.28 is then recharged intermittently in the following manner. With each impulse arriving at 12.1 a monostable circuit 12.36 is triggered (represented here as an integrated circuit, which is known). The negative pulses of fixed duration delivered by it are applied over a resistor 12.37 to the base of a transistor 12.34. During these pulses transistor 12.34 is thus blocked, permitting the application to the base of a transistor 12.30 of the high output voltge of amplifier 12.35 over a voltage divider 12.32, 12.33. It follows that, as long as the output of amplifier 12.35 is high, and only during this time, negative pulses of a duration equal to that of the pules of the monostable circuit 12.36 are applied over a resistor 12.31 to the base of a transistor 12.29, making it conductive by these pulses and charging capacitor 12.28. It follows that from the start of the moment when 12.15 is non-conductive, the voltage applied over 12.37 to the inverted input of 12.35 rises intermittently. When this voltage becomes equal to that applied to the noninverted input, amplifier 12.35 switches back.

This switching thus produces a number nR of impulses arriving at 12.1., after the end of the conduction.

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U.S. Classification701/101, 123/486, 123/487
International ClassificationF02P5/15, F02D41/24, G06J1/00, F02D41/30, G06F7/62, F02D41/36
Cooperative ClassificationF02D41/28, F02D41/365, F02P5/15, G06F7/62, F02D41/30, F02D41/2406, Y02T10/44, G06J1/00, F02D41/2403, Y02T10/46
European ClassificationF02D41/28, F02D41/36B, G06F7/62, G06J1/00, F02D41/24D, F02D41/30, F02D41/24B, F02P5/15