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Publication numberUS3913056 A
Publication typeGrant
Publication dateOct 14, 1975
Filing dateJul 1, 1974
Priority dateJul 1, 1974
Also published asCA1037616A1
Publication numberUS 3913056 A, US 3913056A, US-A-3913056, US3913056 A, US3913056A
InventorsLevinson Lionel M
Original AssigneeGen Electric
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Varistors with patterned electrodes
US 3913056 A
Abstract  available in
Images(1)
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Claims  available in
Description  (OCR text may contain errors)

United States Patent 1191 Levinson Oct. 14, 1975 [54] VARISTORS WITH PATIERNED 3,096,496 7/1963 Burrage et a1. 338/21 ELECTRODES P E C L Alb rima xaminer ritton [75] Inventor: Llonel M. Levmson, Schenectady, g Agent, or Firm jack E. Haken; Joseph T.

Cohen; Jerome C. Squillaro [73] Assignee: General Electric Company,

Schenectady, NY. [57] ABSTRACT [22] Filed; July 1, 1974 Current channeling through stacks of polycrystalline varistor devices for high voltage surge protection ap- PP bio-14841610 plications is prevented by applying patterned electrodes to the varistor elements of the stack. The pat- 52 us. Cl 338/21; 338/20 temhtg of the eleettedes Prevent8 the formation of an 51 Int. 01. 1101c 7/12 equi-petential Surface ever the ihtertaee between [58] Field of Search 338/20, 21; 3177/61, 615 ments of the stack. Therefore, currents are prevented from channeling through the preferential current [56] References Cited paths in each element of the stack and more equal UNITED STATES PATENTS current distribution through the devices is provided resulting in substantially increased reliability of the 1,509,495 9/1924 Slepran 338/21 X Stack and its elements 1,509,496 9/1924 Sleplan 338/21 2,891,194 6/1959 10 Claims, 4 Drawing Figures McStrack et a1. 317/61 X 7/ V IN IJN IIN' II VARISTORS WITH PATTERNED ELECTRODES This invention relates to polycrystalline varistors. More particularly, this invention relates to a novel electrode configuration for polycrystalline varistors for improving the current homogeneity through series stacks of polycrystalline varistor elements for high voltage surge protection.

There are a few known substances whose resistance characteristic is non-linear and is expressed by the equation Y I c where I is the current flowing through the material,

V is the voltage applied across the material,

C is a constant which is a function of the physical dimensions of the body, its composition, and the parameters of the process employed to form the body, and

a is a constant for a given range of current and is a measure of the non-linearity of the resistance characteristic of the body.

A well-known example of such varistor materials is silicon carbide. Silicon carbide and other non-metallic varistor materials are characterized by having an alpha exponent of less than 6. Recently, a family of polycrystalline metallic oxide varistor materials have been produced which exhibit an alpha exponent in excess of 10. These new varistor materials comprise a sintered body of zinc oxide crystal grains, including additionally an intergranular layer of other metal oxides and/or halides, as, for example, beryllium oxide, bismuth oxide, bismuth fluoride, or cobalt fluoride, and are described, for example, in US. Pat. No. 3,682,841, issued to Matsuoka et al. on Aug. 8, 1972 and US. Pat. No. 3,687,871, issued to Masuyama et al on Aug. 29, 1972.

In the electric power distribution arts, it is common to provide high voltage surge protective apparatus at various points in a distribution network to protect the elements of the network and apparatus of electric power customers from damage by high energy surges caused, for example, by lightning strikes or transient load anomalies. Spark gaps and silicon carbide varistors have been employed in the past for this purpose. Because of the relatively low alpha exponent, silicon carbide devices employed for surge protection are usually connected in series with spark gaps. Because of their superior varistor performance, the new metal oxide varistor devices are theoretically considered able to provide superior performance in voltage transient suppression stacks for power distribution systems.

In the configuration in which polycrystalline metal oxide varistors are presently manufactured, the varistor material as described above is pressed into a diskshaped body having a pair of opposed major faces and is then sintered to produce a ceramic varistor disk. A pair of electrodes is applied to the opposing major faces of each disk. High voltage stacks for protection in electric power distribution systems are constructed by serially stacking an appropriate number of electroded disks. Silicon carbide varistor stacks for high voltage surge protection are similarly configured.

In the case of the polycrystalline metal oxide varistors, however, the extremely high alpha exponents,

which provide for superior varistor performance, creates a problem in high voltage, high energy, stacks in that the adverse effects of any nonuniformity of varistor characteristic in a disk is magnified in the degree of undesired current channeling which occurs. Small variations in varistor voltage in a polycrystalline metal oxide varistor disk cause very large current distribution variations through the disk. This current channeling through the disk, in which a very small cross-sectional area of the disk carries almost all of the current flowing between the electrodes across the disk produces thermal stresses within the disk which may fracture it and otherwise contributes to premature failure of the disks. In the case of high voltage surge suppression stacks comprising a plurality of disks having a unitary electrode on each major face of each disk, current channeling occurs through the weakest portion of each disk with the deleterious effects described above.

It is, accordingly, an object of this invention to provide a polycrystalline metal oxide varistor element for inclusion in high energy power distribution surge suppression stacks in which selective current channeling through the elements of the stack is prevented to increase the reliability of the stack.

It is another object of this invention to provide such a polycrystalline varistor element having patterned discontinuous electrodes on the opposing major faces of the element to prevent selective current channeling through the disks of a stack by preventing the formation of equi-potential surfaces at the interface between successive disks of the stack.

It is another object of this invention to provide a high energy, high voltage surge suppression stack having improved current distribution uniformity through the stack.

Briefly, and in accordance with one embodiment of this invention, a body of polycrystalline varistor material having a pair of opposed flat faces has discontinuous electrodes applied to each of the opposed flat faces. The electrodes provide for electrical contact to the body of polycrystalline varistor material, but, because they are discontinuous, they prevent an equipotential surface from existing at the faces of the varistor body. In another embodiment of this invention, a plurality of such varistor bodies having discontinuous patterned electrodes on the major faces of each body are serially stacked to form a high energy, high voltage surge suppression stack in which substantially uniform current distribution through the stack occurs when a voltage across the stack exceeding the varistor voltage thereof occurs. The uniform current distribution is the result of the absence of an equi-potential surface between the elements of the stack and in turn produces a stack in which uniform current distribution therethrough provides improved reliability and performance.

The novel features of this invention sought to be patented are set forth with particularity in the appended claims. The invention, together with further objects and advantages thereof, may be understood from a reading of the following specification and appended claims in view of the accompanying drawings in which:

FIG. 1 is a cross-sectional view of a portion of a high energy, high voltage surge suppression stack illustrating the deleterious effect of current channeling through the stack. 1

FIG. 2 is a plan view of a polycrystalline varistor element for inclusion in high energy, high voltage surge suppression stacks in accordance with this invention having patterned electrodes on the major faces thereof.

FIG. 3 is a sectional elevation view of a high energy, high voltage surge suppression stack in accordance with this invention.

FIG. 4 is a sectional elevation view of a portion of a high energy, high voltage surge suppression stack in accordance with another embodiment of this invention in which insulation material is applied to the major faces of the elements of the stack in complementary pattern to the electrodes thereon.

FIG. 1 illustrates a prior art polycrystalline varistor stack comprising varistor elements 10, 20, and 30 having respectively electrodes 11 and 12, 21 and 22, and 31 and 32 on opposite major faces thereof. As a result of inhomogeneities of material in varistor elements 10, 20, and 30, each element has a preferential current path, respectively, 13, 23, and 33 therein. Because electrodes 12 and 21 and electrodes 22 and 31 provide equi-potential surfaces at the junctions between varistor elements and and 20 and 30, a preferential current path through the entire stack exists. As a result, when a voltage surge exceeding the varistor voltage of the stack occurs, substantially all of the current flowing through the stack flows through the preferential current channel comprising preferential current channels 13, 23, and 33 of the constituent elements of the stack. This results in local heating in the vicinity of the current channels, which may produce fracturing of one or more of the elements of the stack thereby destroying the stack, or may otherwise degrade the performance of the stack as, for example, by electrochemically damaging the varistor elements or the electrodes applied thereto.

In accordance with this invention, current channeling through high energy, high voltage surge suppression stacks is prevented by applying patterned electrodes to the elements of the stack as illustrated in FIG. 2. FIG. 2 shows a major face of polycrystalline varistor element 40 for inclusion in a high energy, high voltage surge suppression stack having electrode means applied to the major faces thereof. The electrode means applied to the faces of varistor disk 40 in accordance with this invention comprise conductive elements 41 applied to the faces of disk 40 in a discontinuous pattern. The discontinuity of the electrode means in accordance with this invention results in the absence of an equipotential surface over the interfaces between elements of a stack and thereby prevents current channeling through an entire stack and prevents the deleterious consequences of such current channeling. Since preferential current channels are spatial randomly located in individual polycrystalline varistor elements, the prevention of current through a stack seeking the preferential channel of each disk of the stack by patterning the electrodes in accordance with this invention greatly improves theeffective homogeneity of a stack as a whole.

While the conductive elements 41 of the patterned electrode shown in FIG. 2 are illustrated as square, this invention is not so limited and other patterns may be employed. The geometry of the pattern is also somewhat a matter of design choice within the constraints imposed by the facts that too large a spacing between conductive elements 41 undesirably decreases the effective volume of varistor element 40 available for utilization and too small a spacing will lead to undesired conduction paths across the surface of varistor element 40 between adjacent electrode elements 41. In practicing this invention, optimally, conductive elements 41 of the patterned electrode should cover approximately two-thirds of the surface area of varistor element 40 and the non-conductive areas 45 should cover approximately one-third of the surface of varistor element 40. Each of conductive elements 41 should cover less than 3 percent of the surface area of varistor element 40.

FIG. 3 is a sectional elevation view of a portion of a high energy, high voltage surge suppression stack in accordance with this invention comprising a plurality of varistor elements as shown in FIG. 2. FIG. 3 shows varistor elements 40, 50, and 60 having patterned electrodes on opposite major faces thereof. Varistor ele ment 40 has an electrode comprising conductive elements 41 on a first face thereof as shown in FIG. 2 and a second electrode comprising conductive elements 42 on the opposite face thereof. Similarly, varistor elements 50 and 60 have electrodes on opposite faces thereof comprising respectively conductive elements 51 and 52, and 61 and 62. Upon the occurrence of the voltage surge exceeding the varistor voltage of the stack illustrated in FIG. 3, conduction paths through the varistor elements of the stack including elements 40, 50, and 60 exist between opposing pairs of conductive elements of the electrodes on opposite sides of each disk. No conductive path exists along the interface between adjacent varistor elements because of the patterning of the electrodes. Accordingly, the current flowing through the varistor stack of FIG. 3 is prevented from selectively channeling through the disks of the stack as described above with reference to FIG. 1. Therefore, current distribution through the stack of FIG. 3 is more uniformly distributed through the varistor elements including elements 40, 50, and 60 illustrated in FIG. 3 comprising the stack.

FIG. 4 illustrates an alternative embodiment of a varistor stack in accordance with this invention wherein the modification comprises the inclusion of insulating material in a pattern complementary to the conductive element pattern in the electrode surfaces associated with each varistor element. In FIG. 4 varistor elements 70, 80, and have patterned electrodes on opposite faces thereof comprising respectively conductive elements 71 surrounded by insulating material 73 on a first major face of varistor element 70, conductive elements 72 surrounded by insulating material 74 on a second major face of varistor element 70, conductive elements 81 surrounded by insulating material 83, and conductive elements 82 surrounded by insulating material 84 on opposite major faces of varistor element 80, and conductive elements 91 and 92 surrounded respectively by insulating material 93 and 94 on opposite major faces of varistor element 90. The inclusion of insulating material in the electrode surfaces serves to increase the electrical breakdown strength between adjacent c'onductive elements of the patterned electrodes, and also serves to protect the varistor stack from environmental contamination.

While this invention has been described with reference to particular embodiments and examples, other modifications and variations will occur to those skilled in the art in view of the above teachings. Accordingly, it should be understood that within the scope of the appended claims, the invention may be practiced otherwise than is specifically described.

The invention claimed is 1. A polycrystalline varistor element for inclusion in a series stack of such polycrystalline varistor elements for high voltage surge protection comprising:

a body of polycrystalline varistor material having a pair of opposed flat faces; and

a plurality of conductive electrode elements applied to spatially separated areas on each of said opposed flat faces for providing electrical contact to said body, said electrode elements being separated, one from another, and adapted so that electric current flow between said separated areas is confined to said body of varistor material.

2. A polycrystalline varistor element as claimed in claim 1 wherein said electrode elements comprise a plurality of conductive elements disposed upon each of said opposed flat faces in a regular geometric pattern.

3. The varistor element of claim 2 wherein said conductive elements collectively cover approximately twothirds of the surface area of each of said opposed flat faces.

4. The varistor element of claim 3 wherein each of said conductive elements individually covers less than 3 percent of the surface area of the face upon which said conductive element is disposed.

5. The varistor element of claim 2 including additionally electrically insulating material disposed upon each of said opposed flat faces in a pattern complementary to said regular geometric pattern.

6. A high energy, high voltage surge suppression stack comprising:

a plurality of bodies of polycrystalline varistor material;

each of said bodies having a pair of opposed flat faces;

each of said flat faces having patterned electrode means applied thereto, said patterned electrode means being electrically discontinuous;

said bodies having said electrodes applied thereto being serially stacked with the electrode means applied to each said body being in contact with the electrode means applied to an adjacent said body.

7. A surge suppression stack as claimed in claim 6 wherein said electrode means comprise a plurality of electrically conductive elements disposed upon each of said opposed flat faces in a regular geometric pattern.

8. The surface suppression stack of claim 7 wherein said serially stacked bodies are aligned so that each of said electrically conductive elements is in contact with a corresponding said electrically conductive element applied to an adjacent said body to provide for electrically serial interconnection among said bodies and to prevent an equi-potential surface from existing along a junction between adjacent said bodies.

9. A surge suppression stack of claim 8 including additionally electrically insulating material disposed upon each of said opposed flat faces in a pattern complementary to said regular geometric pattern.

10. A polycrystalline varistor element for inclusion in a series stack of such polycrystalline varistor elements for high voltage surge protection comprising:

a body of polycrystalline varistor material having a pair of opposed flat faces;

a plurality of conductive elements disposed upon each of said opposed flat faces in a regular geometric pattern for providing electrical contact to said body; and

electrically insulating material disposed upon each of said opposed flat faces in a pattern complementary to said regular geometric pattern.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US1509495 *Apr 1, 1922Sep 23, 1924Westinghouse Electric & Mfg CoPlate and method of treating the same
US1509496 *Apr 1, 1922Sep 23, 1924Westinghouse Electric & Mfg CoPlate and method of treating the same
US2891194 *Mar 25, 1958Jun 16, 1959Mc Graw Edison CoOvervoltage protective device
US3096496 *May 11, 1961Jul 2, 1963Mc Graw Edison CoOvervoltage protective device
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4211994 *Dec 4, 1978Jul 8, 1980Matsushita Electric Industrial Co., Ltd.Resistors, polycrystalline
US4272754 *Dec 17, 1979Jun 9, 1981General Electric CompanyThin film varistor
US5594613 *Jan 20, 1995Jan 14, 1997Cooper Industries, Inc.Surge arrester having controlled multiple current paths
DE10241253B4 *Sep 6, 2002Apr 24, 2008Tridelta Überspannungsableiter GmbhÜberspannungsableiter
WO2003060926A2 *Jan 17, 2003Jul 24, 2003Tridelta UeberspannungsableiteSurge arrester
Classifications
U.S. Classification338/21, 338/20
International ClassificationH01C7/102, H01C7/10
Cooperative ClassificationH01C7/102
European ClassificationH01C7/102