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Publication numberUS3926087 A
Publication typeGrant
Publication dateDec 16, 1975
Filing dateOct 4, 1974
Priority dateOct 4, 1974
Also published asCA1016786A, CA1016786A1
Publication numberUS 3926087 A, US 3926087A, US-A-3926087, US3926087 A, US3926087A
InventorsGriffis Steven W
Original AssigneeGriffis Steven W
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Computerized organ registration affecting system
US 3926087 A
Abstract
A registration affecting system for electronic or pipe organs which provides for monitoring, storage and output actuation of stop and coupler key combinations selected by the operator of the organ. The translated outputs of organ pistons are input and scanned along a common data buss by a central processing unit. The central processing unit determines which registration aid function is being requested by the organ operator and causes actuation of the specific stop combination stored in a memory module. Upon a determination of the proper states of the stop and coupler keys to be actuated, the central processing unit initiates output actuation of the appropriate stop and coupler keys to select the tonal quality required.
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United States Patent [1 1 [111 3,926,087-

Griffis Dec. 16, 1975 COMPUTERIZED ORGAN REGISTRATION Primary Examiner-Stephen J. Tomsky AFFECTING SYSTEM Assistant Examiner.lohn F. Gonzales [76] Inventor: Steven W. Griffis, 4753 Irvine Ave., [57] ABSTRACT N. Hollywood, Calif. 91602 A registration affecting system for electronic or pipe [22] Flled' 1974 organs which provides for monitoring, storage and [21] Appl. No.: 511,996 output actuation of stop and coupler key combinations selected by the operator of the organ The translated outputs of organ pistons are input and scanned (5L2 along a common data p y a centpal processing Fieid 84/345 unit. The central processing unit determmes which registration aid function is being requested by the organ operator and causes actuation of the specific stop [56] References combination stored in a memory module. Upon a de- UNITED STATES PATENTS termination of the proper states of the stop and cou- 3,548,064 12/1970 Oncley 84/345 UX pler keys to be actuated, the central processing unit 3,659,488 5/1972 Deutsch.... 84/345 initiates output actuation of the appropriate stop and 3,686,994 8/1972 Badessa 84/345 couple keys to elect the tonal quality required,

7 Claims, 17 Drawing Figures ORGAN SW/TC/fES (4021/4 TOPS 2 I 18540 0W Mafia (Ad-F65) (001V 7' C 8 C Wye/74o. was wing/ 40: #000456 {KHz/02y is n l l9 2| U.S. Patent Dec. 16,1975 Sheet2of9 3,926,087

Patent Dec. 16, 1975 Sheet 3 0f 9 US. Patent Dec. 16, 1975 Sheet7of9 3,926,087

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our 1 our-2 0am COMPUTERIZED ORGAN REGISTRATION AFFECTING SYSTEM BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to capture combination systems, and more particularly, to those capture combination systems usable with electronic and pipe organs which utilize digital capabilities to store and initiate actuation of appropriate stop and coupler functions.

2. Prior Art The existence of combination systems for use with organs is well known in the prior art. The use of a combination system arises where an organist may wish to change the combination of selected stops or stop control which will thereby alter the tonal quality obtained while the organ is being played. Typically, a number of pistons or key switches are related with each division or keyboard of an organ. In a conventional organ, the pistons or key switches are located beneath each keyboard. a

In a conventional organ, a piston permits actuation of a selected group of stops when that piston is actuated. Actuation of a piston permits selection of any of a number of combinations of stops in accordance with actuation of corresponding ones of the pistons. The pistons are generally arranged in categories which. are identified by their control capabilities. Divisional pistons, for example, are associated with or assigned to a corresponding division and provide for control of only those voice stops and couplers associated with that respective division. Independent general pistons, on the other hand, provide for control of a combination of all of the stops provided in the organ simultaneously regardless of the relationship of groups of those stops to the specified divisions. The setting of the independent general pistons is in no way restricted by the selection of stops as established by any of the divisional pistons. Collective general pistons are related to the independent general pistons, each of the collective general pistons, when actuated, operate a corresponding piston in each group of divisional pistons.

The typical combination systems described in the prior art utilize a memory of some type for storing the combination of stops associated with each piston. Upon actuation of a piston, the combination system utilized by the prior art sets the corresponding stops as indicated in the storage medium. The prior art discloses numerous techniques to implement storage media for combination systems. The prior art systems utilize storage media such as mechanical linkages, electrical barswitches, and electronic memory systems.

The prior art discloses preset combination systems which include a storage media which has fixed wiring to select the preset storage combinations for an electronic organ. As a result, the stop combinations cannot be changed by the organist since the only way to make such changes is by rewiring the organ console. Another system discosed by the prior art is typically designated as a setterboard system, In a setter board system, a switch is associated with each stop, a row of switches being provided for each divisional piston. The storage media is set by positioningthe-switches in the desired on or off positions. A large number of such switches are obviously required in a setter board system and accordingly, independent general pistons are typically not provided with setter board systems, but rather only collective general pistons.

The prior art discloses combination systems which have been designated as capture combination systems, these systems permitting the organist toset information into a combination memory by means of the conventional organ controls. As an example, for the Swell division, a combination of stops can be selected which creates a tonal effect for each of the pistons of that division. The data constituting the stop combination is stored within the storage media by actuating a set piston, simultaneously actuating an available piston of that division. When the organ is being played, whenever that piston is depressed, the stops of the preselected combination which were captured in the operation with the set piston are retrieved, or set. A similar procedure is used to capture stop combinations for each divisional piston as well as the general pistons.

Although capture combinations do provide increased flexibility and ease for selecting approprite stop combination, the capture combination systems described in the prior art exhibit a number of undesirable characteristics. Where more than a single operator is using an organ, it would be typical for each operator to select a different program of stop combinations to be actuated by the pistons. Typically, the prior art capture combination systems have 25 or more pistons, each division having approximately 20 stops. Despite the apparent increased flexibility in the use with such systems, substantial delay and interruptions are often required to reset the captured combinations.

A specific capture combination system described in the prior art utilizes an internal and external memory to either manually input the selected stop combinations associated with each piston, or, through the use of a magnetic card, to input previously stored stop combinations. The difficulties inherent with such a system are substantially similar to those which are present in other capture combination systems described in the prior art. Since the settings can only be manually input, or previously stored through the use of manual selections as stored on a magnetic card, the selection of the stop combinations to be associated with each piston is again a timely operation.

The present invention substantially resolves the inadequacies existing in those devices disclosed by the prior art for determining and actuating appropriate stop combinations associated with a selected piston. Through the use of a read-only memory, no manual inputs of any kind are necessary to select the appropriate internal quality to be associated with a particular organ piston. The processing capability of what is, in effect, a general purpose computer organized to perform a specific function, permits complex selections of stop combination without the need of initially going through the manual insertion and storage procedures which are required by those systems described in the prior art.

SUMMARY OF THE INVENTION The present invention comprises an organ registration effecting system which utilizes digital techniques. Information concerning the states of all pistons and stop and coupler keys is transmitted to input interface modules which are translated to signal levels which are compatible with the internal equipment of the present invention system. The input interface modules comprise a set of multiplexers which isolate the proper 3 piston data to be available on the data buss. Input data is byte oriented and will be transmitted on the data buss to the central processing unit upon demand.

The central processing unit executes a set of instructions which are stored in a read-only memory. The instruction set for the central processing unit is specifically adapted to process the data being input from a pipe or electronic organ and to set up for output those stop combinations which have been previously stored in a random access memory. The list processing techniques which are utilized by the central processing unit will correlate the multiplexed input piston data with the stored stop combinations previously input to the present invention system. To permit the present invention to operate with substantially all types of electronic and pipe organs, a delay count is input to the input interface modules to specify an optimum value for output signals. The delay count is required to allow for variations in the actuation time for stop and coupler keys. By utilizing data processing techniques for correlating piston input data and selective stop combinations which are allocated to each piston, the present invention system provides an efficient way of establishing the stop combination in accordance with the previously stored data.

It is therefore an object of the present invention to provide an improved registration affecting system for electronic and pipe organs.

It is another object of the present invention to provide a registration affecting system which can be easily used with both electronic and pipe organs.

It is still another object of the present invention to provide a registration affecting system for pipe and electronic organs which does not require the manual input of stop combination data.

It is yet another object of the present invention to provide a combination system for pipe and electronic organs which is capable of performing all registrationchanging-aid functions.

The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objectives and advantages thereof, will be better understood from the following description considered in connection with the accompanying drawing in which a presently preferred embodiment of the invention is illustrated by way of example. It is to be expressly understood, however, that the drawing is for the purpose of illustration and description only, and is not intended as a definition of the limits of the invention.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a schematic, block diagram of a registration affecting system for pipe and electronic organs in accordance with the present invention.

FIG. 2 is a schematic diagram of the interface between an organ stop key and the present invention registration affecting system.

FIG. 3 is a schematic, block diagram, illustrating a portion of the multiplexor interface between the organ pistons and the data buss of the present invention system.

FIG. 4 illustrates the address decoder logic for the input multiplexor shown in FIG. 3.

FIG. 5 illustrates a schematic, block diagram of the output interface modules intermediate the present invention registration affecting system and the stop combination keys shown in FIG. 2.

FIG. 6 illustrates the address decoder logic for the output interface module shown in FIG. 5.

FIG. 7 illustrates the timing diagram for the output address decoder shown in FIG. 6.

FIG. 8 illustrates a schematic, block diagram, of the read-only memory utilized by the central processing unit in accordance with the present invention.

FIG. 9 illustrates the address decoder for the readonly memory shown in FIG. 8.

FIG. 10 illustrates a schematic, block diagram, of the random access memory modules utilized by the central processing unit in accordance with the present invention.

FIG. 11 illustrates the address decoder for the random access memory shown in FIG. 10.

FIG. 12 illustrates the timing diagram for the address decoder shown in FIG. 11.

FIG. 13 is a schematic, logic diagram, of the central processing unit shown in FIG. 1.

FIG. 14 illustrates the schematic, logic diagram of the central processing unit control shown in FIG. 13.

FIG. 15 illustrates a schematic, logic diagram, of the P register of the central processing module shown in FIG. 13.

FIG. 16 illustrates a schematic, logic diagram, of the R registers shown in FIG. 13.

FIG. 17 illustrates the timing diagram for the fetching of instructions from the read-only memory for the central processing unit shown in FIG. 13.

DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENT Referring now to FIG. 1, a better understanding of the interaction between the present invention organ registration affecting system and a pipe or electronic organ can be best seen, the organ being generally designated by the reference numeral 10. As stated hereinabove, the present invention is adapted to be utilized with either an electronic or pipe organ since the interface between the organ registration affecting system and organ 10 are compatable irrespective of the type of organ being utilized. In organ l0, pistons 11 permit actuation of a selected group of stops, couplers, or stop combinations 12 when one of the pistons 11 is actuated. Actuation of a piston 11 will permit selection of any of a number of combinations of stops 12 in accordance with a previously established program to be operated within the present invention system. The pistons 11 are generally arranged in category which are identified by their control capabilities. For the purpose of this discussion, all pistons shall be referred to by the reference numeral 11 of the specific category of the piston. Divisional pistons 11, for example, are typically assigned to a corresponding division of organ 10 and provide for control of only those voice stops 12 and couplers associated with the respective division. Independent general pistons 11, on the other hand, provide for control of the combination of all of the stops 12 provided in organ 10 regardless of the relationship of the groups of those stops 12 to the specified divisions. The setting of the independent general pistons 11 is in no way limited or restricted by the selection of stops 12 as established by any of the divisional pistons 11. Collective general pistons 11 are related to the independent general pistons, each of the collective general pistons, when actuated, operating a corresponding piston 11 in each group of the divisional pistons. As shown in FIG. 1, stop and coupler keys 12 typically comprise actuator 14. This shall. be discussed in further detail hereinbelow.

Data available from pistons 11 are transferred to input interface modules 15. In addition, input interface being transmitted from output interface modules 17 in a manner which will be described in detail hereinbelow. The detection of when and what piston 11 has been operated is transmitted from input interface modules on data bus 18, central processing unit 19 receiving and processing all data appearing on data bus 18. Readonly memory 20 permanently stores the special purpose program which is executed by central processing unit 19. Data flow between central processing unit 19 and read-only memory 20 is carried out via data bus 18. Random access memory 21 is used to store correlations between pistons 11 and the desired stop and coupler keys 12 for the combination registration function.

As a preface to the description of the logic and circuits utilized for implementation of the present invention organ registration affecting system, a description of the logic levels and circuit conventions shall be described. All signals internal to the present invention system shall be considered as true when in the high state unless the signal designation is preceded by the designation N. In the detailed description of the logic modules, the logic elements shown constitute standard symbols utilized within the computer industry, all being well known to those having skill in the computer art.

The implementation of stop and coupler keys 12 and their interface to input interface modules 15 and output interface modules 17 can be best seen by reference to FIG. 2. Stop key 12 utilizes manual handle 25 to provide for alternate on-off positioning between contacts 26 and 27. A conventional wiring of stop key 12 is shown including battery 28 and organ windchest 29. As stated hereinabove, stop key 12 can be manually positioned through the use of handle 25 or can be remotely positioned through the use of actuator 14. As shown in FIG. 2, actuator 14 is a typical electromagnetic latching relay which can alternately be positioned by current input to the respective poles 30 and 31. The input to actuator 14 is from the output drivers shown as part of the output interface module 17. A set signal input to the driver circuit coupled to pole 30 will set stop key 12, a clear signal to the circuit coupled to the pole 31 will clear stop key 12. Contact 26 of stop key 12 is coupled to a drive circuit shown as part of input interface module 15. The translation of the signal levels between stop key 12 and actuator 14 and the present invention system are conventional translation circuits and are used to adapt the logic levels of the present invention system to the electromagnetic or other voltage levels used within organ 10. The circuit shown as part of input interface module 15 and output interface module 17 are conventional level translating circuits,

other suitable circuits being well known to those persons having skill in in the art.

An understanding of input interface module 15 can be best seen by reference to FIG. 3. Input interface modules 15 permit the central processing unit 19 to access the state of all input signals from organ 10. The input interface module shown in FIG. 3 has 64 inputs which have been designated by the signal designations P0 P63. The signals from pistons 11 are grouped into eight bit bytes, the total of 64 signals being grouped into eight bytes which are input into a level translator circuit 32 such as shown in FIG. 2. The output signals from level translators 32 are'designated as MPXIN- 0-MPXIN63 and represent the translated inputs compatible with the logic levels of the remaining portions of input interface modules 15. The signals MPXIN- 0-MPXIN63 are input to conventional multiplexors 40. In order to properly select the output signals from multiplexer 40, interface input module address decoder 41 responds to address data transferred from central processing unit 19 and provides for a single bit to be output from multiplexors 40, the output signals being designated as MPXOUTO-MPXOUT7. The byte of data output from multiplexers 40 are amplified and inverted by conventional inverters 42, the data outputs being designated as NDOND7. The completion of the address decode function at address decoder 41 is output as signal M/S which is amplified and inverted as inverter 43 and output as signal ND/A.

As shown in FIG. 3, the signals MPXSELO-MPX- SEL2 and NM/S control the operation of multiplexors 40 while the signal M/S is the source for the signal ND/A. The signal ND/A signals central processing unit 19 that the operation to read a byte of input data to central processing unit 19 has been performed. Referring now to FIG. 4, a detailed logical schematic of input interface module address decoder 41 is shown. Since the addressing of the piston input line is to select one out of eight bits, three address bits designated as NMO-NM2 are utilized. The remaining address bits M3-Ml5 are decoded in any conventional manner and input to what is, in effect, a 14 bit AND gate designated by the reference numeral 45a, 45b and 450. The output of gate 45c is inverted at inverter 46 thereby producing signals M/S and NM/S. As can be seen in FIG. 4, the 14th bit is derived from signal C/S which the central processing unit 19 causes to go true when any memory operation is required. Decoding of the high order 13 address bits M3-Ml5 is performed by selection of either the true or complement form of each bit by appropriate decoding as shown.

Referring now to FIG. 5, a better understanding of the output interface modules can be best gained. By proper orientation of data, and through the use of lists of pointers to stop and coupler keys 12, central processing unit 19 may affect any single or combination of stop keys 12. Referring now to FIG. 5, the output signals from inverters 42 are gated to eight, eight bit latches, the output thereof being designated as LCUT- 0-LOUT63. Central processing unit 19 can temporarily store in latches 50 data representing the desired states of the various keys 12. Signals LOUTOLOUT63 are connected to output driving circuits 51a and 51b as shown in FIG. 2. As was explained in connection with FIG. 2, output driver 51a will set actuator 14 and therefore set stop key 12, circuit 51b resetting actuator 14 and therefore clearing the associate stop key 12.

In order to properly activate the appropriate stop coupler keys 12, output interface modules 52 address the appropriate eight bit latches thereby permitting the activation of appropriate actuators 14. The output interface module address decoder 52 must strobe data into the latches during a time when the data is stable. As soon as the data has been strobed into latches 50, signal ND/A as shown in FIG. is initiated to terminate the operation.

The operation of output interface module address decoder 52 can be best seen by reference to FIGS. 6 and 7 where address decoder 52 and the associated timing diagram are illustrated. The sixteen bit address field, i.e., M0Ml5, is used to generate the appropriate signals needed to operate output interface module 17. M0-M2 define eight binary states which are needed to enable eight bit latches 50. M0, M1 and M2 are input to decoder 55, the eight binary states being amplified at amplifier 56 to produce signals LCO-LC7. As can be seen from FIG. 5, signals LCO-LC7 are used as enable signals to latches 50. The remaining portion of address field, i.e., M3M15, and the negative complements thereof, are input to the effective AND gates 57a, 57b

and 570. Between memory operations from central processing unit 19, signals R/W and C/S are in the false or low state. One shot multivibrator 58 will be reset thereby having the effect of holding signal M/S in the low or false state and thereby disabling decoder 55 and allowing no clock pulses to reach latches 50. Signals C/S resets flip-flop 58 which outputs signal D/A.

An operation is initiated when central processing unit 19 provides an address field MO-MIS, data and raising signals C/S and R/W. At time T0 as shown in FIG. 7, signals C/S and R/W go to the high or true state, signal R/W triggering one shot multivibrator 60. At time tl, one shot multivibrator 60 times out triggering one shot multivibrator 58 which in turn initiates signal M/S and clocks the D/A flip-flop 59 at time [2. Signal ND/A, is the output of inverter 60 and will be sent by central processing unit 19 which in turn resets signals C/S and R/W at time 13. Once signals C/S and R/W are reset, i.e., following time t3. the data and address may or may not change, the states thereof depending on the next program instruction to be executed.

Read-only memory module 20 provides storage for all programs and supplementary data lists required by central processing unit 19. In a typical implementation, information is distributed over one or more read-only memory chips, the composite of the chips making up read-only memory 20. In a typical implementation, readonly memory 20 is made of up chips each holding 256 bytes of data as shown in FIG. 8. Any byte may be caused to appear on the data bus by applying the address field MO-M7 or the complement thereof, and the chip enable signal NROMEO-NROME7. Typical ROM chips 65 have output characteristics such that the output line will not be driven to either a high or low state when the chip 65 is not in an enabled state. As a result, the output lines from each ROM chips 65 may be joined in a common connection which provides for a simple multiplexing arrangement for sending data from the enabled chip 65 to the data buss drivers.

When the output lines from ROM chips 65 are coupled together in a floating, multiplexing scheme, to prevent a floating state from appearing on the data bus, signal M/S which is output from ROM address decoder 66 is in the low or false state. The low state of signal M/S will turn gate 67 off thereby disabling the data bus drivers. A typical implementation for ROM address decoder 66 is shown in FIG. 9. Address bits M8-Ml0 are input to decoder logic 70, the eight binary states of bits M8-M10 producing the eight output states in NROMEO-NROME7. The remaining bits Mll-Ml5, and the complements thereof, are input to gate 71 along with enabling signal C/S. The output of gate 75 is passed through inverter 76 to produce signal M/S. ROM address decoder 66 transforms the address signals into eight chip enables and signal M/S. Upon the loading of the address signals, and when signal C/S goes to the true state, signal M/S will go to the high state triggering one shot multivibrator 77. One shot multivibrator 77 establishes the access time for ROM chips 65 and upon timing out produces output signal ND/A from gate 78. Signal ND/A signals central processing unit 19 that the access of ROM memory 20 is complete.

Referring now to FIG. 10, an understanding of the random access memory module 21 utilized by central processing unit 19 can be best seen. In the embodiment of the present invention shown, random access memory module 21 can store up to 2,048 bytes of random access data used for the storage of stop combinations. As with the case of read-only memory module 20, random access memory 21 is comprised of RAM chips 80. A typical RAM chip 80 usable to implement random access memory module 21 is organized internally as 256 one bit storage locations. Where such chips 80 are used, eight chips operate in parallel to achieve storage and retrieval of bytes of data, each byte comprising eight bits of data. Each chip has a single data input and a single output data line. Eight address lines M0-M7 select one of the 256 locations to be written into or be read out of.

Chip enable signals, NRAMEO-NRAME7 provide for individual enable signals for each group of chips 80. When a chip enable signal is in the low or false condition, a read operation is selected. As in the case with the read-only memory chips 65, when a RAM chip 80 is not enabled the output is in a floating state. RAM address decoder 81 receives a portion of the address field, i.e., bits M8-Ml5, and control signals CIS and R/W. When neither a read or write operation is being performed, signal OUTEN disables gate 82 to prevent the data bus drivers from being in a floating state. As with the case of ROM address decoder 66, RAM ad dress decoder 81 produces signal ND/A to signal central processing unit 19 when the read/write operation is complete.

The operation of RAM address decoder 81 can be best understood by reference to FIGS. 11 and 12 wherein the logic and timing diagrams thereof are shown. The portion of the address field designated as bits M8-Ml0 are input to eight bit decoder 85. The eight binary states of address bits M8-M10 are decoded to the eight individual states NRAMEO-N- RAME7. The remaining bits of the address field, i.e., bits Mll-M15 and the complements thereof, are input to gate 86. The output of gate 86 is also input to decoder 85. Central processing unit 19 initiates a read operation by providing an address on lines M8M 15 and raises control signal C/S at time :0. During a read operation, signal R/W is in the low or false state, the high or true state of signal R/W being the write state. As stated, address bits M8-M10 are decoded thereby enabling one of the eight groups of RAM chips 80. Address bits M0-M7 select one of 256 bytes which will appear on the chipoutput line after the expiration of '9 chip access time. Since signal R/W is in the low state, the output of gate 87 will be signal OUTEN which will be in the high state and therefore enable the data bus drivers. When signal C/S is raised to the high state at 10 are designated as R[] to R[7]. On all pages, the R register 100 is designated as R[0] and constitutes the accumulatonThe accumulator R[0] is also referred to as the A register. The program counter 101 is desigtime t0, the output of gate 86 is inverted at inverter 88 nated as the P register and is two bytes wide and will and causes one shot multivibrator 89 to trigger. When always point to the next instruction to be executed, the the output of one shot multivibrator 89 times out, the instructions being stored in read-only memory module output of gate 90 will be signal ND/A which will signal 20. Memory address register 102 is designated as the M central processing unit 19 that the read operation has register and is two bytes wide and constitutes the been completed at time t2. As can be seen from FIG. source of the addresses for input interface modules 15, 12, the time t2, the data out of gate 82 will be valid and output interface modules 17 and all other modules. The therefore can be read on the data buss drivers. instruction register 103 is designated as the I register Central processing unit 19 writes a byte of data into and comprises one byte of data, I register 103 storing a RAM chip 80 by providing the byte of data at inverter the instruction being executed by central processing 91, address bits M0-M7 at inverter 92 and the remainunit 19 or the first byte of a multiple byte instruction. ing address bits at decoder 85 and gate 86. After pro- The N register 104, Z register 105 and C register 106 viding the address and data information, control signals all constitute one bit storage registers and are used for C/S and R/W are raised to the high state at time t0. special functions. N register 104 indicates a negative Raising signal R/W to the high state triggers one shot arithmetic result, Z register 105 indicates a zero arith- 93 which times out at time tl. Upon the timing out of metic result, and C register 106 indicates a carry funcone shot 93, one shot 94 is triggered at time tl. The tion. combination of one shot 93 and 94 produces output As indicated previously, R registers 100 are each two signal RAMR/W which will cause the data to be stored bytes wide. A necessity for a two byte register is dicin the appropriate location of RAM chips 80. As detated by the need to hold two byte addresses in the R scribed hereinabove, signal ND/A signals central proregisters 100 as pointers to various locations in input cessing unit 19 that the read/write operation for the and output modules 15 and 17 and in memory modules random access memory module 21 is complete. 20 and 21. In order to fill an R register 100, the transfer All functions performed by the present invention of data between central processing unit 19 and interorgan registration affecting system come about as a face modules 15 and 17 and memory modules 20 and result of central processing unit 19 executing programs 21 occur as a succession of two single byte transfers. W stored in read-only memory module 20. An underregister 107 assembles the two bytes received from standing of central processing unit 19 can be best memory modules 20 and 21 intoasingle operand. Also, gained by reference to FIG. 13 wherein a schematic, an operand is broken down into two bytes for transmislogic diagram of central processing unit 19 can be best sion to interface module 17 and memory module 21. seen. All program accessible registers are collectively Instructions are transferred from read only memory referred to as R registers 100. All R registers 100 are module 20 to central processing unit 19 on a byte by two bytes wide, i.e., 16 bits, and are organized into byte basis. pages of eight registers per page. At any point in time, Table 1 set forth hereinbelow, sets forth the instruconly the R registers 100 on a current data page are tion set which is executable by central processing unit accessible. For the purpose of example, the embodi- 19. Table 2 illustrates the instruction format for all ment of the present invention is considered to be orgainstructions shown in Table 1. Columns N, Z and C of nized into only two pages of data, it being obvious that Table 1 indicate when the corresponding result registhe number of R registers can easily be expanded. ter, i.e., registers 104, and 106, will be affected by R registers 100 on a page are numbered from 0-7 and execution of the respective instructions.

TABLE 1 CPU INSTRUCTION SET MNEMONIC FOR- PROCESS N z c MAT TYPE LA 1 A M[R[r]] LA2 l A M[R[r]]; next R[r] -R[r]+2 sA 1 M[ 1 A 8A2 l M[R[r]] A; next R[r] R[r]+2 AA 1 A A+M[R[r]] AA2 l A A+M[R[r]]; next R[r] R[r]+2 LRl 2 R[r] im ARI v 2 R[r]-R[r]+im 'LRD "3 R[m- M[d] SRD 3 M[d] B 1 P R[r] BLD 3 R[r] P; next P d CBR 4 (COND=l P -P+s CBD 3 (COND=l)- P d CNR 4 (COND=O) P +s CND 3 (COND=O) P -d AD 1 A -A+R[r] ADC 1 A -A+R[r}+C SB 1 A AR[r] SEC 1 A -AR[r]+C 1 AND 1 A -A A R[r] OR 1 A Av R[r] XOR 1 A A v R[r] CMPR 1 N02 AR[r] TABLE l-continued CPU INSTRUCTION SET MNEMONIC FOR- PROCESS N Z C MAT TYPE ADI l R[r] R[r]+l SUI l R[r] *"R[r]-l LD 1 A -R[r] ST 1 RH] SLL l A (-AXZ SRL l A A+2 OUT I DISCRETE OUTPUT[r] TABLE 2 INSTRUCTION FORMAT TYPE FORM l OP r 2 OP r im im 3 OP r d: d, 4 OP r s The process column of Table I indicates the data and control operation being carried out by the specific instructions. M[] indicates that the data comes from, or goes to, the memory location given by the address within the brackets. r is three bits in the first instruction byte specifying one of the current R registers 100 or is used for other purposes. Instructions LA2, SA2, and AA2 each provide for automatic stepping of a memory pointer. Note that the pointer is incremented by two to affect data transfers involving two bytes. im refers to two bytes of data immediately following the first instruction byte in read-only memory 20. d is an address (2 bytes) which follows the first instruction byte. COND is the logic as shown:

which is the condition on which the conditional branches are based. The term r[2] is the most significant bit of the R field. s is a short address, i.e., only one byte, and is used as a relative address. NEI Z specifies that the result of N register 104 and Z register 105 are to be set on values based on the result of the operation given to the write of the arrow. Instructions SLL and SRL are logical shift operations, i.e., the bits of the accumulator are shifted left or right with bits shifted out being lost and zeroes inserted into the opposite end of the register. The OUT instruction is a means for providing a pulse on the specified discrete output line, OUTO-OUT7. These lines can be used for a variety of purposes, in the preferred embodiment of the present invention, OUTO-OUT1 and OUT2 control the R register 100 page control hardware.

The hardware needed to implement central processing unit 19 can be best gained by reference to FIGS. 13 16. Referring now to FIG. 13, CPU control 110, A bus 111, B bus 112, C bus 113, D bus 114, E bus 115 and M bus 116 comprise the major control and data buss members of central processing unit 19. The other major elements of central processing unit 19 comprise registers 100, 101, 102, 103, 104, 105 and 106 which have been described hereinabove. Other major features of central processing unit 19 is the arithmetic and logic unit 117 and the shift register 118.

The logic details of CPU control unit 1 10 can be best seen by reference to FIG. 14. CPU control 110 provides all of the control signals for the remaining central processing unit hardware and creates the control signals R/W and C/S used in the operation of interface modules 15 and 17, read-only memory 20 and random access memory 21. The pertinent components of CPU control are step counter and the control read only memory 121. The count stored in step counter 120, the operand field of the current instruction, and the function defined as COND serve as an address to the control read-only memory 121. Each word read from control read-only memory 121 is decoded and activates various control signals. A sequence of words from the control read-only memory 121 will result in execution of the selected instruction.

The output terminals from step counter 120 are designated as QA, QB, QC and OD with output terminal QA representing the least significant bit. Oscillator 122 provides a continuous sequence of clock pulses to input CK. On the leading edge of a clock pulse emanating from oscillator 122, step counter 120 will be incremented by one, if the T and CLR input are high. The T input is a means for stopping step counter 120 during the time when central processing unit 19 is waiting for a D/A signal from interface modules 15 and 17, readonly memory 20 or random access memory 21. The circuit for implementing step counter 120 is conventional and known to those persons having skill in the computer art. When T is in the low state, the step counter 120 will be halted. A low state on input CLR will cause step counter 120 to be reset to zero on the next clock pulse eminating from oscillator 122 irrespective of the state of the signal at input P.

Signal designated as CC/S is output from control read-only memory 121. During that portion of instruction execution where a memory cycle is required, signal CC/S will be in the high state. Signal CC/S is inverted at inverter 12?: and input to gate 124. The output of inverter 123 is also gated through OR gate and causes the T input of step counter 120 to be in the low state since latch 126, which is, in effect, the D/A synchronizer, is normally in the reset state. As a result, step counter 120 is in a waiting condition. When signal D/A occurs, in its complemented form, signal ND/A goes to the low state, the output of gate 124 will go high and on the next clock pulse from oscillator 122, flipflop 126 will be set. As soon as flip-flop 126 goes to the set state, the output of gate 125 will go high permitting step counter 120 to commence counting. Step counter 120 will be incremented on the next clock pulse from oscillator 122. The next word read from control readonly memory 121 will have the signal CC/S in the low state. The T input of step counter 120 will now remain in the high state irrespective of the output of the D/A synchronizer 126. Subsequent to signal CC/S going to the low state, the signal D/A emanating from one of the this delay time, the power supply for the logic has an opportunity to stabilize and oscillator 122 commences operation. After the delay, signal PSEN goes to the high state and remains high until power is removed. All instructions being executed by central processing Flip-flop 127 will be reset after power is applied. The output from flip-flop 127, i.e., NCLEAR, will be in the low state and cause resetting of P register 101 (FIG. 13). The false output of flip-flop 127 will be in the high state and cause resetting of step counter 120. Central struction. During the last word read from control readprocessing unit 19 is now initialized and will commence execution after flip-flop 127 is set causing signal NCLEAR to go to the high state.

13 interface modules 15 or 17 or memory modules 20 or 21 will cause the signal to go to the low state. As soon as signal D/A goes to the low state, the output of gate 124 will go low and D/A synchronizer 126 will be reset.

unit 19 do not require the same number of procedural steps for execution. Signal CLRSTP emanating from control read-only memory 121 provides means to reset step counter 120 and begin execution of the next inonly memory 121 of the current instructions step sequence, signal CLRSTP will go to the high state forcing the CLR input to step counter 120 to the low state. On The remaining logic of CPU control constitutes the next clock pulse emanating from oscillator 122, conventional decoders 128, 129, 130, 131 and 132 and step counter will be reset and commence counting 15 the decoding logic associated therewith. Table 3 set again from zero.

from control read only memory 121 and the output signals shown along the right edge of FIG. 14.

TABLE 3 CPU CONTROL DECODING A BUS CONTROL SIGNALS PTOA MTOA WTOA forth hereinbelow sets forth the decoding of the output RTOA ROM 1 21 OUTPUT CA I CAO When power is first applied to the present invention organ registration affecting system, means are required LLLH LHLL

HLLL

LLHH

SIGNALS ROM l2l OUTPUT ALUOP HHLHLLLL HLHHHHLL HLHLHHLL HHLHHLLL .HLLHHHLL LLHHLLHH LLLLHHHH ROM 12] OUTPUT SIGNALS CW1 CW0 DTOWL DTOWM ETOW SGNEXT L O R T N O C Y R T N E W LLLH LLHL

LHLL

HLLH

LLHH

SETZ SETC OUT SIGNALS SETR SETP SETM SETl SETWL SETWM SETN CCO CCl

ROM l2l OUTPUT CC3 CC2 REGISTER CLOCKS AND OUTPUT ENABLES LLLLLLLLLLHLLLLL LLLLLLLLLHLLLLLL LLLLLLLHHHLLLLLL LLLLLLLHHHLLLLLL LLLLLHHLLLLLLLLL LLLLHLHLLLLLLLLL .LLLHLLLLLLLLLLLL LLHLLLLLLLLLLLLL LHLLLLLLLLLLLLLL HLLLLLLLHHLLLLLL LLHHLLHHLLHHLLHH LLLLHHHHLLLLHHHH .LLLLLLLLHHHHHHHH As stated previously six data buses are employed in the operation of central processing unit 19. Referring again to FlG. 13, A and B buses 111 and 112 respectwo registers to the arithmetic and logic unit 117. Entry of an operand onto A bus 111 is governed by control signals WTOA, MTOA, PTOA and RTOA. These were to initialize central processing unit 19 so that it commences execution of instructions at a particular location in memory, i.e., location zero. Signal PSEN and flip-flop 127 perform the reset function. Signal PSEN is 65 tively, are two bytes wide and transfer operands from a control signal derived from the power supply. Signal PSEN is derived in a conventional manner and is low for a few milliseconds after power is applied. During shown in Table 3 under A BUS CONTROL. B bus 112 is controlled by signal WTOB. It is to be noted that signals WTOA and WTOB give the entire sixteen bit W register 107 onto A bus 111 and B bus 112 respectively via gates 135 and 136. R register 100 is gated to A bus 111 via gate 180, the gate being enabled by signal RTOA. C bus 113 is one bit wide and is derived from flip-flop 106 and associated gates 137, 138 and 139. C bus 113 introduces a third operand into the arithmetic and logic unit 117 during specific operations, the third operand being either a carry being held in flip-flop 106 or a binary one. A byte of data arriving on D bus 114 from a interface module 15 or 17 from memory modules 20 or 21 is in inverted form, i.e., each bit is complemented, and can be gated to the most significant bit portion of W register 107 at gate 138 being enabled by signal DTOWM. The data can be gated to the least significant bit portion of W register 107 at gate 139 and using signal DTOWL.

As stated previously, one byte in the conditional branch instructions, i.e., the s field, is the relative address to the present contents of P register 101, the instruction branching to that address if a condition is satisfied. The relative address can be either positive or negative to allow forward or backward branching. The magnitude of the address will be restricted between 0 and 127. When the s byte arrives on D bus 114, it is expanded to two bytes by the control signals SGNEXT and DTOWL and gated into the sixteen bit W register 107. Signal DTOWL allows the s byte into the least significant half of W register 107. Signal SGNEXT enables gate 140. Signal SGNEXT and D7, the most significant bit of the s byte enters a byte of all zeroes, if the D7 is false, or the byte of all ones, if bit D7 is true, the byte being entered into the most significant half of W register 107. Bit D7 will be true when the s byte is negative in value.

E bus 115 transfers the results from shift register 118 to one of the registers 100, 101, 102, 103 or 107. Some registers only use a part of E bus 115, i.e., N register 104 and I register 103. Data on E buss 1 15 is available to registers 100, 101, 102, 103, 104 and 105 at all times. Entry into W register 107 from E bus 115 is under control of signal ETOW which enables gate 141 and 142 at a proper time so as not to interfere with D bus 1 14. M register 102 is two bytes wide, the output of M register appearing on M buss 116 as well as being gated to gate 143 and being enabled by signal MTOA. The use of bus 116 will be described in detail hereinbelow.

As stated previously P register 101 is the instruction counter. Incrementing of P register 101 is performed by gating the contents of P register 101 at gate 144 via enable signal PT 0A, the contents appearing on A bus 111 being gated to the arithmetic and logic unit 117. The incrementing one is introduced on C bus 113 and arithmetic and logic unit 117 demanded to add the contents of P register 101 and the binary one. The arithmetic result appearing in the arithmetic and logic unit 117 is transferred through shift register 118, on the E bus 115 and entered back into P register 101. When an instruction is to be fetched, the contents of the P register'101 are gated through the arithmetic and logic unit 117 and shift register 118 as described hereinabove and then transferred through M register 102 to bus 116 whereupon a memory read operation is commanded. As was discussed in connection with FIGS. 2, 6, 8, 9, 10 and 12, the data on M bus 116 constitutes the memory address which is used to select the appropriate memory location in interface modules 15 or 17 or in read-only memory 20 or random access memory 21. The details of P register 101 can be best seen by reference to FIG. 15 wherein a schematic logic diagram of the sixteen flip-flops represented by the reference numerals 101a, l0lb and 1010. The inputs to all of the flip-flops of P register 101 are derived from E bus 115, the signals appearing on the set inputs of flip-flops 101a, 101b and 101C being inverted through inverters 145a, 145b and 145C110 provide a complementary input to the reset input of the respective flip-flops. Information is stored in P register 101 from E bus 115 upon the trailing edge of signal SETP. As stated hereinabove, signal NCLEAR acts as a direct reset of all flip-flops 101a, 101b and 101C upon the initiation of power to the present invention system.

A better understanding of the operation and implementation of R registers 100 can be best seen by reference to FIG. 16. As stated hereinabove, the embodiment of the present invention disclosed herein utilizes two pages of data. FIG. 16 illustrates two R register pages. Page 0 is represented in the upper half of FIG. 16, page 1 being represented by the lower portion of FIG. 16. It is to be noted that only a single R[0] is used. A conventional up/down binary counter is provided for keeping track of the current R page. Up/down counter 150 comprises a single flip-flop since only two pages of data are represented in the present embodiment. Counter 150 would comprise additional storage elements where additional pages of data are required. Counter 150 has three inputs to implement the functions of countdown, countup and clear. The input signals to counter 150 are OUTO, OUTI and OUT2, the signals being shown in FIG. 14. On the leading edge of a pulse from the signal OUTl, counter 150 is decremented by one; the signal OUT2 causes counter 150 to be incremented by one; the signal OUTO resets counter 150 to zero.

When counter 150 holds a value of zero, the output thereof will provide an enable signal to decoder 152 which provides eight binary output signals for the three coded input signals collectively referred to as a r. When control signal SELr goes true, decoder 152 is enabled and proceeds to decode the r field into one of the eight output signals. The one true output from decoder 152 enables an AND gate such as gate 153. In this case, the contents of the R register 100 designated as R[l] are enabled, signal being enabled through gates 153, 154 and '155. If, during the time SELr is true, the signal SETR is pulsed, information on E bus 115 would be stored in R[l] since decoder 151 is enabled. In a like.

manner, each of the registers R[0]-R[7] may be gated to the output of gate 155 and loaded from E bus 115.

When counter 150 has a value of one, decoder 151 is disabled and decoder 156 enabled. As a result, the

registers R[0]-R[7] are active. It is to be noted that;

register R[0] for page 1 is the same for page 0 through the use of OR gates 157 and 158. When signal SELr is in the low state, all decoders 151, 152, 156 and 159 are disabled. Inverter 160 enables gates 161 and 162 with a high level thereby enabling the A register, i.e., R[0] to be read from or stored into. When gate 162 is enabled, register R[0] can be read as the output of gate 155 and be loaded from E bus 115 by signal SETR. Gate 163 operates with register R[7] in the same manner as gate 153 operates with register R[l]. Registers 164 and 165 operate with the register of page I, gate 17 164 gating the output of register Rll], gate 165 gating the output of register R[7]. OR gate 166 gates the output of the page 1 registers to gate 155.

M registers 102, I register 103 and the W register 107 are similar to P register 101 in construction and operation. Information in the one byte I register 103 is broken down into several fields designated as OP, r, r(O), r(l) and r(2). The five most significant bits are the OP field and are transmitted to CPU control 110. The remaining three bits are the r field and are sent as a unit to CPU control 110, shift register 118 and R registers 100. Individually, the r bits are used to form the signal COND which is the output of gate 167. Gates 168, 169 and 170 are the terminus of bits r(), r(l) and r(2) respectively. As was stated previously, the two halves of W register 107 can be loaded individually or simultaneously. Each half of register 107 can be gated on to D bus 114 or the entire W register 107 can be gated onto A bus 111.

The arithmetic logic unit 117 can perform two arithmetic operations and four logic operations on two sixteen bit operands. As shown in FIG. 13, the arithmetic logic unit 117 has three operand inputs A and B viaA bus 111 and B bus 112 respectively, and via C bus 113, and operation on the five bit OP field. The resulting output S is input to shift register 1 18. During arithmetic operations, a carry-in may be introduced from C register 106 on C bus 113. The carry-out from arithmetic logic unit 117 will be coupled directly to C register 106 and the input of the complementary inverter 171.

The two arithmetic operations which can be carried out by arithmetic logic unit 117 are add and subtract functions. In either case, no account is taken of a sign bit, the operands being considered to be in the absolute range of 0 to (2 1). Arithmetic logic unit 117 includes a conventional binary adder and follows the conventional principals of binary addition. In the special case of incrementing an operand by one, a zero is entered at the Binput, and a one is entered into the CO input. The arithmetic logic unit 117 performs the subtract operation by forrning the one s complement of the B operand and then performs an addition with that which is on A bus 111. Normal subtraction can be achieved by introducing a one into input C0 along with the A and B operands. Any carry or borrow which is acquired during the addition or subtraction operation is indicated by the output appearing at terminal C16 which goes to a false level during the operation.

The four logical operations are designated as PASS, OR, AND and EXCLUSIVE OR. PASS is simply the 18 gating of the A operand through to the S output, i.e., to shift register 118. OR, AND and EXCLUSIVE OR are conventional logic operations which are performed on a bit by bit basis utilizing the inputs from A bus 111 and B bus 112.

Shift register 118 is sixteen bits in length and holds a sixteen bit operand. Upon operation of the shift regis ter, the output thereof constitutes a sixteen bit shifted copy of the operand. Bits in the original operand which are shifted past either the most significant or least significant bit positions are lost, zeroes filling any vacated positions. A shift operation toward the most significant end of the register is indicated by the signal SHFL, the field r specifying the magnitude of the shift. A shift right is designated by the signal SHFR, the r field designating the magnitude of the shift. If neither signal SI-IFL or SHFR is raised to the true state, the input operand is gated unchanged to the output thereof and onto E bus 115.

C register 106 receives the output from arithmetic logic unit 1 17 via the output terminal C16 of arithmetic logic unit 117. This enables the central processing unit 19 to detect overflows which occur through a conditional branch on the contents of C register 106. In addition, C register 106 stores the carry/borrow function which occurs between cycles of a programmed multiple precision add/subtract. N register 104 is clocked by signal SETN, the set input thereof being coupled to E bus 115, the reset input to N register 104 being coupled through inverter 172 to E bus 115. N register 104 will receive the value of the most significant bit of E bus 115. Z register will be set to one during certain instructions if the contents of E bus 1 15 are all zero. Register 105 is a single flip-flop which is set by the output of gate 173 and reset through inverter 174. Inverter 175 schematically depicts sixteen inverters which are each receiving inputs from one of the sixteen lines of E bus 115. The output of all inverters 175 are anded at gate 173 to implement the function of Z register 105. Therefore, only when E bus 115 contains all zeroes, will register Z register 105 indicate the true state. As stated previously, the outputs from C register 106, N register 104 and Z register 105 are respectively input through gates 168, 169 and 170. The outputs thereof are logically ored at gate 167, the output of gate 167 comprising the signal COND. Signal COND is examined by CPU control during conditional branch instructions to determine whether a branch operation is called for.

TABLE 4 INSTRUCTION EXECUTION STEP R A B C ALUOP SHIFT WIN WTOD REGISTER STORAGE STEP CON- BUS BUS BUS CONTROL CONTROL CONTROL CLOCKS CONTROL CONTROL TROL GATE GATE GATE 0 PTOA F=A SETM 1 DTOWL SETWL,M' C/S WAIT 2 WTOA F=A SETI 3 PTOA lTOC F=A+B+C SETP 4 SELr. RTOA F=A SETM 5 DTOWL SETWL C/S WAIT 6 MTOA lTOC F=A+B+C SETM 7 DTOWM SETWM C/S WAIT 8 WTOA F=A SETN,Z.R CLRSTP 4 SELr RTOA F=A SETM 5 DTOWL SETWL C/S WAIT

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Classifications
U.S. Classification84/345, 984/12, 984/340
International ClassificationG10H1/24, G10B3/00, G10B3/10
Cooperative ClassificationG10B3/10, G10H1/24
European ClassificationG10B3/10, G10H1/24