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Publication numberUS3928849 A
Publication typeGrant
Publication dateDec 23, 1975
Filing dateDec 17, 1974
Priority dateDec 17, 1974
Also published asDE2556864A1
Publication numberUS 3928849 A, US 3928849A, US-A-3928849, US3928849 A, US3928849A
InventorsFrank Schwarz
Original AssigneeUs Energy
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Intrusion detector self-test system
US 3928849 A
Abstract
An intrusion detection system which automatically makes periodic tests of the operability of the system and provides an alarm in the event of a malfunction during the supervisory self-check regimen which alarm is distinguishable from the normal intrusion alarm.
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United States Patent Schwarz 5] Dec. 23, 1975 INTRUSION DETECTOR SELF-TEST 3.64L549 2/1972 Misck et al 340/258 8 SYSIEM 3.717.864 2/1973 Cook et al. 340/253 D [75] inventor: Frank Schwarz, Stamford, Conn.

Primary Examiner-Thomas B. Habecker [73] Asslgnee' :gg g g fig fi gm a g Assistant Examiner-James J. Groody Energy Ru 3 :h and Development Attorney, Agent, or Firm-Dean E. Carlson; John A. Administration, Washington, DC. Koch [22] Filed: Dec. 17, 1974 [21] Appi. No.: 533,741 [57] ABSTRACT [52] US. Cl H 340/410. 250/221. 340/258 D An intrusion detection system which automatically i hm 6 29/00 makes periodic tests of the operability of the system [58] Field of 411 214 and provides an alarm in the event of a malfunction 340/276 255 258 6 6 during the supervisory self-check regimen which alarm is distinguishable from the normal intrusion alan'n.

[56] References Cited UNITED STATES PATENTS 0mm 2 Drawmg gums 3553.664 l/l97l Tucker 340/4l0 I 76 E 7'0 74 2 A I 6 BC Oi I 20 3O 38 1 73 22 3 Alarm 2'! Integrator I F 84 C l8 M 42 E l 43 26 D 54 |7 L integrator I6 t J l 1: 77 52 A H A Belay Integrator A 5| Gl 22 Clock INTRUSlON DETECTOR SELF-TEST SYSTEM The invention described herein was made in the course of or under a subcontract under Contract AT(26-1)-4l0 with the US. Atomic Energy Commission.

BACKGROUND OF THE INVENTION This invention relates to intrusion detector systems and more particularly to an intrusion detector system which automatically makes periodic tests of the operability of the system.

Numerous situations occur where it is desirable to safeguard an area by monitoring entry therein without the immediate physical presence of a human guard. A number of intrusion detector systems employing electronic components and circuitry which detect the presence of an intruder and provide an alarm in response thereto have been devised to meet this need.

Since malfunctions of electronic components and circuitry can never be completely ruled out and such malfunctions can occur at unpredictable times and circumstances, it is essential that the integrity and operability of an intrusion detector system be subjected to periodic testing.

SUMMARY OF THE INVENTION Accordingly, it-an object of this invention to provide an improved intrusion detector system. It is a further object of the invention to provide an intrusion detection system which incorporates the capability for auto matically testing the operability and integrity of the system. It is an additional object of the invention to provide an intrusion detection system which automatically activates the detector mechanism in order that the operability of the system be periodically tested. It is an even further object of the invention to provide an intrusion detection system which periodically automatically simulates an intrusion but which prevents an alarm signal from being given in response to the simulated intrusion unless a defect or malfunction is present in the system in order to provide a supervisory self-check of the system.

Briefly stated, the above and additional objects are accomplished by periodically developing a plurality of signals by a clock means, one of which initiates a simulated intrusion in order to activate the detector operated circuit, a second of which is a signal of opposite state to the intrusion signal output of the detector operated circuit and a third of which is a delay signal of shorter duration than the other two. The three signals initiated by the clock means are combined along with the output signal from the detector operated circuit as inputs to a combination of logic gates in order to provide alarm signals in response to an actual intrusion and in response to a malfunctioning of the system during the periodic supervisory self-check sequence and, conversely, a prevention of any alarm signal in response to the simulated intrusion of the self-check sequence in the event the system is operating normally in all respects.

The above-mentioned and additional objects and advantages of the invention and a further understand- BRIEF DESCRIPTION OF THE DRAWlNGS FIG. 1 is a diagrammatic representation of an intrusion detection circuit utilizing a preferred embodiment of the invention, and

FIG. 2 is a representation of electrical signals devel' oped at various points in the circuit of FIG. 1.

DESCRIPTION OF PREFERRED EMBODIMENT Referring now to the two figures of the drawing, the various components of intrusion detector circuit 10 illustrated in FIG. 1 and the signals produced at various points of the circuit illustrated in FIG. 2 will be explained in conjunction with their function, first, in response to an actual intrusion and, then, in response to a simulated intrusion initiated by the supervisory self check feature of the system.

Detector operated circuit 12 is so constituted in a manner to be further described hereinafter as to produce an output E at point 13 which is at either one of two possible switching states. Those skilled in the logic switching art will appreciate that a great deal of latitude is possible in the selection of particular values for binary switching states, depending in large degree on the particular components selected to perform the gate functions. Although the preferred embodiment will be described in terms of positive logic where one switching state is at maximum positive voltage (hereinafter abbreviated as MV and representative of a l in binary logic) and the opposite switching state is at 0 volts, many other combinations are, of course, possible.

Assuming nonnal circuit operation, the output of detector operated circuit 12 at point 13 is at MV in response to a non-intrusion condition and at zero in response to an intrusion condition. A zero state at input 14 of NAND gate 15 produces an MV output at 16 regardless of the state of the input at 17. Accordingly, it can be seen that assuming the absence of an MV state at point 18, the conditions governing the occurrence of which will be described hereinafter a zero state at point 13 in response to the activation of detector 20 will produce an MV alarm signal at output 16 of gate 15.

Before proceeding into the description of the supervisory self-check feature of the invention, it will be helpful to gain a rudimental understanding of the operation of the particular detector operated circuit 12 illustrated in FIG. 1. Of course, as will become apparent hereinafter, the actual requirements of detector operated circuit 12 insofar as its satisfactory use with the invention is concerned are that it produces an output E at 13 of one switching state in response to a nonactivated condition of detector 20 and an output of a second state in response to activation of detector 20 in response to either a real or a simulated intrusion, and that detector 20 can be activated in response to some phenomenon which is initiated by clock means 22 in order to simulate an intrusion.

In the particular detector operated circuit 12 illustrated in FIG. I, detector 20 is a passive, therrnopile type such as that described in my US. Pat. No. 3,760,399 issued Sept. 18, 1973 to Barnes Engineering Company as my assignee. As described in that patent, an object moving across the field of view of the thennopile-produces an output 26 of changing polarity as illustrated in waveform B of FIG. 2. The output 26 is applied to preamplifier 27, having one or more stages, and the positive going portions 28 of the alternating 3 positive-and-negative-going signals 28 and 29, are compared against a positive reference, +R, by comparator and the negative portions 29 compared against a negative reference, -R, by comparator 31. When the +R or R references are exceeded, the respective comparator 30 or 31 switches state to provide a pulse which is stretched by the respective integrator 34 or 35 to provide an MV output pulse 36 or 37 of waveforms C or D of selected time duration at 38 or 39. When positive and negative pulses 28 and 29 of waveform B are both present and of sufficient magnitude and in appropriate time sequence as would be characteristic of an activation of detector 20, portions of the MV pulses 36 and 37 of waveforms C and D would be applied to inputs 42 and 43 of NAND gate 44 during the same time interval, as shown in FIG. 2. Simuitaneous MV inputs to NAND gate 44 would, of course, be the only combination to cause a zero output at 13. As previously described, a zero state at input 14 of NAND gate 15 would produce the MV alarm signal at 16 which is the intruder alarm pulse 45 of waveform F.

Proceeding now to the supervisory self-check feature of the invention as embodied in the circuit of FIG. I, an MV pulse 47 of waveform Aof FIG. 2 is periodically generated by clock operated means 22. In one detector circuit embodying the invention, an astable multivibrator having a repetition rate of about once every half hour was the heart of clock means 22. However, particular clock means for particular applications will come readily to the thought of those skilled in the art. While the time periods indicated on HO. 2 are those actually produced in the particular circuit and are provided as a matter of reference, many other combinations would be completely satisfactory for other applications of the invention.

The MV pulse 47 is utilized to develop a number of signals utilized by the circuit and is, accordingly, passed in three directions at junction 48. As the first of these, pulse 47 is A-C coupled through capacitor 51 to light emitting diode 52 to causethe radiation of light, including infrared, therefrom which is seen by detector 20 as an intrusion. Other sources of infrared radiation, such as a light bulb, would, of course, be satisfactory. Receipt of the radiation from LED 52 by detector 20 causes detector operated circuit 12 to respond in the same manner as if an actual intrusion had occurred thereby resulting in a zero output at 13 as previously described.

MV pulse 47 of waveform A is also applied to input 14 of gate 15 through junction 18. The MV pulse 47 at junction 18 would, of course, override the zero pulse 53 of waveform E thereby making input 14 of gate 15 to be at the same state as it would be under normal, non-intrusion circuit operation, i.e., detector 20 in the inactivated condition. The voltage at junction 13 will continue to be determined by the state of gate 44, resistor 54 providing isolation between junctions l3 and 18.

A third application of waveform A is made through delay and integrator circuits 57 and 58, respectively, to produce the shortened, delayed MV pulse 59 of waveform A. Waveform A is applied as one input 61 to NAND gate 60 and waveform E as the other input 62. Referring now to FIG. 2, it will be seen through a comparison of wavefonns A and E that under normal operation of circuit 10 in response to the initiation of the self-check cycle, as heretofore described, signal G will ilways be at MV. Under such normal operation of the 4 circuit, there would be no occasion when waveforms E and A would both be at MV in order to cause NAND gate 60 to change state and switch output 63 from MV to zero.

Since waveform G is one input into the alarm gate. NAND gate 15, and since waveform G is at MV provided that the circuit is operating normally without malfunction. the signal F at output 16 will normally be the MV alarm signal on all occasions other than when input 14 is at MV. As previously described, input 14 is at MV under (1) normal circuit operation, non-intrusion conditions and (2) normal circuit operation under the supervisory self-check regimen due to the application of waveform A to junction 18. However, if during the supervisory self-check sequence the output of detector operated circuit 12 at junction 13 should fail to drop from MV to zero for any reason such as, for example, the failure of detector 20, the failure of LED 52, etc. an MV alarm signal would be produced at 16 due to the following.

The failure of point 13 to drop to zero during the supervisory self-check regimen would result in a simultaneous application of MV at input gates 61 and 62 of NAND gate 60 during the production of shortened MV pulse 59 of waveform A. This would cause NAND gate 60 to change state and drop output 63 from MV to zero during the period of pulse 59 of waveform A. Accordingly, zero pulse 64 of the same period of time as pulse 59 would be developed in waveform G, the output 63 of gate 60. The input of zero pulse 64 at 17 coupled with an MV input at 14 the latter due to application of waveform A at 18 as previously explained would result in NAND gate 15 providing an alarm signal, i.e., MV pulse 65 shown in dotted, slightly shortened form in waveform F of FIG. 2, at 16 simultaneously with the development of pulses 59 and 64. Since pulse 65 is of shorter interval than intruder alarm pulse 45 and occurs on a cyclical basis, a malfunction of the circuit which causes a failure of output 13 of detector operated circuit 12 to drop to zero during the supervisory self-check sequence would be readily distinguishable from the usual intruder alarm. This self-check fault alarm would reoccur with each cycle ofclock means 22 until the malfunction was corrected.

While the supervisory circuit thus far described would provide an alarm signal for the most probable malfunctions, it is conceivable that a malfunction in the line producing waveform A could result in a permanent hang-up of junction 18 at MV. Malfunctions of that character would always block an intruder signal and would not be detected by the circuit described up to this point. This could happen in a number of ways. There will in all probability berseveral buffer and inverter stages in the line producing waveform A and a failure of these in the MV position would block junction 18. In addition, any failure of a multivibrator of clock means 22 in the MV position would deactivate both the intrusion signal and the supervisory self-check circuit described up to this point and would not be detected.

The provision of NOR gate and OR gate 71 preserves the ability of the circuit to provide an alarm in the event of an actual intrusion regardless ofa malfunction of that type. NOR gate 70 provides an essentially redundant path for actual intrusion signals around alarm gate 15. The MV alarm signal at output 74 of NOR gate 70 would only occur upon the simultaneous occasion of zero inputs at 72 and 73. As previously described, the E waveform. which is applied to input 72, would be zero in response to the activation of detector by either an actual or simulated intrusion. Due to the AC coupling of clock signal A through junction 77 and capacitor 76 which is seen as waveform A" at input 72 of gate 70, the only occasion which would not produce a zero input at 73, and therefore an MV alarm signal at output 74, in the event of the activation of detector 20 would be the application of an MV pulse to capacitor 76. An absence of an MV pulse due to hang-up of waveform A at steady MV, or any other voltage for that matter, would not provide the MV input to 73 which would be necessary to prevent the zero intrusion signal of waveform E at 72 from being converted into the MV alarm signal by NOR gate 70. However. the intrusion signal would not be converted into an alarm signal when it is due to the simulated intrusion of the supervisory self-check feature and the normal pulse 47 of waveform A is, in fact, seen at junction 77 and converted into positive pulse 81 of waveform A".

The RC time constant ofthe capacitor 76-resistor 80 combination is selected to provide pulse 81 of waveform A" at a sufficiently high voltage for a length of time which will prevent the NOR gate 70 from chang ing state during the supervisory self-check sequence, i.e., during the period of pulse 53 of waveform E.

Since OR gate 71 will provide an MV alarm signal at output 84 upon receipt of an MV signal at either (or both) inputs 85 and 86, two simultaneous malfunctions, one in the main intrusion signal channel and one in the supervision circuit, would be necessary to render the circuit unresponsive to an actual intrusion without warning. it will be appreciated that the malfunction of clock 22 could readily be periodically monitored through, as an example, producing and periodically reviewing a recording of the clock output. Moreover,

the usual installation of an intrusiondetector system would employ a plurality of detectors 20, and therefore of circuits 10, providing a redundancy which would reduce the probability of an actual intrusion going undetected to an extremely small value.

While the foregoing describes the fundamental novel features of the invention as applied to a preferred embodiment, it will be understood that various omissions, substitutions and/or changes may be made by those skilled in the art within the principle and scope of the invention as expressed in the appended claims.

What I claim is:

1. In an intrusion alarm system the combination comprising:

A. Detector operated means for providing an output signal of the first of two switching states under normal circuit operation nonintrusion conditions and an output signal of the second of said states in response to activation of the detector,

B. Clock operated means for periodically providing (l) a first signal for simulating an intrusion, (2) a second signal for overriding said signal of said sec ond state from said detector operated means, and (3) a third signal,

C. First gate means operatively connected for receiving the output signal of said detector operated means and said third signal from said clock means for providing an output of a first of two states in response to either a normal condition, an intrusion. or a simulated intrusion and an output of the second of two states in response to a malfunction, and

D. A second gate means operatively connected for receiving the outputs of said first gate, said detector operated means and said override signal for providing an output of a first of two states in response to either a normal condition or a simulated intrusion condition with normal circuit response thereto and of the second state in response to an actual intrusion or a simulated intrusion coupled with a malfunction.

2. The intrusion alarm system of claim 1 including means for providing a redundant path for the output of said detector operated means.

3. The system of claim 2 wherein said means for providing a redundant path includes a third gate means operatively connected for receiving the output signal of said detector operated means and a signal in response to said second signal of said clock means for producing an output of a first state in response to an actual intrusion.

4. The system of claim 3 wherein said first and second gates are NAND gates and said third gate is a NOR gate.

5. The intrusion alarm system of claim I wherein the detector of said detector operated means is of a passive type responsive to infrared radiation and said first signal of said clock operated means activates a source of infrared radiation.

' The system of claim 5 wherein said source of radiation'is a light emitting-diode.

7. The intrusion alarm system of claim 1 wherein said first and second gates are NAND gates.

8. The intrusion alarm system of claim 7 wherein said first state of said detector operated means is a logical 1, said first, second and third signals of said clock means are logical l's, said first state of the output of said first gate is a logical l and said first state of the output of said second gate is a logical 0.

9. The system of claim 4 wherein said first state of said detector operated means is a logical 1, said first second and third signals of said clock means are logical ls, said first state of the output of said first gate is a logical 1, said first state of the output of said second gate is a logical 0, and the first state of the output of said third gate is a logical 1.

10. The system of claim 9 including an OR gate as a fourth gate operatively connected to receive the outputs of said second and said third gate.

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Classifications
U.S. Classification340/515, 340/567, 250/221, 250/DIG.100, 340/516
International ClassificationG08B13/183, G08B29/12, G08B29/14, G08B13/00
Cooperative ClassificationY10S250/01, G08B29/14, G08B29/123, G08B13/183
European ClassificationG08B29/14, G08B13/183, G08B29/12A