|Publication number||US3929338 A|
|Publication date||Dec 30, 1975|
|Filing date||Dec 26, 1973|
|Priority date||Dec 27, 1972|
|Also published as||DE2263570A1|
|Publication number||US 3929338 A, US 3929338A, US-A-3929338, US3929338 A, US3929338A|
|Inventors||Juergen Peter Busch|
|Original Assignee||Nsm Apparatebau Gmbh Kg|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (2), Referenced by (48), Classifications (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
United States Patent Busch 1 1 Dec. 30, 1975 [5 GAMING APPARATUS 3,772,874 11 /1973 Lefkowitz 350 160 LC  Inventor: Juergen Peter Busch, Bingen,
Germany Primary ExaminerStanley H. Tollberg  Assign: NSM Apparatebau Gmb" $112152): l:sgent, or Firm-Wolfgang G. Fasse; W1llard Kommanditgesellschaft, Bingen (Rhine), Germany 221 Filed: Dec. 26, 1973 AC [2|] Appl. No.: 428,345 An apparatus of the type having a display panel with game feature can'iers and other indicating devices is provided in which the display panel is formed as a liq-  Foreign Appl'cflmn Priomy Data uid crystal display. Circuit means are provided for se- DCC. 27, [972 Germany 2263570 lecfiygly onnling the elements of the crystal display so that three modes of control are employed,  U.S. Cl; 273/138 the display being difl nt in each f the three modes l Ill. Cl- In one d: certain f the devices are conllnof Search uously sequentially operated and in a second mod a 350/160 12 random control of certain display devices is provided, 1 the last occurring indication in the second mode being 1 Relel'fl'lcts Cited held in the third mode of operation. 4
UNITED STATES PATENTS 3,731,986 5 1973 Fegason 252 4011 LC 6 4 0mm:
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a. EMORY US. Patent Dec. 30, 1975 Sheet 3 of3 3,929,338
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COMPUTER DECODER I OUT COUNTER GAMING APPARATUS BACKGROUND OF THE INVENTION This invention relates to an indication system for an apparatus of the type having game feature carriers, as well as other indicating arrangements, and is particularly directed to the provision of a system of this type in which the display enhances the desire of an individual to use the apparatus. The invention additionally relates to circuit arrangements for controlling the display systern.
In prior art devices of this type, game feature carriers were provided in the form of disks or rollers for displaying the game feature symbols. The game feature carricrs were driven by an electric motor by way of friction clutches, and a braking action was applied to the game feature carriers by mechanical means, or by electromechanical means including magnets. In order to ascertain a winning in the device, for example, the winning of free games, sensing means were provided for sensing the positions of the individual game feature carriers. The sensing means in turn were arranged to cooperate with mechanical sensing levers. The apparatus frequently employed a winning" matrix in the form of nine windows arranged in the matrix form of three rows and three columns of windows. These windows were illuminated in response to the progress of a plurality of games played on the apparatus, the illumination being effected by means of glow bulbs. The pattern of illumination of windows provided an indication of the opportunity for greater or lesser winnings in the apparatus. In the prior art arrangements, it was necessary for the bulbs to be repeatedly switched on and off. Consequently, it was necessary to replace the bulbs frequently.
Such apparatus also frequently employed other indicating devices, such as a special game counter, in the form of either a register or roller counter or an indicator counter. These arrangements necessitated the use of-expensive and complicated mechanical control devices.
In apparatus of this type, the impetus to use the apparatus has been found to be dependent to a large extent upon the outer appearance of the apparatus, and especially on the illumination of the apparatus and the various indicating devices provided thereon. All of the above described indicating arrangements of prior apparatus were relatively large in size and required extensive mechanical control arrangements. Consequently, the prior art arrangements were subject to frequent failure in use.
OBJECTS OF THE INVENTION In view ofthe foregoing, it is the aim of the invention to achieve the following objects singly or in combination:
to provide an apparatus of the above described type which is economical to produce, and in which the probability of breakdown is minimized;
to provide an apparatus of the above described type having game feature carriers and other indicating arrangements which are not mechanically operated;
to provide an apparatus of the above described type in which the various display means on the display panel are in the form of liquid cyrstal display devices; and
2 to provide a circuit arrangement for controlling the game feature carriers and other indicating devices, wherein the indicating devices are in the form of liquid crystal display means.
SUMMARY OF THE INVENTION In accordance with the invention, an apparatus is provided in which various indications, such as winning symbols, loss symbols, a winning matrix and a special game counter, as well as the display of features providing an impetus for using the apparatus are all displayed by means of liquid crystal display devices. In order to increase the incentives for a player to use the apparatus, the display of symbols representing winning and losing is present when the apparatus is not in use, or is only partially in use, in order to attract the attention or curiosity of prospective players. In order to further enhance the attraction features of the apparatus, the individual liquid crystal displays are preferably arranged so that the display of different colors is provided.
The arrangement in accordance with the invention provides the advantage that it enables the possibility of employing relatively simple control means for controlling the liquid crystal displays. The color displays may easily be changed by changing color filters. In addition, liquid crystal displays are especially adaptable to production of integrated display panels, so that the entire display panel may be formed as a single unit. Liquid crystal displays in accordance with the invention are substantially failure-proof, and the costs of producing such displays are relatively low.
In accordance with a preferred embodiment of a circuit arrangement in accordance with the invention for controlling a liquid crystal display, a clock generator is provided for controlling a logic circuit as well as a signal transformer. The logic circuit is connected to a winning" combination means, which in turn is connected to a random number generator. The control means is further connected to a memory, the memory being in turn connected to a display or indicator field. The indicator field is connected to the signal transformer, which in turn is connected to a counter and the winnings matrix.
BRIEF FIGURE DESCRIPTION In order that the invention may be more clearly understood, it will be described, by way of example, with reference to the accompanying drawings, wherein:
FIG. I is a block diagram of a display system in ac cordance with one embodiment of the invention;
FIG. 2 is a circuit diagram illustrating in greater detail the circuits of the counters, memories, the indicator field and the control circuit means of the arrangement of FIG. I;
FIG. 3 is a circuit diagram of a circuit for controlling the coin counter indication and the special game indication of FIG. 1; and
FIG. 4 is a circuit diagram of the arrangement for the indication of the winnings matrix of the arrangement of FIG. 1.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS The game sequence of an apparatus in accordance with the invention, may comprise the following modes of operation:
A. Stand-by mode. This mode corresponds to the time that the apparatus is switched on and is in stand-by operation, but no individual is actually operating the apparatus, nor is the apparatus in the process of ascertaining the results of a game. The apparatus is consequently ready for playing of a game at this time.
B. Playing mode. This mode corresponds to the time at which the apparatus is actually being operated by an individual, and during which time the individual game feature carriers are providing a rotating indication.
C. Stationary indication mode. This mode corresponds to the time following a playing mode, when the game feature carriers are not providing a rotating indi cation. During this mode of operation, the winning or loss is ascertained.
Referring now to the block diagram of FIG. 1, a clock pulse generator 1 is provided, which is operative in all of the three modes of operation above described. The output of the clock generator is connected to a control logic circuit 2 and a signal transformer 3. A display panel 6 is provided having a plurality of individual game feature carriers 5. The control logic circuit 2 is connected to a memory circuit 4 which insures that during the standby mode of operation determined loss or winnings symbols are displayed on the game feature carriers. At this time a control signal is also supplied to a picture display 7 on the display panel 6, the picture display 7 serving, for example, as an advertising display. The game feature carriers 5 and the picture display 7 are controlled from the logic circuit 2 by means of the signals I to P.,, as indicated in FIG. 1, a multiplex control arrangement being employed for this purpose. In addition, during the stand-by mode A the counter or computer 8 controls a numerical display 9 on the display panel by way of the signal transformer 3. A numerical display 11 on the display panel is controlled at this time by means of a special game counter 10. If the counter 8 is switched over to the storage function of the winning matrix 12, the display 13 of the winning matrix 12 is controlled, rather than the special game display 11.
During the playing mode B, the clock generator 1 controls a winning combination circuit 14 by way of the logic circuit 2. The winning combination circuit 14 at this time supplies a continuously repeated signal to the memory 4. These signals comprise decoded outputs and are coupled from the memory 4 to the loss and winning symbols of the game feature carriers 5 so that these symbols are sequentially illuminated in a continuous cycle of operation during the playing mode.
As indicated in FIG. 1, the control logic circuit 2 supplies the signals DC,-Stop to DC -Stop to the winning combination circuit. These signals cooperate with signals from a random number generator 15 and effect the storage of a bit combination in the memory circuit 4. This bit combination is decoded and controls the winning or loss indication 5.1 to 5.4 corresponding to the signals DC,-Stop to DC -Stop. This display is provided on the game feature carriers 5. Subsequently, these indications of the individually controlled symbols on the game feature carriers remain continuously illuminated. The indication of the individual game feature carriers, however, occur sequentially. The picture display 7 is not controlled during the playing mode of operation. The numerical display 9 controlled by the counter 8 and the numerical display 11, controlled by the special game counter 10, remain controllable during the playing mode B in the same manner as during the stand-by mode A. In other words, if a change occurs in the counter 8 or in the special game counter 10, such a change will be applied to control the corre sponding numerical displays 9 and 11. Alternatively, as discussed above, the display 13 may be controlled by the winning matrix 12 at this time.
During the stationary display mode C, the signals present in the memory circuit 4 control the indications 5.1 to 5.4. These signals, stored in the memory circuit 4, have previously been produced by the winning combination circuit 14. Consequently, the player may now see the resulting winnings combination as a stationary image on the game feature carriers 5. Simultaneously, the numerical display 9 and the numerical display 11 or alternatively the display 13 of the winning matrix, are also controlled for their respective displays.
The various interconnecting leads in the block diagram of FIG. I are identified with the signals carried by these leads. The significance of these signals will be discussed in greater detail in the following paragraphs. Referring now to FIG. 2, various control signals controlling the operation of the circuit of the invention are derived from a control circuit 53. The various signal outputs of this circuit and their production are well known. For example, the stop pulses DC to DC are disclosed in Belgian Pat. No. I,537. The signals DC to DC DC -Stop to DC -Stop, and P to P are merely multiplex signals which are correlated to the game feature carriers in order to control the storage in the shift register 29 and thus the display D to D in the display field 6. Multiplex signals of this type are well known. The signal EoG is a signal corresponding to the end of a game. Briefly, the control pulses DC to DC are generated so that these signals appear at the beginning of a period of play, but terminate in a sequential order, the cessation of the signal being separated, for example, by milliseconds or seconds. The stop pulses DC, to DC occur sometime subsequent the start of the cycle of their respective control pulses DC to DC respectively, these pulses also occuring sequentially. The pulses may be under automatic control, as are the pulses DC to DC 4th but their time of occurrence may also be controlled manually.
Referring now to FIG. 2, during the stand-by mode A of operation, the signal EoG, which signifies the end of a game, has a state I. This signal EoG is applied to an inverter 15, the output of the inverter 15 being connected to one input of an AND-gate 17. The AND-gate 17 is thereby blocked to prevent the passage of signals from a five bit position counter 18. The clock pulses produced by the clock pulse generator I generates a five-bit combination in the five-bit counter 19, this bit combination being continuously repeated. The signal B06 is applied directly to one input of the AND-gate l6, and consequently, the five-bit combination output of the counter 19 can at this time be applied by way of the AND-gate 16 to OR-gates 20 to 23. The outputs of the OR-gates 20 to 23 are applied by way of the AND- gates 24 to 27 to an OR-gate 28, the output of the OR-gate 28 being applied to a shift register 29. The signals P to P are applied to second inputs of the AND-gates 24 to 27, and consequently, during the times P to P.,, the five-bit combinations from the counter 19 are applied by way of the respective AND gates 24 to 27 and the OR-gate 28 to the shift register 29. The information thus applied in series to the shift register 29 is shifted in five'bit steps through the shiftregister. The last five-bit combination in the shift register is applied to a one out of thirty-two decoder 30. The output of the decoder 30 is applied to the picture display 7 and also to the sections of the liquid crystal display D, to D.,, corresponding to the game feature carriers 5.1 to 5.4 of FIG. I. The elements D, to D, indicate the symbols appearing or present on the game feature carriers. For example, if the digit 3 appears on the game feature carrier 5.1 of FIG. 1, then this digit 3 appears on the indication D, in the liquid crystal display. The signals P, to P, are multiplexed to the displays as indicated in FIG. 2 and also applied to the AND- gates 24 to 27 to control the displays. Thus, the selection of the individual indicator positions 5.1 to 5.4 in the multiplex control is effected by means of the timlng signals P, to P, The control of the picture display 7 occurs continuously due to the fact that the multiplex signals P, to P are applied thereto by way of the OR- gate 31.
During the playing mode B of operation of the apparatus, the signal EoG has a state 0 and thus the AND- gate 16 is closed and the AND-gate 17 is opened by way of the invertor 15. Clock pulses from the clock generator 1 are applied to the five-bit position counter 18 by way of an AND-gate 32. The pulses of the clock generator are also applied to the five-bit counter 19 as above discussed. The outputs of the bits of the counter 19 are applied to a comparator 33 for detecting every fifth pulse of the clock generator, and the Null outputs of the comparator33 thus produced, is applied to one input of an AND-gate 34. The stop signals DC, to DC, are applied to the AND-gate 34 by way of the OR-gate 35. The output of the AND-gate 34 is applied to the position counter 18 as a reset signal.
The output of a random number generator is applied to the second input of the AND-gate 32 by way of an invertor 36. The output signals of the random number generator are dynamic logic signals which can either have a state 1 or a state 0. When a random number appears, a 0 signal appears at the output of the random number generator 15, and consequently, due to the use of the inverter 36, a 1 signal is applied to the second input of the AND-gate 32. Thus, when the random number generator output becomes 1, the AND-gate 32 is closed, and the pulses from the clock generator 1 are prevented from passing the AND-gate 32. Consequently, the position counter remains in its previously set position when the output of the random number generator is l. The pulse duration of the output signal of the random number generator determines the number of clock pulses passing the AND-gate 32 and as above stated, it thus controls the number which is stored in the position counter 18.
The information stored in the position counter 18 is applied by way of the AND-gate 17 to one input of each of the AND-gates 37 to 40. The signals DC,,, to DC, are applied to the second inputs of these AND- gates respectively. The outputs of the AND-gates 37 to 40 are applied by way of the OR-gates 20 to 23 and the AND-gates 24 to 27, the OR-gate 28, the shift register 29, and the decoder 30 to the indicators D, to D, in the above described manner. The passage of information is controlled by the signals DC to DC,,,, which control the opening of the AND-gates 37 to 40 respectively.
The control signals DC to DC are also applied to the inverters 4] to 44 respectively, the outputs of these inverters being applied to first inputs of the AND-gates 45 to 48 respectively. The output of the counter 19 is applied to second inputs of the AND-gates 45 to 48,
and third inputs of these AND-gates are energized by way of a control switch S0. The outputs of the AND- gates 45 to 48 are applied to third inputs of the OR- gates 20 to 23, for activation of the indicators D, to D in the above described manner. The inverters 41 to 44 prevent the control of the indicators D, to D, at any time that these indications are being controlled by the output of the position counter 18. The pulses from the counter 9, which are applied to the AND-gate 45 to 48 by way of the conductor 49, assure a continuously repeating bit combination in the shift register 29 when the switch 50 is closed, and the AN D-gates 37 to 40 are blocked. Such bit combination assures that the winning and loss symbols in the indicators 5.1 to 5.4 are continuously rotating.
The shift register 29 is normally not connected for ring-around operation. This type of operation may be effected, however, by means of the switch 51 and the AND-gate 52. Thus, the switch 51 applies an energizing signal to one input of the AND-gate 52 and the-other input of the AND-gate is connected to the output of the shift register 29. This feature assures that winning values provided in a fixed manner by the position counter 18 may be stored in the shift register 29 until the end of the game and during the time of selection of the first winning or loss symbol of the first game feature carrier.
The indications on the indicators D, to D, are determined by the coded output of the decoder 30, the specific indication given thus being determined by the signals applied to the register 29 during the time that the corresponding multiplexing signals P, to P, are present. The indications on the indicator D, to D, may be in moving form. It is apparent thus that when the indicators are under the control of the counter 19, they are continually changing their indications, for example, by rotation of indications. When the indicators are under the control of the position counter 18, they are being controlled in accordance with the play of the game. The switches 50 and 51 are controlled in accordance with the option outputs of the control circuit 53, to provide the necessary control functions of the circuit as above discussed. FIG. 3 illustrates in greater detail the control of the numerical displays 9 and 11 by means of the signal transformer 3. In this figure the elements between the clock generator I and the displays 9 and 11 correspond to the elements of the signal transformer.
The numerical displays 9 and 11 controlled by the counter 8 and the special game counter 10 are controlled in parallel in all of the modes A, B and C of operation as above discussed. Random frequency signals from the counter 8 and the special game counter 10, namely, the signals BCD,, BCD BCD and BCD,, must be converted to a determined lower frequency in order to control the liquid crystals of the display. The signals BCD, to BCD are binary coded signals for energizing the BCD seven segment decoder 58. The signals s, to s, are the corresponding multiplex control signals. In order to convert the BCD signals to a determined lower frequency, the relatively slower pulses of the clock generator 1 are applied to a counter 54, the counter 54 being connected to provide a one out of seven code at its output. The resulting 7 outputs s, to s, are applied to first inputs of separate AND-gates 55. The other inputs of the AND-gates are controlled by the multiplexing signals 8, to S The signals s, to s are also applied to the numerical displays 9 and 11.
The AND-gates 55 are thus opened to permit the passage of the higher frequency signals from the computer 8, i.e., the signals S to S These signals are passed through the OR-gate 56 to D-type flip-flops 57. These signals serve as inscribing signals for the signals BCD BCD BCD,, and BCD applied to the D terminals of these flip-flops, The outputs of the D-type flipflops 57 are connected to a decoder 58, and the outputs of the decoder are connected for the control of the numerical display 9 of the computer 8, and the numerical display I] of the special game counter 10.
The elements ID to 70, as illustrated in FIG. 3 are digit-two-indications" of the numerical displays 9 and 11. It should be born in mind, however, that in this context the numerical displays 9 and 11 are individual structural elements of the entire liquid crystal display means of the apparatus. By interconnecting these indications in a multiplex manner, the individual digits are energized or controlled so that no individual holding circuits are necessary for the digits. If the computer 8 is switched to the storage function of the winning matrix 12, then the display 13 of the winning matrix is controlled as shown in FIG. 4, and in this case, the numerical display of the special game counter is not controlled. The output signals BCD to BCD of the computer 8 and the signals 8,, S and S are provided for controlling the winnings matrix. The binary coded decimal signals are applied to the D terminals of the flipflops 59, and the signals S to 8;, are applied to the inscribing terminals thereof. These signals cause the storage of the signals BCD BCD BCD,, and BCD in the D-type flip-flops 59. The outputs of the D-type flip-flops 59 in turn are applied to the display of the winning matrix as indicated by the numerals l to 9 in FIG. 4. An apparatus of the above type is constructed and arranged in such a manner, for example, that free games may be obtained. The game storage may be constructed in the manner of a matrix, which is provided with its own indicating means, as shown in FIG. 4 by the numerals I to 9. These elements also constitute the part of the entire liquid crystal display arrangement of the apparatus. The output of the signals from the computer 8, i.e., the binary coded decimal signals, are applied in a multiplex method with the signals S to 8 An intermediate storage is effected in the flip-flops 59 which effect the switching on of those individual elements of the entire element arrangement indicated by numerals l to 9, the individual elements corresponding the the trigger signals. The elements I to 9 of FIG. 4 thus correspond to the winning matrix display 13 of three rows of three columns each of display elements. These indicating elements are not individual liquid crystals, but instead are individual structural elements of the entire integrated liquid crystal display arrange ment of the apparatus.
Although the invention has been described with reference to specific example embodiments, it is to be understood, that it is intended to cover all modifications and equivalents within the scope of the appended claims.
What is claimed is:
l. A control and indicator apparatus, comprising a first group of a plurality of display devices, first and second counters, a clock generator connected to apply clock pulses to said first and second counters, shift register means, means for selectively applying the output of said counters to said shift register means, and decoder means coupled to determined stages of said shift register means for controlling said display devices, said means for selectively applying the outputs of said counters to said shift register means comprising first and second AND-gate means connected to the outputs of said first and second counters respectively, means for selectively operating said first and second AND- gate means, OR-gate means coupling the output of said second AND-gate means to said shift register means, a plurality of third AND-gate means coupling the output of said first AND-gate means to said OR-gate means and means for selectively opening the AND-gate means of said plurality of AND-gate means.
2. The control and indicator apparatus of claim 1, further comprising a group of second AND-gate means having inputs connected to the output of said second counter and outputs connected said OR-gate means, and further comprising means responsive to said means for selectively opening the AND-gate means of said first mentioned plurality of AND-gate means for opening the AND-gate means of said second group of AND- gate means when the corresponding AND-gate means of said first mentioned group of AND-gate means are closed.
3. The control and indicator apparatus of claim I, further comprising random control means for inhibiting the application of said clock pulses to said first counter, and means responsive to the count of said second counter for resetting said first counter.
4. The control and indicator apparatus of claim 1, further comprising a second group of a plurality of display devices, a source of coded signals of random frequency, signal transforming means connected to said clock generator for converting said coded signals to a lower frequency, and means for controlling the display devices of said second group of display devices with the output of said signal transformer means.
5. In an apparatus of the type having a display panel with game feature carriers, the improvement wherein said game feature carriers are mechanically fixed liquid crystal means positioned to provide rotating displays, and further comprising additional mechanically fixed liquid crystal means on said panel, and circuit means connected to the liquid crystal means of said game feature carriers and to said additional liquid crystal means for controlling displays thereon, said circuit means comprising means for controlling said liquid crystal means of said game feature carriers to produce rotating displays only during first determined times, means for controlling said liquid crystal means of said game feature carriers during second determined times to produce fixed displays, and means for controlling said additional liquid crystal means during said second determined times.
6. The apparatus of claim 5, wherein said additional liquid crystal means comprise first liquid crystal means arranged to produce a numerical display, and second liquid crystal means arranged to produce a matrix display and said circuit means comprises means during said second determined times for selectively control ling said first and second liquid crystal means, and further comprising means for displaying different colors on the liquid crystal means of said apparatus.
* ll i
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