|Publication number||US3935439 A|
|Application number||US 05/487,105|
|Publication date||Jan 27, 1976|
|Filing date||Jul 12, 1974|
|Priority date||Jul 12, 1974|
|Also published as||DE2531165A1|
|Publication number||05487105, 487105, US 3935439 A, US 3935439A, US-A-3935439, US3935439 A, US3935439A|
|Inventors||Dennis Darcy Buss, Walter Howard Bailey|
|Original Assignee||Texas Instruments Incorporated|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Non-Patent Citations (8), Referenced by (36), Classifications (12)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to charge transfer devices, including charge coupled devices (CCD) or bucket brigade devices (BBD), and which are employed for cross-correlation or convolution of two signals, both of which vary with time.
It is well-known in the art to employ various devices for the processing of two signals through convolution. However, fixed tap weights are used as weighting coefficients for performing the convolution between the two signals, the operation being performed digitally. In analog applications, a digital filter requires the transforming of the analog signal to a form usable by a digital device, as well as requiring a large number of arithmetic operations to perform the convolution between two signals.
Accordingly it is a feature of this invention to provide an electronic device which directly receives analog signals and which performs a convolution between said analog signals with a minimum of time and apparatus required.
Other objects and features of the invention will become apparent to one skilled in the art upon consideration of the specification including the claims and the drawings.
In accordance with the present invention, a convolution is to be performed between two analog signals with semiconductor devices. The apparatus of the instant invention employs charge transfer device shaft register for accepting the input signals.
The convolution tap weights may be made to vary as a function of time continuously updating such tap weights. The update is accomplished by displacing the old tap weights held in the tap weight shift register with newly sampled values of the tap weight signal.
FIG. 1 is a block diagram of a variable tap weight convolution filter.
FIG. 2 is a schematic diagram of a charge coupled device shift register with amplifiers for receiving outputs therefrom.
FIG. 3 shows clock pulse and signal waveforms pertinent to operation of FIG. 2.
FIG. 4 is a schematic diagram of a bucket brigade device shift register with amplifiers for receiving outputs therefrom.
FIG. 5 is an illustration of apparatus embodying the invention for handling positive and negative weighting coefficients.
FIGS. 6 and 7 are block diagrams of other embodiments of apparatus embodying the invention for handling positive and negative weighting coefficients.
As set forth above, the present invention employs charge transfer devices, which include charge coupled devices and bucket brigade devices, for performing a convolution of two signals, utilizing variable tap weights. Such devices are used as shift registers in the convolution filter of the present invention, one shift register functioning to store tap weights from a time-variable input signal, and another shift register for receiving the signal to be convolved. Being fashioned from charge transfer devices, the shift registers are less complex than conventional shift registers and accordingly allow more economical applications.
In general a CCD stores charges proportional to analog input signals in potential wells, beneath electrodes disposed at and insulated from a semiconductor surface, moving these wells from electrode to electrode in order to transfer the charge with the resulting shift register function occurring.
A BBD commonly comprises a row of insulated gate field effect transistors (IGFETS) having their channels in series and storage capacitance provided between the gate and drain of each transistor. In integrated circuit form, a common doped region provides the drain for one transistor and the source for the next succeeding transistor, as well as providing an interconnection between them. The gate electrodes of the transistors are extended to overlap the respective drain regions sufficiently to provide the required gate-drain capacitances. The BBD transfers charge by providing a potential difference between storage capacitors at the site from which and the site to which the charge is to be transferred. When the potential difference is large enough the charge transfers from one capacitor to the next.
It is understood that any combination of CCD's or BBD's may be used for the input shift registers of the present invention.
Essentially a device according to the present invention is illustrated by the block diagram of FIG. 1.
Two charge transfer device shift registers SR1 and SR2 are provided; these may both be CCD or BBD shift registers; alternatively one may be a CCD and the other a BBD shift register. Analog signals V1 and V2 are sampled and clocked into shift register SR1 and SR2 respectively and propagated along those shift registers in conventional manner. The sampled values of V2 provide tap weights for the convolution operation to be performed. Signal levels stored at corresponding stages of each shift register are non-destructively detected and applied as inputs to multipliers M which provide outputs proportional to the products of the sampled values at each shift register stage. The outputs of the multipliers M are simultaneously summed or accumulated by a summation amplifier SA to provide a convolved output signal. The convolution of V1 and V2 is indicated by the symbols V1 x V2.
FIG. 2 illustrates in greater detail a portion of a system as shown in FIG. 1 using CCD shift registers SR1 and SR2. Associated clock pulse timing diagrams are illustrated by FIG. 3. The CCD shift registers SR1 and SR2 are illustrated in FIG. 2 as 3-phase registers with the transfer electrodes connected to clock pulse phase lines as shown. However, any polyphase CCD shift register system could be used, the choice being determined by the particular application involved. In both shift registers, each stage incorporates a floating gate amplifier for non-destructive detection or sampling of the signal level stored at that stage. Thus, in each stage of the shift registers SR1 and SR2, a floating electrode FE (i.e., an electrode not connected to a clock pulse phase) is located between the φ2 and φ3 phase transfer electrodes. Considering A of shift register 1 and shift register 2, the floating electrodes FE thereof are connected to (or extended to form) the gate electrodes of respective IGFETs Q1 and Q2, the source of transistor Q1 being connected to the drain of transistor Q2 with an output taken from the source of transistor Q2 so that transistors Q1 and Q2 function as a source follower amplifier. Respective preset IGFET transistors Q3, Q4 have their sources connected to the gates of transistors Q1 and Q2, the gate of each transistor Q3 being connected to receive preset pulses φPS. For clarity, FIG. 2 illustrates a structural configuration and a circuit schematic for the floating gate amplifier just described.
The drains of transistors Q1 of all the stages of the shift register SR1 are connected to a common drain supply VDD while the sources of transistors Q2 of all the stages of shift register SR2 are connected as a common input to a current summation amplifier SA having an output terminal OT.
Operation of the system illustrated by FIG. 2 may be explained as follows. With clock signal φ2 on, signal sample related charges are stored beneath the φ2 electrodes in shift registers SR1 and SR2. During a portion of the on period of clock pulse φ2 that does not overlap the associated φ1 pulse period, a short precharge pulse φPS is applied to the gates of transistors Q3 and Q4 to precharge the floating gate nodes N1A and N2A of shift registers SR1 and SR2 to a predetermined voltage. When clock pulse φ2 switches to an off condition, charges corresponding to the signal levels previously stored beneath the phase φ2 electrodes are transferred to beneath the floating gate electrodes FE in the respective shift registers SR1 and SR2, giving rise to corresponding gate voltages VSi at transistor Q1 and VGi at transistor Q2. The resulting current Ii through the transistors Q1 and Q2 is thus proportional to the product VGi x VIi. The nodes N1A and N2A may be reset to a reference potential prior to occurrence of the next φ1 pulse. It is not necessary to reset every clock period, however.
The product current Ii for all of the stages of the shift registers are applied as a common input to the current summing amplifier SA to produce a convolved output signal at the output terminal OT.
In FIG. 3, the same waveform is shown for nodes N1A and N2A for the sake of simplicity; however, it will be appreciated that the actual voltages of these nodes will normally differ, depending on the respective values of signal related voltages VSi and VGi.
When floating gate amplifiers are fabricated with two levels of conducting material (double level process) a part or all of the floating gate may lie beneath clock electrodes.
In place of a floating gate amplifier as described with reference to FIG. 2, a floating diffusion amplifier may be used. In that case, doped (e.g., diffused) regions would be formed in the semiconductor substrate at locations corresponding to the floating electrodes FE which would be omitted. The doped regions would extend beyond the transfer electrodes in a direction laterally of the signal propagation direction along the shift registers, and the gate electrodes of transistors Q1 and Q2 would be extended to ohmically connect with the corresponding doped regions in the shift registers SR1 and SR2 respectively.
FIG. 4 shows an embodiment of the invention utilizing BBD shift registers SR1 and SR2 in conjunction with floating diffusion amplifiers for signal detection at the shift register stages. In the shift registers SR1 and SR2, each stage is defined by two IGFETS QX and QY with associated gate-drain capacitances CX and CY. Application of φ1 phase clock pulses to the gates of transistors QX transfers signal related charge to the associated capacitances CX from the capacitances CY of the transistors QY of the respective preceding stages. During a φ2 phase clock pulse applied to transistors QY (non-concurrently with φ1) charge is transferred to capacitances CX of transistors QX from the capacitances CY of the transistors QY of the respectively succeeding stages corresponding to signal propagation from CY to CX. For convenience, FIG. 4 shows representative shift register stages in structural format and in circuit schematic format, and the stages would be continued to the right to provide a desired number of stages in each shift register.
Considering stages A of shift registers SR1 and SR2, the drain regions D of transistors QX are extended laterally of the direction of charge propagation along the shift registers. Transistors Q1 and Q2 have gate electrodes G ohmically connecting with the extensions of the drain regions D of transistors QX in shift registers 1 and shift register 2 respectively. The source of transistor Q1 is connected with the drain of transistor Q2 and these two transistors function as a linear source follower amplifier with the drains of transistors Q1 of each stage connected to a common supply voltage VDD, while the sources of the transistors Q2 of each stage are applied as a common input to a current summation amplifier SA.
The operation of the system may be explained as follows. Input signals VG are applied to the shift register SR2 to store required tap weight signals in the respective stages of that shift register. An analog signal VS to be convolved is sampled and clocked into the shift register SR1. A charge stored at the node NA1 of shift register SR1 having a magnitude depending on the associated sample of the input voltage VS, gives rise to a corresponding gate voltage VSi at transistor Q1 of stage A. Likewise, a gate voltage VGi is applied to the transistor Q2 of stage A as a result of the tap weight related charge stored at node N2A of shift register 2. The resultant current Ii flowing through transistors Q1 and Q2 is then proportional to the product VSi x VGi. These product currents are summed by the current summation amplifier SA to provide an output convolution signal at the terminal OT.
At this point, it is important to consider the manner in which the currents Ii are combined. In sampling an input signal to be utilized as the tap weight function, the fact of its being time-variable indicates that both positive and negative weighting coefficients may be encountered.
In general, positive and negative weighting coefficients are connected respectively to positive and negative summing buses, with the signals being combined through a differential amplifier. There are two basic methods which may be employed to accomplish this.
First, only the magnitude of the input signal VG would be applied to the shift register SR2. This may be accomplished by full wave rectification of the signal, with the arithmetic sense of the signal being retained by a digital shift register. The sources of transistors Q2 would then not all be connected in common to a single summation amplifier SA, but would be selectively connectable to either a positive or a negative current summation amplifier, dependent on the sign of the corresponding tap weights, under control of the digital sense shift register.
Alternatively, one could use two shift registers in the place of former shift register SR2. The tap weight signal VG would be applied to the first shift register SR2A, the inverse of the tap weight signal applied to the second shift register SR2B, with only the positive voltages activating the load transistor Q2 in each transistor. The negative voltages would correspond to a zero weighting coefficient and therefore would not be used.
This technique would also require the use of two summing buses, one for each shift register, SR2A, SR2B, which are connected to the appropriate inputs of a differential amplifier.
There is a third apparatus which may be employed in accord with the present invention to solve the problem of handling positive and negative weighting coefficients. Specifically, the tap weight input signals VG into shift register SR2 (FIG. 5) are offset from their normal value by the addition of a d-c component (B) so that a zero value of weighting coefficient would be represented by a voltage which gives a load conductance midway between its minimum and maximum value. A positive weighting coefficient would then be represented by a larger conductance (than the median value) and a negative coefficient would be represented by a smaller conductance (than the median value). Under these conditions the weighting coefficients of the signals at the i th stage of the shift register SR2 will be
Hi (t) = VGi (Tdi -t) + B
Hi = ith weighting coefficient
VGi = amplitude of the sampled signal stage i
Tdi = delay time between the input of a signal to the shift register and the sampling of such signal at stage i.
The convolution signal VOA, then depends on VS x (VG +B).
It now becomes necessary to cancel the term Bx V5 from the output signal VOA. As shown in FIG. 5, this is accomplished by applying the input signal VS to shift registers SR1A and via an inverter INV to shift register SR1B.
A unit 50, which may be a shift register storing constant tap weight signals, or which may be conventional weighting means applies fixed tap weight coefficients having the value B to the signals sampled at the stages of the shift register SR1B which receives the inverse of input signal VS. Thus, the convolved signal on line VOB is dependent on [- VS x B]. The signals on lines VOA and VOB are applied as non-inverting inputs to a current summation amplifier CSA which produces an output signal Vout proportional to VS x VG, i.e., the d.c. component B has been canceled.
FIG. 6 is a block diagram form represents a further embodiment which may be utilized in the cancellation of the constant term B, which has been added to the top weighting signal VG. The weighting coefficient hi A from the combination of the tap weight signal VGi + B from the ith stage of the shift register SR1A for the signal VSi from the ith stage of shift register SR2 appears as:
hi A (t) = VGi (Tdi - t) + B
Tdi = delay time between the analog sample being inputted to the shift register SR1A and the detection thereof at the ith stage
hi A (t) = weighting function at a time t at the i th stage
B = the constant component added to the signal
Consequently, the convoluted signal at VOA is RΣ1 [VSi VGi + BVSi ]
Similarly, the convoluted signal at VOC is RΣi [-VSi VGi + BVSi ] where R is a gain factor and the time dependence of VSi and VGi is implicit. Application of the signals VOA and VOC are non-inverting and inverting inputs, respectively to the current summation amplifier CSA provides an output signal Vout = 2R Σi VSi × VGi which is equivalent to the convolution operation 2RVS x VG.
In another embodiment shown at FIG. 7, a CTD shift register SR2 receives a tap weight signal VG offset by a constant d.c. component B. Shift register SR2 generates weighting signals for convolution with analog input signal VS inputted to CTD shift register SR1. In a separate operation, the input signal samples of VS are weighted by the constant d.c. component B, e.g., using a shift register SR3 having constant level signals stored at each stage thereof or using conventional weighting means.
The tap weights applied from the i th stage of shift register SR2 is thus hi A (t) = VGi (Tdi - t) + B. and the tap weight from the i th stage of shift register SR3 is
hi C (t) = B
The resultant convoluted signals on output lines VOA and VOC are applied, respectively, as non-inverting and inverting inputs to current summing amplifier SCA to produce an output signal
Vout α VS x VG.
The modification of a shift register SR1 as shown in FIG. 2 or FIG. 4 to function as illustrated by FIG. 7 is straight forward and will not be described in detail.
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|U.S. Classification||708/818, 708/819, 333/165, 257/214, 257/251|
|International Classification||G06G7/19, H03H15/02|
|Cooperative Classification||G06G7/1907, H03H15/02, H03H2015/026|
|European Classification||G06G7/19C, H03H15/02|