|Publication number||US3987293 A|
|Application number||US 05/601,897|
|Publication date||Oct 19, 1976|
|Filing date||Aug 4, 1975|
|Priority date||Aug 4, 1975|
|Publication number||05601897, 601897, US 3987293 A, US 3987293A, US-A-3987293, US3987293 A, US3987293A|
|Inventors||Arthur W. Crooke, Horst A. R. Wegener|
|Original Assignee||Sperry Rand Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (23), Classifications (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to the art of electrical filters and specifically to a sampled data filter, employing bucket brigade technology, the response of which may be varied with the alteration of a stored reference function.
2. Description of the Prior Art
Bucket brigade delay line (BBDL) technology which allows information storage in analog form offers the means by which the theory that has been developed for the design of digital filters can be utilized to design sampled data analog filters without the need for analog-to-digital conversion, thus combining the advantages of digital signal processing with the speed and simplicity of analog circuitry. These techniques have been employed in the prior art to design recursive and transversal type filters. The response characteristics, i.e., center frequency and bandwidth, of the recursive filters depend on the circuit parameters of gain and BBDL clock frequency, both of which may be electrically controlled thus providing a programmable filter. However, the recursive structure gives rise to spurious responses that limit the filter's frequency range of operation. Techniques to minimize the spurious responses require an appreciable increase in circuitry and gain parameters with a concomitant increase in complexity and cost.
Prior art transversal filters utilizing BBDL technology have been designed with fixed and programmable response characteristics. Fixed response designs establish desired weighting at each tap by means of a suitable choice of storage capacitance values whereas the programmable designs utilize amplifiers at each tap, the transconductance of which is electrically altered to provide the required weights to achieve the desired frequency response. Stop band performance characteristics of these filters is dependent upon the relative accuracy that can be achieved in the tap weight implementations, which is limited by the transconductance control ability of the amplifiers. Additionally, the filter characteristics that may be programmed are limited by the transconductance ranges of the amplifiers utilized.
The present invention provides a programmable transversal filter wherein the tap weights are supplied by a stored reference function, thereby eliminating the limitation on the range of filter characteristics that may be realized that are imposed by the achievable relative tap weight accuracies and transconductance ranges of the prior art.
A preferred programmable general purpose filter constructed according to the principles of the present invention includes an input signal sampler which provides a number of input signal samples and a reference signal sampler which provides an equal number of reference signal samples that are the weighting factors applied to the input signal samples. These weighting factors represents samples of the inpulse response of the desired filter. Each input signal sample is multiplied by a corresponding reference signal sample and the resulting signal products are summed to obtain an output signal which is the sampled output response of the filter for the given number of input signal samples.
Both the input signal sampler and the reference signal sampler may be a charge transfer device, the charge transfer efficiency of which may limit the filter characteristics that may be programmed. Limitations composed by charge transfer efficiency are aggravated by the fact that storage in these devices is unipolar and a d.c. bias must be applied to the input and reference signals at the intput terminals of the samplers. These problems are minimized with the use of a push-pull sampler or shift register which includes two tapped delay lines that operate with complementary input signals. The input signal to be sampled is coupled to the input terminal of one of the delay lines and to the input terminal of an inverter, the output terminal of which is coupled to the other delay line, thus coupling the input signal to the first delay line and the negative of the input signal to the second delay line. Simultaneously a d.c. bias voltage is coupled to the input terminals of the first and second delay lines, thus providing a bias voltage plus the signal at the input terminal of the first delay line and a bias voltage minus the signal at the input terminal of the second delay line. At each tap along the delay line, the sampled signal from the second delay line is subtracted from the sample signal of the first delay line, this results in a signal representative of the sampled signal only, thus reducing bias errors resulting from the charge transfer efficiency factor.
The subtraction required for push-pull operation for both the input and reference signal shift registers and the multiplication of the input signal sample by the reference signal sample are all accomplished by a novel circuit which employs four MOSFETS and a difference amplifier. The gate electrodes of the first and second MOSFETS are coupled as are the gate electrodes of the third and fourth. One of these pairs is coupled to a tap of one of the reference signal delay lines and the other pair is coupled to the corresponding tap of the other reference signal delay line. The drain electrodes of the first and third MOSFETS are coupled to a tap of one of the input signal delay lines and the drain electrodes of the second and fourth MOSFETS are coupled to a tap of the other input signal delay line. The drain currents of the first and fourth MOSFETS are added by connecting the source electrode of the first to the source electrode of the fourth and the drain currents of the second and third MOSFETS are added by connecting the source electrode of the second to the source electrode of the third. One of these current sums is connected to a terminal of the difference amplifier and the other current sum is connected to a second terminal of the difference amplifier. With this circuitry and with the MOSFETS operating in the triode region, the signal that appears at the output terminal of the difference amplifier is equal to the product of the sampled input signal and the sampled reference signal. Other features and advantages of the invention will become apparent from the following detailed description.
FIG. 1 is a block diagram showing a digitally programmable general purpose filter.
FIG. 2 is a block diagram showing a digitally programmable general purpose filter employing push-pull analog delay lines.
FIG. 3 is a schematic of a subtraction multiplier network.
FIG. 4 is a schematic diagram, partially in block form, of a multiplier summation network.
The output of a filter is given by the convolution of the input signal with the impulse response of the filter. If the output signal is a sequence of sampled data, the filter output is described by the convolution equation: ##EQU1## wherein Yi is the filter output signal after summing the previous N samples, Xi -n is the nth previous sample and rn is the filter impulse response value during the time interval of the nth sample. Thus a filter may be synthesized by storing the most recent N samples of the input signal xt, multiplying each sample by an appropriate weighting factor which is a sample of a reference function representative of the desired filter impulse response, and summing the products.
Referring to FIG. 1, a programmable filter 10 may include an input signal analog shift register 11, which may be a BBDL or other charge transfer device that stores the most recent samples of the input signal applied to the input terminal 12; a reference signal analog shift register 13, which stores samples of the reference signal applied to the reference signal input terminal 14; an analog buffer register 16, which may be a charge transfer device; multipliers 151 to 15N, wherein each sample of the input signal is multiplied by a corresponding sample of the reference signal, and summation network 20. Samples of the reference function, which are the weighting factors rn for the signal samples, appear at terminals 131 through 13N. These weighting factors may be applied directly to the multipliers 151 through 15N or may be stored in the analog buffer register 16, from which they are coupled to the multipliers 151 through 15N. Weighting factors rn stored in the buffer register 16 remain stored until a new set of weights is entered therein from the analog shift register 13. Output signals from the multipliers 151 to 15N, which represent the multiplication of the input signal samples by the weighting factors, are coupled to the summing device 20 via lines 211 through 21N wherein their sum representing the desired filtered signal, is obtained and coupled to an output terminal 22.
A digital reference signal may be employed to provide the weighting factor rn by coupling the digital reference signal to the input terminal 23 of a digital serial memory 24, the output terminal 25 of which couples to a digital-to-analog converter 26. The output terminal 27 of the digital-to-analog converter 26 is then coupled to the input terminal 14 of the reference signal analog shift register 13. With the incorporation of the digital serial memory 24 and the digital-to-analog converter 26, the digital reference signals are converted to analog reference signals which are coupled to the reference signal analog shift register 13, whereby the weighting factors rn are coupled to the multipliers 151 to 15N from the output terminals 131 to 13N. Once a digital reference signal has been entered into the digital serial memory 24, it may be maintained by coupling the input terminal 23 of the digital serial memory 24 to the input terminal 28 of the digital-to-analog converter 26. This coupling allows the digital serial memory 24 to be periodically refreshed by recirculation while at the same time its output is converted to an analog signal which provides the analog reference to the reference signal analog shift register 13.
Storage in charge coupled and bucket brigade devices is unipolar, thus requiring a d.c. bias when an a.c. signal is to be stored. Due to the charge transfer efficiencies of these devices, bias errors are generated as the bias signal is transferred from tap to tap along the analog shift register. This problem may be minimized with the use of a push-pull analog shift register which comprises two charge transfer shift registers operating with complementary input signals. The input signal to one shift register being a bias voltage plus the signal and the input to the other being the same bias voltage minus the signal. Since the complementary relationship is maintained at each tap of the charge transfer shift register, subtracting corresponding tap signals results in an effective cancellation of the bias voltage. Thus, bias voltage error degradation to the filter response may be maintained by utilizing push-pull analog shift registers.
Refer now to FIG. 2, wherein a programmable analog filter 10 incorporating push-pull analog shift registers is shown. An input signal s, applied to the input terminal 12 is coupled to the input terminal 31 of the input signal analog shift register 11 and to the input terminal 32 of an inverter 33. The output signal of the inverter 33, which possesses a polarity that is opposite to the polarity of the signal applied to the input terminal 32, is coupled to the input terminal 34 of a second input signal analog shift register 35. An input signal bias voltage Vs is supplied at terminal 36 by a d.c. source (not shown). The bias voltage Vs is then coupled to the input terminals 31 and 34, whereby a voltage equal to Vs +s is applied to the input terminal 31 of the input signal analog shift register 11 and a voltage equal to Vs -s is applied to the input terminal 34 of the second input signal analog shift register 35. The output taps 371 to 34N of the input signal analog shift register 11 and the output taps 381 to 38N of the second input signal analog shift register 35, at which delayed signals Vs +s and Vs -s appear, are each coupled respectively to difference circuits 391 to 39N, whereby the samples of the biased input signals Vs +s and Vs -s, which appear at the output taps 371 to 37N and the output taps 381 to 38N are coupled to the appropriate difference circuits 391 to 39N, wherein the difference between the sampled biased signals Vs +s and Vs -s is taken and a signal which is representative of the sampled input signal s is coupled to each output terminal 391C to 39NC.
Still referring to FIG. 2, a reference signal r applied to the input terminal 14, is coupled to an input terminal 40 of the reference signal analog shift register 13 and to the input terminal 41 of an inverter 42. The output signal from the inverter 42, which possesses a polarity that is opposite to the polarity of the signal applied to the input terminal 41, is coupled to the input terminal 43 of a second reference signal analog shift register 44. A reference signal bias voltage Vr is supplied at terminal 45 by a d.c. source (not shown). The bias voltage Vr is then coupled to the input terminals 40 and 43 of reference signal analog shift registers 13 and 44, respectively, whereby a voltage equal to Vr +r is applied to the input terminal 40 of the reference signal analog shift register 13 and a voltage equal to Vr -r is applied to the input terminal 43 of the second reference signal analog shift register 44. The output taps 131 to 13N of the reference signal analog shift register 13, at which delayed signals of Vr +r appear, are coupled to corresponding input terminals of the analog buffer register 16, whereby samples of the biased reference signals Vr +r, at the output taps 131 to 13N, are coupled to difference circuits 461 to 46N via the output terminals 161 to 16N of the analog buffer register 16. Similarly, the output taps 441 to 44N of the second reference signal analog shift register 44 are coupled to corresponding input terminals of a second analog buffer register 47, whereby samples of the biased reference signal Vr -r, at the output taps 441 to 44N are coupled to difference circuits 461 to 46N via the output terminals 471 to 47N of the analog buffer register 47. The signals at the output terminals 461C to 46NC of the difference networks 461 to 46N are representative of the samples of the reference signal r, being the differences between the sampled reference signals at the output terminals 471 to 47N and the sampled input signals at the output terminals 161 to 16N, respectively.
Each sample of the reference signal r at the output terminals 461C to 46NC of the difference networks 461 to 46N and each sample of the input signal s at the output terminals 391C to 39NC of difference networks 391 to 39N is coupled respectively to multipliers 151 to 15N wherein each sample of reference signal r and the corresponding sample of input signal s are multiplied. Signals at the output terminals of each of the multipliers 151 to 15N are coupled to summation network 20 via lines 211 to 21N wherein the products of the sampled reference signal r and the sampled input signal s are summed and a signal representative of this sum, which is the output signal of the filter, is coupled to the output terminal 22.
Though the sampled signals at the output taps of registers 13 and 44 are coupled to difference networks 461 to 46N via the analog buffer registers 16 and 47, these couplings could have been directly from storage registers 13 and 44 as previously discussed.
Each of the combinations of subtraction networks 39k and 46k with multiplier 15k comprise an over-all subtraction multiplier network 50k which for simplicity hereinafter will be referred to as a multiplier. These two arithmetic operations may be performed by the network shown in FIG. 3 though other combinations of difference and multiplier circuits may be employed. FIG. 3 is a schematic diagram of a novel multiplier circuit that provides linear arithmetic operation for bipolar input signals over a large dynamic range. The circuit consists of four MOSFET transistors 51, 52, 53 and 54, all of which operate in the triode region. The gate electrode 51g of MOSFET 51 is connected to the gate electrode 52g of MOSFET 52, thereby forming a node 55 and the gate electrode 53g of MOSFET 53 connected to the gate electrode 54g of MOSFET 54 thereby forming a node 56. The drain electrode 51d of MOSFET 51 is connected to the drain electrode 53d of MOSFET 53 thereby forming a node 57 and the drain electrode 52d of MOSFET 52 is connected to the drain electrode 54d of MOSFET 54 thereby forming a node 58. The source electrodes 51s of MOSFET 51 and 54s of MOSFET 54 are connected thereby forming a node 60, and the source electrodes 52s of MOSFET 52 and 53s of MOSFET 53 are connected thereby forming a node 59. Nodes 55, 56, 57 and 58 serve as the input terminals to the multiplier 50k and as such correspond to input terminals 46ka, 46kb, 39kb and 39ka, respectively. Nodes 59 and 60 coupled to input terminals 63 and 64, respectively, of difference amplifier 65, the output terminal 66 of which couples to line 21k of FIG. 1.
The voltage current relationships of a FET operating in a triode region is given by
Id = β [(Vg - Vth) Vd - 1/2 Vd 2 ]
where Id is the drain current, Vg is the gate voltage, Vd is the drain voltage, Vth is the threshold voltage, and β is a constant.
In FIG. 3, the voltage at input terminal 39kb, which is equal to Vs +s is the drain voltage for FETS 51 and 53, and the voltage at input terminal 39ka, which is equal to Vs -s is the drain voltage for FETS 52 and 54. The voltage at input terminal 46ka, which is equal to Vr +r is the gate voltage for FETS 51 and 52 and the voltage at input terminal 46kb is the gate voltage for FETS 53 and 54. Since the FETS are to operate in the triode region the values of Vs, Vr, s and r are chosen so that Vd for each FET is always negative and Vg - Vth is always more negative than Vd. For these conditions, the drain currents Id1, Id2, Id3 and Id4 for transistors 51, 52, 53 and 54, respectively, are
Id1 = β[(Vr +r - Vth) (Vs +s) - 1/2 (Vs +s)2 ]
Id2 = β[(Vr +r - Vth) (Vs -s) 1/2 (Vs -s)2 ]
Id3 = β[(Vr -r - Vth) (Vs +s) - 1/2 (Vs +s)2 ]
Id4 = β[(Vr -r - Vth) (Vs -s) - 1/2 (Vs -s)2 ]
The drain current Id1 flowing through the source electrode 51s of transistor 51 and the drain current Id4 flowing through the source electrode 54s of transistor 54 add at node 60, this sum being coupled to the positive input terminal 64 of difference amplifier 65, while the drain current Id2 flowing through source electrode 52s of transistor 52 and the drain current Id3 flowing through source electrode 53s of transistor 53 add at node 59 this sum being coupled to the negative input terminal 63 of difference amplifier 65, whereby the signal at the output terminal 66 of differential amplifier 65 is representative of the algebraic sum
Iko = Idk1 - Idk2 - Idk3 + Idk4 = 4βrk sk.
Since each of the multipliers 50l to 50N, when employing the circuitry of FIG. 3, provides two currents to the difference amplifier 65, the summation of the products may be accomplished by connecting all the terminals 63l to 63N to a common bus line 67 and all the terminals 64l to 64N to another bus line 68 as shown in FIG. 4. Bus lines 67 and 68 may then be coupled to the negative and positive input terminals, respectively, of difference amplifier 69. In this manner, only one amplifier need be employed to form the algebraic sum of currents, Idiff, from the contributions of all the multipliers 50l to 50N where: ##EQU2##
While the invention has been described in its preferred embodiment, it is to be understood that the words which have been used are words of description rather than limitation and that changes may be made within the purview of the appended claims without departing from the true scope and spirit of the invention in its broader aspects.
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|U.S. Classification||708/819, 327/552, 377/58|
|Cooperative Classification||H03H2015/026, H03H15/02|