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Publication numberUS4000506 A
Publication typeGrant
Application numberUS 05/566,259
Publication dateDec 28, 1976
Filing dateApr 9, 1975
Priority dateApr 10, 1974
Also published asCA1026468A1, DE2515577A1, DE2515577C2
Publication number05566259, 566259, US 4000506 A, US 4000506A, US-A-4000506, US4000506 A, US4000506A
InventorsSusumu Hirai, Kunizo Suzuki, Hajime Yagi
Original AssigneeSony Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Bipolar transistor circuit
US 4000506 A
Abstract
A transistor circuit comprising a bipolar transistor with high input impedance is disclosed. The transistor has low emitter-base conductance, and especially has a low conductance component caused by the recombination of minority carriers in an emitter. The emitter capacitance caused by stored minority carriers is low because of the low conductance component. These enable emitter-grounded operation at high current gain and high frequency.
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Claims(6)
We claim as our invention:
1. A circuit comprising:
a transistor having a first region of semiconductor material of one conductivity type, a second region of semiconductor material of the opposite conductivity type interfaced with said first region and forming a first PN junction at the interface, a third region of semiconductor material of said one conductivity type interfaced with said second region on the opposite side thereof from said first region and forming a second PN junction at said second interface;
an input circuit connected to said first and second regions;
an output circuit connected to said first and third regions;
the conductance of said first and second regions having first and second conductance components which correspond to the recombination of minority carriers in said first and second regions respectively;
said conductance component in said first region being less than ten times the conductance component in said second region;
and the capacitance caused by stored minority carriers in said first region being smaller than that in said second region.
2. A circuit according to claim 1, in which said first region of said transistor is provided therein with a third junction between a region of low impurity concentration and a region of high impurity concentration, which junction is spaced from said second region by a distance smaller than the diffusion length of minority carriers in said first region when said first junction is forwardly biased in operation, said region of low impurity concentration lying between said first and third junctions, and the width of said high impurity concentration region being less than the width of said low impurity concentration region.
3. A circuit according to claim 1, in which said first region is provided therein with a hetero junction spaced from said second region by a distance smaller than the diffusion length of minority carriers injected into said first region from said second region when said first junction is forwardly biased.
4. A circuit according to claim 2, in which the width of said high impurity concentration region is approximately one-half that of said low impurity concentration region.
5. A circuit according to claim 1, in which said second region is provided therein with a low impurity concentration portion and a high impurity concentration portion surrounding said low impurity concentration portion.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor circuit and particularly to a transistor circuit using a bipolar transistor with high input impedance.

2. Description of the Prior Art

A transistor having its base width greatly reduced in order to improve its high frequency characteristics is disclosed in U.S. Pat. No. 3,591,430.

The above mentioned transistor has such a construction as shown in FIG. 1, which illustrates an NPN-type transistor. In FIG. 1, an embedded base region 10b of, for example, P-type is formed on an N-type semiconductor substrate which is a collector region 10c, and a semiconductor layer forming an emitter region 10e is formed on the base region 10b. On the periphery of the embedded base region 10b there is formed a base electrode contact region 10b' of relatively high impurity concentration in an annular shape which is extended to the semiconductor surface. A base electrode 11b is deposited on the region 10b' in an ohmic contact therewith, an emitter electrode 11e is deposited on the emitter region 10e surrounded by the region 10b' in an ohmic contact therewith, and a collector electrode 11c is deposited on the collector region 10c in an ohmic contact therewith. Reference 10e' designates a region used to deposit the emitter electrode 11e on the emitter region 10e in ohmic contact therewith. Reference characters E, B and C indicate emitter, base and collector terminals, respectively.

In the thus constructed transistor, the portion of the base region facing the semiconductor surface, that is, the portion connected with the base electrode 11b, is formed therein as a region 10b' of relatively high impurity concentration, so that carrier injection is small relative to the surface of the aforesaid portion or relative to the lateral direction. For this reason, the emitter junction is operated mainly at a junction portion je between the emitter region and the embedded region 10b, that is, a portion opposite a collector junction jc. In addition, the thickness of the region 10b is quite small, so that the base transport factor β is high.

Meanwhile, a consideration will be given on the emitter-grounded current amplification factor hFE which is used as one of parameters for evaluating the characteristics of a transistor. If the base-grounded current amplification factor is taken as α, the emitter-grounded current amplification factor hFE is given as follows: ##EQU1## Further, the base-grounded current amplification factor α is given as follows:

α = α*βγ                            2.

where α* is the collector amplification factor, β is the base transport factor, and γ is the emitter injection efficiency.

Considering now an emitter-grounded transistor circuit, a simplified hybrid π-type equivalent circuit for this circuit in a range between middle and high frequencies is shown in FIG. 2. In this circuit, the following letters or characters are employed:

______________________________________rx :   base resistance,gπ:  parameter indicating recombination component   of base current which is expressed as conduct-   ance for the sake of convenience in this   specification,Cπ:  parameter indicating component of base current   corresponding to variation of excessively   stored carriers,Cμ, g0 :   Parameters indicating base width modulation   according to collector voltage,gm :   mutual conductance, andCJE :   base-emitter junction capacity.______________________________________

In this case, if the variation of base current is taken as ib and the variation of emitter-base voltage as vbe, the parameters g.sub.π and C.sub.π are defined as follows: ##EQU2##

On the other hand, the current amplification factor hfe of an AC component is defined by hfe = I.sub. O /Ii in the case when an output is short-circuited, where Ii is the input current and IO is the output current. Now, if the complex frequency is taken as s, a voltage V across g.sub.π and C.sub.π in FIG. 2 is expressed as follows: ##EQU3## Further, since IO = gm V and normally C.sub.μ << C.sub.π , the following relation is obtained: ##EQU4##

Now, in an NPN-type transistor, g.sub.π is considered as being divided into a hole current component gp and an electron current component gn for the sake of convenience. That is,

g.sub.π  = gp + gn                            6.

From the equations (5) and (6), the current amplification factor hFE of DC component or the current amplification factor at a time of s = 0 is expressed as follows: ##EQU5##

In the transistor shown in FIG. 1, since its base transport factor β is made high as described previously, the recombination of electrons is small to satisfy the relation gn << gp. Accordingly, its hFE is given as follows: ##EQU6## However, in normal transistors including the transistor of this kind, reducing the recombination of holes, is not considered so that gp is relatively large. For this reason, as apparent from the equation (8), relatively high hFE can not be obtained.

The conductance components gp and gn are expressed as follows. At first, emitter current IE, collector current IC and base current IB are respectively given as follows:

IE = A(Jn + Jp )

IC = βAJn

IB = IE - IC

ib = a{jp + (1 - β)Jn }

where A is junction area, Jn is current density according to electrons injected from emitter into base, and Jp is current density according to holes injected from base into emitter.

Further, the following relations are obtained: ##EQU7##

A transistor with its Jp being reduced is disclosed in U.S. Pat. No. 2,822,310. In other words, the emitter is provided therein with a high resistive region whose thickness is selected smaller than the diffusion length of minority carriers thereby to reduce the current density Jp according to the diffusion of minority carriers in this emitter.

In this connection, the emitter injection efficiency γ is given as follows: ##EQU8##

Accordingly, the reduction of Jp is equivalent to the enhancement of γ.

SUMMARY OF THE INVENTION

It is a main object of this invention to provide a bipolar transistor circuit in which the cut-off frequency is high and the current amplification factor hfe in a range between intermediate and high frequencies is higher than those of the prior art embodiments mentioned above.

The other objects, features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawing.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a schematic enlarged cross-sectional view showing a prior art transistor,

FIG. 2 is a hybrid π-type equivalent circuit of the prior art transistor shown in FIG. 1,

FIG. 3 is a schematic enlarged cross-sectional view showing one example of a transistor according to this invention,

FIG. 4 is a schematic enlarged cross-sectional view showing another example of a transistor according to this invention, and

FIG. 5 is a circuit diagram showing an emitter-grounded type circuit using a transistor according to this invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A description will hereinafter be given of one embodiment of this invention with reference to FIG. 3. The illustrated example is of an NPN-type transistor, in which a semiconductor substrate 20 is provided therein with a first semiconductor region or emitter region 1 of first conductivity type, an N-type in this example, having high resistivity, a second semiconductor region or base region 2 of second conductivity type an P-type which is disposed adjacent thereto, and a third semiconductor region or collector region 3 of first conductivity type namely N-type having high resistivity which is disposed adjacent to the second region 2. A first PN-junction or emitter junction Je is formed between the first and second regions 1 and 2, and a second PN-junction or collector junction Jc is formed between the second and third regions 2 and 3. In the example of FIG. 3, a high impurity concentration region 1a of the first conductivity type or N-type is provided in the first region spaced from junction Je by a distance WE to form an low-high impurity concentration junction 7(L-H) junction in the region 1, thus providing a potential barrier substantially parallel to and spaced from the emitter-base junction Je by a distance smaller than the diffusion length Lp of minority carriers (holes) injected into the region which form the region 2 when the transistor is forwardly biased. By selecting a difference of impurity concentration sufficiently great between 1A and region 1, and by having the width of the high impurity concentration region 1A smaller than region 1, as hereinafter described, a potential barrier is obtained at 7 having an energy level higher than 0.1 eV and a built-in-field larger than 103 V cm.

On the high impurity concentration region 1a of the first region, and the second and third regions 2 and 3, there are deposited first, second and third electrodes, that is, emitter, base and collector electrodes 5e, 5b and 5c, respectively, to lead out therefrom first, second and third terminals, that is, emitter, base and collector terminals E, B and C, respectively.

The manufacturing method of this semiconductor device will be described as follows. On an N-type semiconductor substrate 21 of high impurity concentration mainly forming a low resistive region 3a of the third region 3 there is epitaxially grown a semiconductor layer 22 of low impurity concentration forming the third region 3 of the same N-type. Then, on the semiconductor layer 22 there is selectively formed the second region 2 of P-type at a thickness of about 0.1μ (micron) with the concentration in an order of about 1016 to 1018 atoms/cm3 by diffusion or ion implantation. Next, on the semiconductor layer 22 there is epitaxially grown an N-type semiconductor layer 23 of low impurity concentration in an order of 1015 atoms/cm3 at a thickness of about 0.2μ which mainly forms therein the first region 1, thus the semiconductor substrate 20 being constructed. Then, a P-type impurity is selectively diffused across the semiconductor layer 23 in an annular shape with a relatively high impurity concentration in an order of 10.sup. 20 atoms/cm3 to form an extending region 2A which is used for leading out the electrode 5b for the second region 2. Next, the N-type region 1a of high impurity concentration in an order of about 1020 atoms/cm3 is formed in the first region 1 with a thickness of about 0.1μ by diffusion, for example, solid diffusion from the polycrystal semiconductor layer. Further, an extending portion 3A of the low resistive region 3a is formed outside the region 2A across the semiconductor layers 23 and 22.

Thus, since the impurity concentration at portions of the regions 1 and 2 forming the junction Je is selected low, the hole diffusion length Lp at this portion is large. When the built-in-field at the potential barrier 7 is sufficiently large in magnitude, the diffusion length Jp is expressed as follows: ##EQU9## where Dp is diffusion constant of holes in the emitter and Pn is hole density in the emitter at equilibrium. The equation (12) reveals that the value of Jp is reduced by a ratio of WE /Lp as compared with a case of no potential barrier.

An example of a transistor having a potential barrier in its emitter, using a hetero junction except the example using the L-H junction shown in FIG. 3. In other words, an N-type emitter region with large Lp is provided adjacent to a P-type base region and a wide bandgap region is provided between the emitter region and the substrate surface to form a hetero junction. At this hetero junction, a potential barrier for holes is formed in the balance band.

The emitter region is composed of a semiconductor in which the width of bandgap is not narrower than that of the base region.

The wide bandgap region is formed by an N-type semiconductor region in opposition to the emitter junction between the emitter and base regions so as to have a shape such as preventing holes from being recombined at the semiconductor surface. In this case, the emitter injection efficiency can be further enhanced by providing in the conduction band a potential barrier such as to accelerate electrons. The height of the potential barrier for holes at the hetero junction is desired to be more than 0.1eV.

An idea using the hetero junction in a transistor is disclosed in, for example, Proc. IRE, vol. 45, p1535 (1957) in which a transistor as formed in therein an emitter-base junction. However, it was difficult to form a good hetero junction between P-type and N-type semiconductor regions.

Another embodiment of this invention using the hetero junction is shown in FIG. 4. On an N+-type collector substrate 41 in which galium arsenide GaAs is doped with tin Sn at high concentration, an N--type semiconductor layer 42 of GaAs mainly forming a collector region 34 is formed by liquid epitaxial growth. Then, this layer 42 is partially doped with germanium Ge to form a P-type base region 33. However, the base region 33 may be formed with an epitaxial layer of GaAs. On the base region 33 there are respectively formed by liquid epitaxial growth an N--type semiconductor layer 43 of GaAs serving mainly as the emitter region 32 and an N-type semiconductor layer 44 of Ga1 -x Alx As doped with Sn which mainly forms a wide bandgap emitter region 31 and consists of a different kind of material from that of the semiconductor layer 43. Germanium Ge is diffused through the semiconductor layers 43 and 44 so as to reach the base region 33 to form a P-type base contact layer 45. On the region 31 of the semiconductor layer 44 and on the substrate 41 there are respectively formed an emitter electrode 36e and a collector electrode 36c by Au-Ge alloy, and on the base contact layer 45 there is formed a base electrode 36b by Au-Zn alloy.

According to the above described construction, in addition to the formation of a good hetero junction 35 in the emitter, the hetero junction in the base contact layer 45 blocks electrons to improve its base transport efficiency and noise characteristics, and further the hetero junction between the layers 43 and 44, which are applied with the collector potential, reduces the surface recombination of electrons to improve its current characteristics and noise characteristics.

As described above, with the present invention, the potential barrier 7 as shown in FIG. 3 is provided in the emitter region or the first region 1 opposite to the emitter junction Je with a distance therebetween smaller than the hole diffusion length Lp thereby to reduce the current density Jp and, as apparent from the equation (9), to reduce the conductance component gp. Particularly, in this invention, the following relation is established:

gp < 10 gn                                       13.

That is, the base operation of the base region 2A is cancelled while only the region 2 is utilized as the base operative region, thus the base transport efficiency β is enhanced. Accordingly, the conductance component gn is decreased because the electron recombination in the region 2 is decreased. However, when gp is larger than gn, the conductance g.sub.π is determined by gp. For this reason, in the present invention, the values of the conductance components gp and gn are selected to satisfy the relation gp < 10gn. As a result, the value of g.sub.π is made quite small as compared with the prior art. If gn is made as a reference, it is desired to decrease gp to an extent substantially the same as gn. In order to make gp quite small, the built-in-field at the potential barrier 7 is made quite large, for example, about 104 V/cm. Accordingly, as apparent from the equation (7) the factor hFE can be substantially enhanced according to this invention.

However, practically in the higher frequency range, the term s (C.sub.π + C.sub.μ + CJE) of the equation (4) becomes effective to change the phase and hence the absolute value |hfe | is decreased. If the highest value of a cut-off frequency at which the value of hfe is decreased to 1/√2 the highest value is taken as fT (= ωT /2π), the following equation is obtained: ##EQU10## (In this case, C.sub.μ can be neglected since it is normally small.) If g.sub.π is small, ωT tends to be lowered.

In the present invention, though g.sub.π is made small in order to increase hFE as mentioned above, the term of capacitance in the equation (14) is made quite small thereby to enhance ωT or the cut-off frequency fT. In other words, with the construction of this invention, since the both regions forming the first junction or emitter junction Je, that is, the first and second regions 1 and 2, particularly the first region 1 is selected low in concentration, CJE can be selected quite small.

On the other hand, C.sub.π will be considered. Now, C.sub.π is divided into a base stored component C.sub.πB and an emitter stored component C.sub.πE. That is, the following equation is established:

C.sub.π  = C.sub.πB + C.sub.πE          15.

if minority carrier charges stored in the base and emitter are taken as gB and gE, and the widths of the base and emitter (having large Lp) are taken as WB and WE, respectively, the relationships thereamong are expressed as follows: ##EQU11## In this case, however, the assumption is given as follows:

Ln > WB and Lp > WE 

as will be obvious from these equations (16) and (17), C.sub.πB and C.sub.πE, that is, C.sub.π can be made small by reducing the base width WB and the emitter width WE. An idea to make WE small is described in the above mentioned U.S. Pat. No. 2,822,310. However, since Lp is selected large in order to make hFE large, C.sub.πE can not be made sufficiently large (If Lp < WE is satisfied as in the normal case, C.sub.πE is small irrespective of WE). In this invention, as mentioned above gp is made small thereby to introduce the following relation:

C.sub..sub.πE < C.sub.πB                        18.

that is, from the equations (9) and (17) the following relation can be established: ##EQU12## As a result, it is noticed that if gp is made small, C.sub.π E can be made smaller than C.sub.πB.

As described above, in the present invention, the equations (13) and (18) are satisfied thereby to provide a circuit wherein the cut-off frequency fT is high and hfe is high in the middle and high frequency ranges.

In the above described embodiments, the NPN-type transistor is mainly employed, but it will be understood that the PNP-type transistor can also be used by selecting the respective regions to have the reverse conductivity types to those of the illustrated regions.

An emitter-grounded type circuit using the aforementioned transistor is shown in FIG. 5. In FIG. 5, reference character Rg represents a signal source impedance and Z denotes a collector load. In this invention, excepting the normal voltage during operation, the current driving operation can also be performed by making Rg large because of high input impedance of the transistor.

It will be apparent that a number of changes and variations can be effected without departing from the scope of the novel concepts of the present invention.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US2822310 *Apr 23, 1956Feb 4, 1958Philips CorpSemi-conductor device
US3591430 *Nov 14, 1968Jul 6, 1971Philco Ford CorpMethod for fabricating bipolar planar transistor having reduced minority carrier fringing
US3761319 *May 17, 1971Sep 25, 1973Philips CorpMethods of manufacturing semiconductor devices
Non-Patent Citations
Reference
1 *H. Kroemer, "Theory of Wide-Gap Emitter For Transistors," Proc. Ire, vol. 45, No. 11, pp. 1535-1537, TK5700I7, Nov. 1957.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4099987 *Jul 25, 1977Jul 11, 1978International Business Machines CorporationFabricating integrated circuits incorporating high-performance bipolar transistors
US4178190 *Oct 10, 1978Dec 11, 1979Rca CorporationMethod of making a bipolar transistor with high-low emitter impurity concentration
US4682196 *Dec 9, 1985Jul 21, 1987Kokusai Denshin Denwa Kabushiki KaishaMulti-layered semi-conductor photodetector
US4720735 *Aug 31, 1983Jan 19, 1988Nishizawa JunichiPhototransistor having a non-homogeneously base region
US4750025 *Jan 30, 1986Jun 7, 1988American Telephone And Telegraph Company, At&T Bell LaboratoriesDepletion stop transistor
US4841350 *Dec 9, 1987Jun 20, 1989Nishizawa JunichiStatic induction photothyristor having a non-homogeneously doped gate
US4905070 *Sep 2, 1988Feb 27, 1990Motorola, Inc.Semiconductor device exhibiting no degradation of low current gain
US4910562 *Apr 26, 1982Mar 20, 1990International Business Machines CorporationField induced base transistor
US5289043 *Jul 27, 1990Feb 22, 1994Texas Instruments IncorporatedSwitching system for selectively enabling electrical power to be applied to plural loads
US6252282 *Feb 9, 1999Jun 26, 2001U.S. Philips CorporationSemiconductor device with a bipolar transistor, and method of manufacturing such a device
US6894367 *Feb 14, 2003May 17, 2005Infineon Technologies AgVertical bipolar transistor
EP0232589A2 *Oct 30, 1986Aug 19, 1987SILICONIX IncorporatedZener diode
Classifications
U.S. Classification257/591
International ClassificationH01L29/00, H01L29/73, H01L27/00
Cooperative ClassificationC07C2101/14, H01L29/73, H01L29/00, H01L27/00
European ClassificationH01L27/00, H01L29/00, H01L29/73