|Publication number||US4072545 A|
|Application number||US 05/688,811|
|Publication date||Feb 7, 1978|
|Filing date||May 21, 1976|
|Priority date||Dec 3, 1974|
|Also published as||DE2541548A1, US4016587|
|Publication number||05688811, 688811, US 4072545 A, US 4072545A, US-A-4072545, US4072545 A, US4072545A|
|Inventors||Francisco H. De La Moneda|
|Original Assignee||International Business Machines Corp.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Non-Patent Citations (1), Referenced by (62), Classifications (25)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a division, of application Ser. No. 529,193 filed Dec. 3, 1974, now U.S. Pat. No. 4,016,587.
This invention relates to MOS devices and processes for making same.
In order to achieve higher circuit speed and density in integrated circuit field effect transistors, it is necessary to reduce both the horizontal and the vertical dimensions of the device. Experimental and analytical evidence indicates that the threshold voltage, VT, of IGFET's falls sharply as the source-drain spacing is reduced. Studies for example by F. H. De La Moneda, "Threshold Voltage from Numerical Solution of the Two Dimensional MOS Transistor", IEEE Transaction on Circuit Theory, Vol. CT-20, pages 666-673, Nov. 1973, show that in order to avoid this drop, it is necessary to compensate by scaling down both the horizontal and the vertical dimensions of the device for example by reducing the thickness of the gate oxide and the junction depth and, in addition, by scaling up the substrate doping level by some factor. However, reductions in gate oxide thickness and increased substrate doping have adverse side effects. It is well known that reduced oxide thicknesses diminish the reliability of the device. The threshold voltage and the junction capacitance increase with the square root of the doping concentration and therefore devices with increased doping concentration become impractical for faster circuit applications. In view of this, it is necessary to use high resistivity substrates for the formation of the smaller IGFET device and then later adjust the device parameters to reduce the detrimental influence of a high resistivity substrate on the threshold voltage. Such adjustments include ion implantation of the substrate, reduction of the oxide thickness, and reduction of the junction depth to the extent that such reduction is possible with conventional device fabrication processes. Conventional processes for fabricating insulated gate field effect transistors determine the junction depth by the initial drive-in cycle and subsequent heat cycles associated with oxidation steps. These conventional device fabrication processes are not capable of producing very shallow source and drain junctions necessary for IGFET's of reduced size.
It is an object of the invention to make an IGFET device in an improved manner.
It is another object of the invention to make an IGFET device having a high circuit speed and density in an improved manner.
It is still another object of the invention to make an IGFET device having high circuit speed and density with a reduced source and drain junction depth, in an improved manner.
It is still a further object of the invention to make an IGFET device having an improved contact to a very shallow junction source and drain.
An integrated circuit field effect transistor device is disclosed which has as its source and drain, epitaxial regions which are grown from the surface of the silicon substrate so as to protrude above same. The source and drain regions serve as low resistivity contacts and have very shallow junctions in the substrate region.
The reduced junction depth allows the device designer to reduce the channel length of the IGFET devive without requiring a compensatory reduction of the gate oxide thickness and/or an increase in the substrate doping concentration.
Two self-aligned source and drain device fabrication processes are disclosed. The first process yields a polysilicon field shield simultaneously with the growth of the epitaxial source and drain protrusions and the polysilicon gate region. The second process produces a field region composed of thermal silicon dioxide.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of the preferred embodiments of the invention, as illustrated in the accompanying drawings.
FIGS. 1A through 1K illustrate the sequence of operative steps necessary to fabricate the protruding source and drain IGFET device with a polysilicon field shield. FIG. 1J shows a cross sectional view of a completed IGFET device invention.
FIGS. 2A through 2P illustrate the sequence of operative steps necessary to fabricate the protruding source and drain IGFET device with thermal oxide in the field region. FIG. 2P is a cross sectional view of a completed IGFET device with the thermal oxide in the field region.
The process for fabricating the protruding source and drain IGFET device with a polysilicon field shield is illustrated in FIGS. 1A through 1J. An N-channel process will be used for illustrative purposes, however, the process is equally amenable to the production of P-channel devices.
FIG. 1A illustrates the starting wafer 2 of crystalline silicon having a background doping level of 1015 impurities per cm3.
FIG. 1B illustrates the first step in processing the silicon wafer 2 where the thermal silicon dioxide layer 4 is grown thereon to a thickness in the range of 500 × 10-8 cm.
FIG. 1C illustrates the first masking step wherein the silicon dioxide layer 4 is masked by a photoresist and the window regions 3 and 5 are etched from the silicon dioxide layer 4 exposing the wafer surface 2, by suitable photolithographic methods.
FIG. 1D illustrates the steps of growing the epitaxial and polycrystalline silicon layer 6 on the surface of the silicon dioxide layer 4 and the exposed areas of the silicon wafer 2. Those regions above the silicon dioxide layer 4 become polycrystalline silicon and those regions above the windows 3 and 5 become epitaxial layers of silicon having a crystalline orientation equal to that of the wafer 2. The polysilicon portions 7, 9 and 11 have a thickness of 1μ and the epitaxial regions above the windows 3 and 5 have a thickness of 1μ. The polysilicon layer regions 7 and 11 will form the polysilicon field shield in the finished device and the polysilicon layer region 9 will form the polysilicon gate region in the finished device. The epitaxial silicon region 13 above the window 3 will serve as the source and the region 15 above the window 5 will serve as the drain for the completed IGFET device.
FIG. 1E illustrates the step of depositing a silicon nitride layer 16 over the entire surface of the polysilicon/epitaxial silicon layer 6. FIG. 1E further illustrates the second masking step of etching out the region 18 and 20 around the polysilicon gate region 9 and the gate oxide 10 using a suitable etchant such as a suitable mixture of hydroflouric and nitric acids.
A shallow N+ conductive layer 22 and 24 can be formed between the self-aligned gate region 9 and the source 13 and drain 15 epitaxial contacts by means of ion implantation or diffusion of for example phosphorus.
FIG. 1G illustrates the use of a third mask to permit the etching out of a moat region 26 extending from the surface of the nitride layer 16 down to the surface of the silicon substrate 2, thereby defining nitride layer 28 on top of the source projection 13, nitride layer 30 on top of the polysilicon gate 9, and nitride layer 32 on top of the epitaxial drain protrusion 15. Thus the polysilicon gate 9, the source protrusion 13, and the drain protrusion 15 are electrically isolated from the polysilicon field shield region which is comprised of the portions 7 and 11 of the polysilicon layer 6 which surround the device.
FIG. 1H illustrates the use of a fourth mask to locate the self-aligned contacts to the drain protrusion 15, the source protrusion 13, and the gate 9 of the device. The nitride layer 16 is removed except for the regions 28, 30 and 32.
FIG. 1I illustrates the step of growing a silicon dioxide layer over all exposed silicon surfaces to insure that the gate 9, the source 13, and the drain 15 are electrically isolated from the field shield 7 and 11 and from each other. Since the oxide growth should not be more than 1500A, this heat cycle will not drive impurities from the epitaxial layer 13 and 15 and the ion implanted junctions 22 and 24 substantially deeper into the substrate 2. In the region of the substrate 2 immediately next to the gate 9, the doping concentration is controlled by the ion implantation step shown in FIG. 1F and does not need to be as high as that of the epitaxial layer 6 whose sheet resistivity must be as low as is possible. Therefore the junctions for the implanted regions 22 and 24 are shallower at their boundaries adjacent to the gate than are the junctions 17 and 19 underneath the epitaxial source 13 and drain 15 layers, respectively.
FIG. 1J dip etch with a suitable etchant such as hot phosphoric acid is now employed to remove the nitride layers 28, 30 and 32 so as to form the self-aligned contact regions for the source 13, gate 9, and drain 15 regions, respectively. A layer of aluminum is then deposited upon all exposed surfaces of the configuration shown in FIG. 1I.
FIG. 1K shows the IGFET device after the use of mask number 5 to define the aluminum interconnection pattern. The etching step delineates the source contact 44 for the source protrusion 13, the gate contact 36 for the polysilicon gate 9, and the drain contact 38 for the drain protrusion 15.
Note that the vertical elevation of the silicon source contact 13 and silicon drain contact 15 are not to scale. The difference in the elevation between the interface of silicon contact 13 and metal 44 and the elevation of the upper surface of polysilicon field shield 11 is approximately equal to the thickness of the gate oxide 10. Thus, the top surface of the finished device is almost planar, which is very desirable for projection printing.
This process has the advantage of decoupling the fabrication of the source junction 22 and the drain junction 24 from their respective conductive interconnections 13 and 15 by using ion implantation for the formation of the self-aligned junctions 22 and 24 and epitaxial deposition for the source protrusion 13 and drain protrusion 15. It is therefore possible to fabricate junctions and interconnections whose parameters are individually tailored for best device performance. The junctions are very shallow and have low junction capacitance while the interconnections have low sheet resistivity, low isolation capacitance, and are deep enough for reliable metallurgy.
Where the device application requires a field oxide instead of a polysilicon field shield, the following process will be useful.
FIG. 2A shows the starting wafer 50 of crystalline silicon having a P type background doping of 1015 impurities per cm3. A blanket boron implantation 52 can be made at this time to avoid inversion layers between devices.
FIG. 2B illustrates the step of depositing a silicon nitride layer 54 on top of the semiconductor substrate 50.
FIG. 2C illustrates the use of a first mask to delineate the source window by means of the nitride mask 56 and the drain window by means of the nitride mask 58 which are left after the etching process.
FIG. 2D illustrates the step of growing the field oxide layer 60 over all exposed regions of the silicon wafer 50. The nitride mask 56 and 58 prevents the growth of oxide at the source and drain windows.
FIG. 2E illustrates the step of using a second mask to define the gate area between the nitride mask 56 and 58. The alignment of the second mask is not critical since the objective is to remove the portion 62 of the oxide layer 60 which is separated from the field portion of the oxide layer 60 by the width of the nitride mask 56 and 58. The etching and removal of the oxide portion 62 leaves the gate region 64 of the wafer surface 50 exposed. If the threshold voltage of the resulting device is to be adjusted using ion implantation, the photolithographic mask number 2 can also be used to block out the implantation from the field regions 60.
FIG. 2F shows the next step of growing a thin oxide 66 in the gate region 64.
FIG. 2G illustrates the next step of dip etching to remove the nitride mask layers 56 and 58 from the surface of the wafer 50.
FIG. 2H illustrates the next step of growing a layer of epitaxial silicon over all exposed surfaces. The silicon layer will be epitaxial in the source region 72 and the drain region 74 since it is formed over the exposed areas of the monocrystalline silicon substrate 50. The silicon layer will be in the polycrystalline phase in the region 68 and 70 over the field oxide region 60 and in the region 76 over the gate oxide layer 66. The polysilicon layer 68 will ultimately be the electrical contact to the source region 72 and the polysilicon region 70 will ultimately be the contact to the drain region 74. The polysilicon layer 76 will ultimately be the conductive gate electrode for the IGFET device.
FIG. 2I illustrates the next step of depositing a nitride layer 78 over all exposed surfaces of silicon.
FIG. 2J illustrates the use of mask three to etch the nitride and polysilicon so as to isolate the protruding source 72 and nitride layer 82 from the gate oxide 66, polysilicon gate region 76, and nitride layer 80 by the region 86. Mask number three also separates the protruding drain region 74 and nitride layer 84 from the gate oxide 66, the polysilicon gate region 76, and the nitride layer 80 by the region 88. Two choices are available for the configuration of the gate electrode. A moat similar to the one described in FIG. 1G can be etched around the gate polysilicon 76 as is shown in FIG. 2J or, as an alternative, the polysilicon region 76 for the gate can be extended out over the field oxide region as a gate contact. Although this second alternative consumes more silicon area, it offers an easier metallurgy configuration.
FIG. 2K illustrates the next step which is the implantation of phosphorus in the region 86 to self-align the source electrode 72 with the edge of the gate region 76 and the implantation of phosphorus in the region 88 to self-align the drain region 74 with the gate 76.
FIG. 2L illustrates the use of mask number four to define the windows where the subsequent metallurgy will contact the polysilicon region 68 for the source 72, the polysilicon region 70 for the drain 74, and the polysilicon region 76 for the gate. This technique is used in the recessed oxide process to contact the gate as disclosed by H. L. Kalter, et al in IBM TDB, Vol. 14, No. 10, March 1972.
FIG. 2M illustrates the step of growing a silicon dioxide layer 98 in the range 1000A to 2000A in thickness to seal the silicon surfaces left exposed with masks three and four.
FIG. 2N illustrates the step of removing the nitride layers 80, 82 and 84 with a dip etch so as to expose contact regions for the drain 72, the gate 76, and source 74.
FIG. 20 illustrates the step of depositing the layer of aluminum 100 over the substrate to contact the windows described in FIG. 2L, thereby forming the self-aligned gate, source and drain contacts.
FIG. 2P illustrates the fifth and last masking step of defining the aluminum interconnection pattern in the aluminum layer 100 thereby defining the source metallization 102, the gate metallization 104, and the drain metallization 106. It should be noted that by placing the source contact 102 and drain contact 106 on top of the field oxide 60, no special metallurgy is needed to avoid aluminum spikes that may short out to the substrate 50. FIG. 2P illustrates the completed IGFET device with a field oxide.
In a manner similar to the polysilicon field shield process of FIGS. 1A-1K, the disclosed process for thermal oxide field region of FIGS. 2A-2P has the novel feature of decoupling the fabrication of the source and drain junctions 90 and 92, respectively, from their conductive interconnections 72 and 74, respectively, by using ion implantation for the former and epitaxial deposition for the latter. It is therefore possible to fabricate junctions and interconnections whose parameters are individually tailored for best device performance. The junctions are very shallow and have a lower junction capacitance than in the prior art since the side-wall junction capacitance is substantially reduced. The side-wall is now embedded in the oxide layer 98, which is a dielectric. In addition, since an epitaxial layer is used to form the protruding source and drain, the interconnections have low sheet resistivity, low isolation capacitance, and are deep enough for reliable metallurgy.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.
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|U.S. Classification||438/294, 257/E23.164, 257/E29.04, 257/E29.255, 257/E21.43, 438/300, 257/900, 438/297, 438/489|
|International Classification||H01L27/088, H01L29/78, H01L29/08, H01L23/532, H01L21/8234, H01L21/336|
|Cooperative Classification||H01L29/78, H01L23/53271, H01L29/66628, H01L29/0847, H01L2924/0002, Y10S257/90|
|European Classification||H01L29/66M6T6F11D3, H01L29/78, H01L23/532M2, H01L29/08E2|