|Publication number||US4118784 A|
|Application number||US 05/762,695|
|Publication date||Oct 3, 1978|
|Filing date||Jan 26, 1977|
|Priority date||Feb 26, 1976|
|Also published as||DE2704641A1|
|Publication number||05762695, 762695, US 4118784 A, US 4118784A, US-A-4118784, US4118784 A, US4118784A|
|Inventors||Henri J. Nussbaumer|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Non-Patent Citations (1), Referenced by (6), Classifications (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to digital filtering techniques and, more particularly, to the devices with which it is possible to minimize the number of operations necessary to carry out a digital filtering operation.
Filtering a signal x(t) by a filter having an impulse response designated by h(t) results in a signal y(t) determined by a so-called aperiodic convolution operation between these two terms, i.e., y(t) = h(t) x(t) where y(t) is representative of the filtered signal.
When sampled signals are to be filtered, the above operation becomes ##EQU3## where YM IS REPRESENTATIVE OF THE SAMPLE OF ORDER M OF THE FILTERED SIGNAL,
an with n = 0, 1, 2, . . . , are representations of the filter coefficients which result from a sampling operation of h(t) and
xm-n is representative of the sample of order i = (m-n) in the signal to be filtered.
The higher the value of N, the better is the quality of the resulting filtering operation.
With reference to formula (A), it can be seen that the determination of the value of each of the samples of the filtered signal requires the carrying out of N multiplications and N-l addition. In practice, the multiplier device is usually expensive and, also, multiplication is a comparatively long operation. Therefore, the greater the number of multiplications to be performed to determine a representation of a sample ym, the slower will be the filtering operation. Also, it is to be noted that the frequency of occurrence of the samples xi at the filter input should be at least twice the highest useful frequency of the spectrum of signal x(t); it can easily be understood that this slow computation considerably limits the interest in the thus involved filter for the greater precision samples, and this, more particularly, is true when the signal has to be processed in real time.
In the development of digital filters, it has, therefore, been necessary to try to overcome the above-mentioned drawbacks and many solutions have been proposed. One proposed solution is to make use of the properties of some of the mathematical transforms and, more specifically, those which belong to the family of the discrete Fourier transforms (DFT). Such transforms have an advantage in that they verify the so-called convolution theorem. In other words, when designating by [AK ] and [XK ] the transforms of sets [an ] and [xi ], each of N terms, and by CK the terms resulting from multiplication CK = AK . XK, it has been demonstrated that the inverse transform of set [CK ] supplies terms cm resulting from the convolution of the set of terms [an ] with the set of terms [xi ], thereby making it possible to obtain samples ym of the desired filtered signal.
Now, the carrying out of both direct and inverse transforms requires only simple operations. More specifically, with transforms of the Mersenne or Fermat type, the only multiplications to be performed are those to supply terms CK from AK and XK. It results therefrom that the number of necessary multiplications is reduced by a factor N, which is a considerable saving.
However, the use of discrete transforms entails the carrying out of periodic convolutions (the so-called circular convolutions) whereas a filtering operation requires an aperiodic convolution. In the book by Gold and Rader entitled, "Digital Processing of Signals" (Chapter 7) published by McGraw Hill Company in 1969, there is disclosed one way to convert from the first type of convolutions to the second ones by dividing the stream of samples of the signal to be filtered into sample blocks of a given length, proceeding with circular convolution operations upon said blocks and, then, combining the results of the separate blocks. In this book, the authors define more specifically two processing methods, the first one being called the "overlap-add" method, and the second one being called the "overlap-save" method. The difference between these two methods is in the manner in which the data groups are formed before being submitted to circular convolution operations and, of course, how the results of these convolutions are combined.
When making use of either of these methods in a filtering operation, the length of each sample block is fictitiously increased either by appending thereto a sequence of zero terms (overlap-add) or by repeating part of the preceding block (overlap-save). Thus, when a N-coefficient filtering operation is desired, one has to process, at least, 2N-term sequences. This requires the use of a device for carrying out 2N-term transforms. Now there is a close relationship between the length of a transform and the size of the words processed by the same. Thus, when the transform is a 2N-term transform, the devices involved are usually considerably more complex than those which are involved in the processing of N term blocks.
It is then an object of this invention to provide a digital filter for the carrying out of transforms and which requires smaller and simpler devices than those found in the prior art.
This invention will be further described, by way of a preferred embodiment, with reference to the accompanying drawings:
FIG. 1 is a block diagram of the preferred embodiment of the filter according to this invention.
FIGS. 1A and 1B illustrate details of the blocks of FIG. 1.
FIGS. 2, 3 and 4 are other embodiments of this invention.
FIGS. 5, 6 and 7 illustrate details taken from FIG. 4.
FIG. 8 is another embodiment of this invention.
FIG. 8A illustrates details of structure of a block of FIG. 8.
As seen above, the use of discrete transforms of the DFT type makes it possible to perform circular convolutions. In other words, the normal transforms designated by [AK ] and [XK ] of successive terms [al ] and [xn ] are ##EQU4## with l, n, k = 0, 1, . . . , N-1.
It results therefrom that the inverse transform operation upon each of the blocks [CK ] where CK = AK ·XK, verifies the relationship ##EQU5## (exponent i is indicative that cm results from the processing of the ith block of N samples).
The first portion of expression (2) belongs to sample ym of the filtered signal whereas the second portion belongs to ym+N. If it is possible to separate these two terms and complete them, terms ym and/or ym+N can be obtained.
To this end, let us suppose that the same data and coefficient blocks are also subject to a different circular convolution with a modified DFT type transform. More specifically, let us suppose that: ##EQU6## Designating by dm the terms resulting from the inverse transform of [ZK · BK ], there is obtained: ##EQU7##
Since the product of two DFT transforms is a DFT transform of a circular convolution, it can be seen that q+n-m is operated modulo N.
When W is chosen so that WN =1, the results are that ##EQU8##
This result can be summarized into the formula ##EQU9##
The same remark that was made with respect to expression (2) can be made here, i.e., dm contains one portion which belongs to sample ym, with the other portion belonging to the sample ym+N except for the fixed coefficient RN. For the generation of the complete values of these filtered signal samples, it will, therefore, be possible to combine the processing operations of two consecutive blocks of N samples each in the signal to be filtered, such as, for instance, the ith and (i-1)th blocks.
One can write ##EQU10##
Many values of RN can be significant since with them it is possible to obtain the desired filtered samples in a simple way. It should be noted that, for instance, R can be chosen so that RN =-1. This can be obtained more particularly when R=-1 and use is made of the Mersenne or Fourier transforms, where N is odd and W=2 or W=e-j (2π/N), respectively. But, Fourier or Fermat transforms could also be used, where N is even and
W = e-j (2π/N), with j = √-1 or W=2 respectively,
if R is chosen so that R2 =W. In that case, blocks having an even number of samples N will be used.
The representation of the mth sample of the filtered signal resulting from the processing of the ith block of N samples, namely ym iN, can be obtained by summing the terms cm i + cm i-1 + dm i - dm i-1.
It is obvious that these summations can be performed in many different ways. Indeed, (cm i + cm i-1), on the one hand, and (dm i - dm i-1) on the other hand, can be grouped; in that case, the circuit performing the combination cm i + cm i-1 + dm i - dm i-1 would be comprised of two delay elements and three adders. But the terms can be grouped otherwise, for instance, by forming (cm i + dm i) and (cm i - dm i); in that case, a single delay circuit operating upon (cm i - dm i) would be sufficient to deduce cm i-1 - dm i-1 therefrom.
In either case, the filter is the one shown in the block diagram in FIG. 1. In this device, the stream on circuit 1 of the samples of the signal to be filtered is divided into blocks of N consecutive samples which are applied simultaneously to two circular convolution generators (CCG) 2 and 3. These convolution generators include transform generators 4 and 5. Generator 4 produces the terms ##EQU11## on output 6 whereas generator 5 produces terms ##EQU12## on output 7.
A read only memory (ROM) 8 is utilized to store terms (1/N)AK and 1/N)BK where ##EQU13## wherein the coefficients an are those of the filter function to be implemented and are presented on lines 10 and 11, respectively. Multipliers 12 and 13 receive the signals on outputs 6 and 10 and on outputs 7 and 11, respectively, to develop the terms (1/N)AK ·XK and (1/N)BK ·ZK which are supplied over respective outputs 14 and 15 to a first 16 and a second 17 generator generating transforms and which are the inverse of those of generators 4 and 5, respectively. The first generator 16 performs operations ##EQU14## and, therefore, produces cm i terms on output 18, whereas the second generator 17 generates terms dm i on its output 19 by performing operations ##EQU15##
Terms cm i and dm i, then, are introduced into combining device 20 which will generate the terms 2ym on output 21 by performing the summation
2ym = (cm i + cm i-1 dm i - dm i-1) (5)
In practice, the terms AK /2N and BK /2N will be stored in ROM 8 so that the output will be the terms of ym and not 2ym.
Circuit 20 can be implemented according to the schematic diagram shown in FIG. 1A. It would, in this case, be comprised of two delay elements 22 and 23, each having a delay equivalent to the transfer time of one block of N terms, cm or dm, two adders (ADD) 24 and 26 and one subtractor (SUB) 25. When the inputs of delays 22 and 23 are receiving cm i and dm i, respectively, the outputs thereof on lines 28 and 29 will be producing cm i-1 and dm i-1 . Adder circuit 24 and subtractor 25 will produce terms cm i + cm i-1 and dm i - dm i-1 , on outputs 30 and 31, respectively, and adder 26 will produce the terms ym on output 21.
However, other circuits equivalent to the circuit shown in FIG. 1A could also be utilized. FIG. 1B schematically illustrates a combining device 20 which is comprised of a single delay element 33; this element delays the terms cm i - dm i supplied to its input 34 by a subtractor 35 receiving the input terms cm i and dm i on its plus and minus inputs, respectively. The output 36 of delay 33 carries the terms cm i-1 - dm i-1. The cm i and dm i inputs are also supplied to an adder 37 whose output 38 is combined with output 36 in another adder 39 to provide the terms ym on output 21.
Other equivalent forms exist. For instance, it can be shown that, because of the fact that some operations can be permuted, some elements of combining circuit 20 can be brought into the data flow before the carrying out of the transforms. When so placed, the structure of the filter will resemble that shown in FIG. 2. The samples of the signal to be filtered on input line 1 are delayed by the time of one block of signals in delay unit 41. The output terms xn on output 42 are then combined additively in adder 43 and subtractively in subtractor 44 to form the series Xn = xn + xn+N and series Zn = xn+N - xn. Data blocks [Xn ] and [Zn ] on outputs 45 and 46 are introduced into circular convolution generators 2 and 3, respectively, as in FIG. 1, one performing the so-called normal transform operation in generator 4 and the other one performing the so-called modified transform operation in generator 5. The convolution generators 2 and 3 are also comprised of multipliers 12 and 13 and the inverse transform generators 16 and 17 of the normal and modified types, respectively. For this structure, it is then sufficient to add term-to-term the outputs of CCG 2 and CCG3 on outputs 18 and 19 in an adder 47 to obtain samples ym of the filtered signal.
Furthermore, when R is chosen as equal to -1, expression (5) can also be written: ##EQU16## where i is representative of the index of the data block to which the terms correspond.
Since the sign of (-1)m is independent of K, the operations
[XK i ·AK i + XK i-1· AK i-1 + (-1)m BK i· ZK i - (-1)m BK i-1 ·ZK i-1 ]
can be performed before proceeding to the inverse transform.
The structure of the schematic diagrams shown in FIGS. 1 and 2 can, therefore, be simplified so as to be comprised of a single inverse transform generator. This elimination of an inverse transform generator requires the addition of only one inverter and one switch, as shown in the diagram of FIG. 3 which is derived from FIG. 1. The device shown in this figure is similar to the upper half of FIG. 1 and includes the input 1 to which the samples xn are applied in blocks of N terms. These blocks are simultaneously sent to the two transform generators 4 and 5, generating XK and ZK, respectively. The terms so obtained are introduced into multipliers 12 and 13 which also receive terms (1/2N)AK and (1/2N)BK from a ROM 8 and supply (1/2N)AK i XK i and (1/2N)BK i ZK i, on outputs 14 and 15, respectively, when the sample block of order i is processed. The use of delay circuits 50 and 51 each providing an output delay equivalent to the processing time of one sample block will enable the present output on line 14 to be additively combined with the delayed output from delay 50 in adder 52 and the output on line 15 to be subtractively combined with the output of delay 51 in subtractor 53 to provide the terms ##EQU17## at the output 54 of adder 52 and the terms ##EQU18## at the output 55 of subtractor 53
The terms coming from subtractor 53 are taken either directly from output 55 or are taken from the output 56 of an inverter 57 receiving output 55, according to whether the m parameter of the sample ym to be generated is even or odd. The selection is made by the switch 58 controlled by the factor m and the output of switch 58 is one input of an adder 59 which also receives the output of adder 52. The output of adder 59 is the input of an inverse transform generator 60 whose output on line 21 is the desired samples ym.
It is possible to simplify this filter even more when R=-1, for then ##EQU19##
Under those conditions, transform generators 4 and 5 need only half the required working power when connected according to the schematic diagram shown in FIG. 4. This device includes a switch 70 controlled by a counter 71 which sends the even order of samples x2n in each block of samples to transform generator 72, which generates on its output 74 the terms ##EQU20## and sends the odd order samples x2n+1 to transform generator 73 which generates on its output 75 the terms ##EQU21## An adder 76 is connected to sum the outputs of generators 72 and 73 to produce ##EQU22## Similarly, a subtractor 77 is connected to the outputs of generators 72 and 73 to subtractively combine the outputs to produce ##EQU23##
These XK and ZK are the same as the output terms of transform generators 4 and 5 of FIG. 3 and they are further processed in the same manner.
The rest of the device of FIG. 4 is in every respect similar to the lower part of the device shown in FIG. 3. It can, therefore, be seen that the computing power necessary in generators 72 and 73 need be only half of that required in generators 4 and 5.
The filter illustrated in FIG. 4 can be implemented in many different ways and, more specifically, a preferred embodiment can be designed as diagrammed in FIG. 5, where it has been assumed that the utilized transform generators are of the Mersenne type. The device shown in FIG. 5 includes a transform generator 81 which receives samples xn on line 1 and which acts, alternatively as the transform generators 72 or 73 of FIG. 4 as controlled by the state of the synchronization signal t1 on line 82, i.e., as signal t1 assumes a logic level "1" or "0." For a logic level of "1", generator 81 will produce the terms ##EQU24## and for logic level "0," it will produce the terms of ##EQU25##
These terms will be supplied to a switch 83 in the following order ##EQU26##
These output terms are alternatively switched by a t2 control signal on line 86 into either shift register 84 of a length corresponding to two words, or into one word long shift register 85. The data flow through shift registers 84 and 85 is under the control of timing signals t4 and t5, respectively, on lines 87 and 88. The term in register 85 may be sent either directly through a gate 89 or inversely through an inverter 90 under the control of a timing signal t3 on a line 91 or t3 on a line 92, into adder 93 which is operating modulo 2N -1. The output of adder 93 is alternately the term XK or term ZK and these terms are sent to multiplier 94 which, also alternately receives the terms of (1/2N)AK and (1/2N)BK from a ROM 95 and alternately generates the terms of (1/2N)AK XK and (1/2N)BK ZK on its output 96. The terms coming from multiplier 94 are delayed in a buffer 97 for a time corresponding to one block. The use of an inverter 98 controlled by timing signal t6 on line 99 and a gate 100 controlled by signal t6 on line 101 makes it possible to enter the delayed term from buffer 97 either inversely or true into an input of a modulo, 2N -1 adder 102 to be added to the term on line 96 to generate the terms ##EQU27## alternatively. The terms coming from adder 102 on line 103 are sent through a switch 104 controlled by a timing signal t7 on a line 105 to an assembly comprised of one word length shift register 106 controlled by timing signal t8 on a line 107 to feed a one word length delayed term to an input of modulo 2N -1 adders 109 and 110 or alternately, directly from switch 104 to another input of adder 110 and complementally through an inverter 111 to the other input of adder 109. These adders 109 and 110 generate the terms ##EQU28## respectively. The samples ym of the filtered signal on line 21 are then generated by inverse transform generator 112, similar to generator 81, controlled by timing signal t9 on line 113 and receiving the outputs of adders 109 and 110.
The timing signals t1 through t9 are provided by a ROM 114 addressed by a counter 115 driven by a clock signal on a line 116.
Generator 81 must carry out operations of the type ##EQU29## since it has been assumed that the utilized transforms were of the Mersenne type. Therefore, the simple thing to do would appear to consist in weighting each sample by the corresponding powers of two, which, in the binary form, necessitates bit order shifts only, and accumulating the so-weighted terms. It is, however, more economical to proceed otherwise.
In the Mersenne transforms, N is a prime number, and the exponents of W=2 are taken modulo this prime number N. Therefore, when K varies from 0 to N-1, the exponents of W assume each of the integral values from 0 to N-1 only once. A single multiplication-by-two circuit, therefore, can be used. Let us suppose, for instance, that sample blocks are to be processed wherein N=5. The transforms will be performed modulo p=25 -1 and the exponents of W will be chosen modulo 5. It results therefrom that
X0 = X0 + x1 ·20 + X2 ·20 + x3 ·20 + X4 ·20
x1 = x0 + x1 ·2 + x2 ·22 + x3 ·23 + x4 ·24
x2 = x0 + x1 ·22 + x2 ·24 + x3 ·2 + x4 ·23
x3 = x0 + x1 ·23 + x2 ·2 + x3 ·24 + x4 ·22
x4 = x0 + x1 ·24 + x2 ·23 + x3 22 + x4 ·2 ##EQU30##
It can be observed that the powers of 2, namely 20, 21, 22 23, and 24 are sequentially assigned to weight the terms XK in the X + Z terms as follows: ##EQU31##
The Mersenne transform 81 can, therefore, be implemented according to the schematic diagram in FIG. 6. The samples xn of the signal to be filtered on input 1 are introduced into a one-word capacity buffer memory 120, through a switch 121, They are sent from output 122 of buffer 120 to those storage locations in a random access memory (RAM) 123 which store terms ##EQU32## Ram 123 has a storage location for each term and the terms are read out in a predetermined order by clock pulses on line 124. The first terms read out will be those which contain the value xn and the xn value will be entered on the RAM's write cycle through an adder 125. On later read out cycles, the stored value in RAM 123 will be passed through switch 126 by timing signal t1,3 on line 127 to a second input of adder 125 where it will be combined with a later weighted value of xn. After all of the unweighted xn have been entered into locations of RAM 123, the xn is sent from buffer 120 to shifter 128 where it is doubled by shifting its bits by one position leftward and the doubled xn is reinserted into buffer 120 through switch 121. The value 2xn is then added in adder 125 to the contents of those storage locations in RAM 123 which are to receive it. The procedure goes on this way until all the terms ##EQU33## are formed in RAM 123 and these terms are then read from RAM 123 through switch 126 to output line 129 in the following order ##EQU34##
Inverse transform generator 112 of FIG. 5 is similar to generator 81 in principle but it has two inputs, one coming from adder 109 and the one one, from adder 110. Elements 121, 128, and 121 of FIG. 6 must, therefore, be duplicated, as shown in FIG. 7. The output of adder 109, FIG. 5, is set to switch 131, buffer 130 and shifter 138 for doubling whereas the output of adder 110 drives similar switch 141, buffer 140 and doubling shifter 148. The outputs 132 and 142 of buffers 130 and 140 are alternate inputs to an adder similar to adder 125, FIG. 5, through a switch 139. The rest of the inverse transform generator 112 is comprised of elements similar to RAM 123 and switch 126 as shown in FIG. 6.
It has been shown above that a comparatively simplified digital filter could be designed for dealing with blocks of samples, which blocks are not artificially lengthened. This is done by the processing of said blocks of samples through two parallel channels, each of which performs a different circular convolution. To this end, one of the channels operates according to a normal DFT type transform, and the other one operates with a modified transform operation of the type: ##EQU35## When combining the terms given by the two circular convolutions, it has been shown that the desired filtered signal samples may be obtained in association with parasitic terms. It has also been shown that these parasitic terms could be eliminated by a judicious choice of parameter R. By way of example, the case with RN =-1 has been mentioned. It is obvious that other parameters R can be chosen but their usefulness will depend on the complexity of the combination circuits of the two circular convolutions required. In the particular case of the Fourier transforms, an interesting choice is to use R=21/N for, then, RN will assume a simple value with RN =2 and the multiplications by the powers of R are multiplications by real numbers whereas when choosing R=W1/2, the multiplications by powers of R are multiplications by complex numbers.
It may, sometimes, be of interest to combine more than two simultaneous circular convolutions for the filtering operation. By way of example, let us suppose that two modified circular convolutions, one with RN =-1, the other one with RN =j, where j = (-1)1/2, are performed on each of the blocks. For the latter, transforms in the form ##EQU36## can be chosen.
By defining terms Xk, ZK and YK as being the transforms of terms [xn+N + Xn ], [xn+N - xn ]and [xn+N - jxn ], respectively, one is able to develop the digital filter shown schematically in FIG. 8. Samples xn on input 1 are delayed by the time for one block of samples, namely by N sample times in delay 150 so that samples xn and xn+N can be utilized simultaneously. These terms are simultaneously introduced into three circular convolution generators 151, 152 and 153. Generator 151 is comprised of a normal transform generator 154 which generates the terms ##EQU37## multiplier 155 which receives the above terms and also receives terms (1/2N)AK, from a ROM 156 and an inverse transform generator 157 which generates the terms ##EQU38## from the output terms of multiplier 155.
The other generators are built in a somewhat similar way to that of generator 154 with the exception that generator 152 makes use of a first modified transform function with a parameter Rn such that RN =-1, and produces terms dm whereas generator 153 makes use of a second modified transform function with a parameter Rn such that RN =j and produces terms em. The outputs of these three circular convolution generators are then combined together in circuits 158 in order to give the terms of ##EQU39##
ym i = 1/4 [2j(em i - dm i) + (1-j) (cm i - dm i) -2j (em i-2 -dm i-2) + (1+j) (cm i-2 -dm i-2)] (8)
Nc - rom coefficient memory 156 can be common to the three convolution generators to which it supplies the normal transforms (AK) or the modified transforms (BK and UK) of the filter coefficients [an ].
Thus, it can be observed that from the terms produced by the three circular generators 151, 152, and 153 two consecutive blocks of N samples of the filtered signal can be obtained, as shown in FIG. 8 where terms cm, dm, and em are combined to supply samples yi and yi+1, consectively.
Of course, this filtering approach is of practical interest only if the combining circuits 158 performing operations (7) and (8) can be implemented in a simple manner. This can be the case when the transforms to be implemented are of the so-called Fermat type. The transform coefficient W can be advantageously chosen equal to four and each of the operations will be performed modulo 2q +1 with q=2t. In that case, the factor R utilized in transform generator 152 will be chosen equal to W1/2 =2, whereas the factor utilized in transform generator 153 will be W1/4 =21/2. But the Fermat transform is of even greater interest since the factor j, where j = (-1)1/2, has a real value in the corresponding digital system. Indeed, (2q) modulo 2.spsb.q+1 =-1, whence j= 2q/2 = 22.spsp.t-1. This makes it possible to have no discrimination between the real and imaginary portions of the terms processed in combining circuit 158, which considerably simplifies this device. FIG. 8A illustrates an embodiment of circuits 158. It is assumed for this circuit that the terms produced by the circular convolution generators of the device shown in FIG. 8 are
cm i /2, dm i /2, and em i /2.
The divisions by two can be obtained by halving the coefficient terms before they are stored in ROM 156 or by a one order shift to the right of the binary value representations of the output terms. Term cm i /2 on input 160 is simultaneously applied to the additive input of a subtractor 163 and to an input of adder 164. Term dm i /2 on input 161 is simultaneously applied to the other input of adder 164 and to the subtractive inputs of subtractor 163 and a second subtractor 165. Term em i /2 on input 162 is applied to the additive input of subtractor 165. The output of subtractor 163 is multiplied by two in a multiplier 166 and by (1-j) in a multiplier 167, whereas the output of subtractor 165 is multiplied by 2j in a multiplier 168. The outputs of multipliers 167 and 168 are added together in an adder 170. The outputs of multiplier 166, adder 170 and adder 164 are transmitted to shift registers 171, 172, and 173, respectively, to introduce a delay corresponding to two blocks of terms in shift registers 171 and 172 and to one block in shift register 173. The output of shift register 172 is subtracted from that of register 171 in a subtractor 175 whose output is added to the output of adder 170 in an adder 176. The outputs of adder 176 and shift register 173 are connected to a two-position switch 177. When in position 1, the switch 177 supplies to output 21 terms ym i which result from the processing of the ith block of N samples and in position 2, it supplies terms ym i+1 which result from the processing of the following block.
It is to be understood that the preceding description has been given as a preferred embodiment only and that numerous alterations can be developed without departing from the scope of this invention as set out in the following claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3679882 *||Jun 11, 1970||Jul 25, 1972||Ibm||Fourier digital filter or equalizer and method of operation therefor|
|US3925646 *||Apr 19, 1974||Dec 9, 1975||Battelle Memorial Institute||Information and process control enhancement system employing series of square wave components|
|US4006351 *||Nov 11, 1974||Feb 1, 1977||James Nickolas Constant||Recursive filter implemented as a matched clutter filter|
|1||*||C. M. Rader, "Discrete Convolutions via Mersenne Transforms", IEEE Trans. on Computers, vol. C-21, No. 12, Dec. 1972, pp. 1269-1273.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US4410955 *||Mar 30, 1981||Oct 18, 1983||Motorola, Inc.||Method and apparatus for digital shaping of a digital data stream|
|US4882668 *||Dec 10, 1987||Nov 21, 1989||General Dynamics Corp., Pomona Division||Adaptive matched filter|
|US4918742 *||Apr 22, 1988||Apr 17, 1990||The Boeing Company||Image processing using multi-pass convolution with small kernels|
|US5193173 *||Oct 30, 1989||Mar 9, 1993||Hitachi, Ltd.||Method and device for storing data subjected to dispersion processing|
|US5270953 *||Aug 31, 1992||Dec 14, 1993||Rockwell International Corporation||Fast convolution multiplier|
|US5956262 *||Mar 12, 1996||Sep 21, 1999||Thomson Multimedia S.A.||Digital filtering device|
|U.S. Classification||708/315, 708/321|