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Publication numberUS4188620 A
Publication typeGrant
Application numberUS 05/959,097
Publication dateFeb 12, 1980
Filing dateNov 9, 1978
Priority dateNov 14, 1977
Also published asDE2849368A1, DE2849368C2
Publication number05959097, 959097, US 4188620 A, US 4188620A, US-A-4188620, US4188620 A, US4188620A
InventorsJean-Claude Lamare, Christian Maury
Original AssigneeCompagnie Internationale Pour L'informatique
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Phase decoder
US 4188620 A
Abstract
The binary value of coded signals having opposite going transitions normally in the center of a bit cell, wherein the direction of the transition determines the binary value of the bit cell, is detected. The repetition rate of bit cells of a coded signal control the rate which a signal to be integrated is accumulated by an integrator. The integration duration is controlled by the length of the bit cell. The direction of integration is controlled by the direction of the center transition of each bit cell. In response to the amplitude of the accumulated signal at the end of the integration duration being greater or less than a reference amplitude, the binary value of the bit in the bit cell is determined. Integration is performed by first and second integrators respectively activated to accumulate the signal to be integrated during odd and even numbered bit cells. The first and second integrators are reset to zero during even and odd numbered bit cells, respectively. The accumulated signals of the first and second integrators are sensed prior to resetting thereof to indicate the binary values of the odd and even numbered bit cells.
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Claims(8)
What is claimed is:
1. Apparatus for integrating a series of bi-level electric bits, comprising at least one integrator containing a capacitive integrating member, a device for controlling the integrator responsive to the series of bits for controlling the duration and direction of charging current flowing in the capacitive member as a function of the direction and duration of each individual bit in the series, a circuit for resetting the integrator to zero at the end of each integrating operation of each bit, a generator responsive to the repetition rate of the bits for supplying the capacitive integrating member with a charging current proportional to the nominal frequency FO of the bilevel bits.
2. The apparatus of claim 1, wherein the apparatus comprises first and second integrators, a switching device connected between an output of said current generator and inputs of the first and second integrators, said switching device including first and second devices for respectively controlling the first and second integrators, first and second circuits for respectively resetting the first and second integrators to zero, the switching device being responsive to the bits to be integrated and the current supplied by the said current generator such that the first integrator is in integrating operation while the second is being reset to zero by its zero reset circuit, and vice-versa.
3. Apparatus according to claims 1 or 2 wherein each circuit for resetting an integrator to zero comprises a diode bridge having a first terminal connected to one terminal of the capacitive integrating member of the integrator associated with the resetting circuit, another terminal of said member being connected to a constant reference voltage, a second terminal of the bridge, diagonally opposite from the first terminal being connected to said voltage, the other two opposing diagonal terminals of the bridge being respectively connected to sources of different constant voltages derived by a device for controlling the bridge.
4. Apparatus according to claims 1 or 2 wherein each control integrator device comprises first and second switches, one of which is closed while the other is open, said switches being connected to the integrator and current sources whereby closing of the first switch causes positive integration by the integrator while the closure of the second switch causes negative integration.
5. Apparatus according to claims 1 or 2 wherein each integrator includes a negative current generator that drives a capacitive integrating member.
6. Apparatus for detecting the binary value of coded signals having opposite going transitions normally in the center of a bit cell, the direction of the transition determining the binary value of the bit cell, the bit cells being subject to phase distortion causing a shift in the center position of the transition, comprising integrator means, means responsive to the repetition rate of bit cells of a coded signal for controlling the rate at which a signal to be integrated is accumulated by the integrator means, means responsive to the bit cell period for controlling the integration duration of the integrator means, means responsive to the direction of the center transition of each bit cell for controlling the integration direction of the integrator means during each bit cell, and means responsive to the amplitude of the accumulated signal at the end of the integration duration relative to a reference amplitude for indicating the binary value of the bit in the bit cell.
7. Apparatus according to claim 6 wherein the integration means includes first and second integrators, means for respectively activating the first and second integrators to accumulate the signal to be integrated during odd and even numbered bit cells, means for respectively resetting the first and second integrators to zero during even and odd numbered bit cells, said indicating means including means for respectively responding to the accumulated signal of the first and second integrators prior to resetting thereof to indicate the binary values of the odd and even numbered bit cells.
8. A method of detecting the binary value of coded signals having opposite going transitions normally in the center of a bit cell, the direction of the transition determining the binary value of the bit cell, the bit cells being subject to phase distortion causing a shift in the center position of the transition, comprising sensing the repetition rate of bit cells of a coded signal, in response to the sensed repetition rate controlling the rate at which a value is integrated, in response to the sensed repetition rate controlling the integration duration, sensing the direction of the center transition of each bit cell, in response to the sensed direction, controlling the direction of the integration during each bit cell, and sensing the amplitude of the accumulated, integrated value at the end of the integration duration relative to a reference amplitude to indicate the binary value of the bit in the bit cell.
Description
FIELD OF INVENTION

The present invention relates to an apparatus for and method of integrating a series of electrical signals, and more particularly, to an integrating apparatus and method wherein the accumulation rate for a signal to be integrated is a function of the repetition rate of the signal. While the present invention is described in connection with an apparatus for detecting data recorded on a magnetic tape of a magnetic tape deck, it is clear that the description is equally applicable to any appropriate electric signal detecting apparatus.

BACKGROUND OF THE INVENTION

In present day data-processing systems, magnetic tape decks are commonly used because they have large storage capacity, and require relatively short times for magnetic read/write heads to access data contained anywhere on the magnetic recording tapes from the moment when the heads receive a data access command from the processing system. Magnetic tapes carry data, in coded (usually binary) form, on parallel recording tracks (usually nine) having widths that do not exceed a few hundredths of a millimeter. It is current practice for tape decks to carry only a single removable magnetic tape which is replaced by another tape as soon as reading and/or writing operations involving the first tape have been completed.

Each read-out track of a tape has associated with it a read/write head which is positioned very close to, or even in contact with, the track. The tape moves discontinuously past an assembly formed by the heads for all of the recording tracks. The discontinuous movement is a sequence of "unitary movements", each comprising: (a) a tape speed up phase, during which the tape has a high acceleration; (b) a phase during which the tape moves at a substantially constant speed VO, and (c) a braking phase during which the tape has a high deceleration until it is completely stopped. It is current practice for the data to be read, during each "unitary movement", after the speed up phase, while the tape is moving at constant speed VO.

What are termed slow variations in the tape speed are speed variations about speed VO which take place while the data are read. Frequently these variations are 25% of the speed VO and somtimes as great as 50% of VO. The duration of these variations is a few fractions of a millisecond. Instantaneous variations in the tape speed, on the other hand, are speed variations having durations approximately a hundred to a thousand times shorter than that of the slow variations.

When binary data bits recorded on a magnetic tape pass by an assembly of magnetic read/write heads associated with all of the recording tracks, each of the heads derives a series of analogue electric signals which are shaped into a series of square-wave electrical pulses by shaping circuits. The pulse voltage varies between minimum and maximum values vmin and vmax. For ease of exposition, a description will be given only to the signals derived by a single head; it is to be understood that the same description is equally applicable to the signals derived by the oter heads. The leading edge of the electrical pulse is that part of the pulse during which the voltage changes from the value Vmin to the value Vmax. Oppositely, the trailing edge of a pulse is that part of the pulse during which the voltage changes from the value vmax to the value Vmin. The binary codes most frequently used in writing data on magnetic tapes are such that, after the signals have been read and shaped, a bit equal to "logic one" corresponds to a leading or positive going edge of a pulse while a bit equal to "logic zero" corresponds to the trailing or negative going edge of a pulse.

The series of transduced square-wave electrical pulses constitutes a substantially cyclic signal DE having a nominal mean frequency FO and period TO ; hence, TO defines a single signal bit or "bit cell period". It is clear that the frequency FO of the transduced signal is porportional to the tape speed. Hence, thehigher the tape speed, the greater the number of data items read by the magnetic head per unit of time, whereby frequency FO corresponds to speed VO. For any variation in the tape speed there is a corresponding frequency variation. Thus for a slow tape speed variation there is a corresponding low frequency and for an instantaneous speed variation there is a corresponding instantaneous frequency variation.

If t0 is the time at which a given "bit cell" begins, the time (t0 +TO /2) is termed the "center of the bit cell" and the time (t0 +TO) is termed the "end of the bit cell". Each cell contains either a leading or trailing pulse edge situated in the center of the cell, and possibly, a leading or trailing edge at the end of the cell. Only rising or decaying edges situated in the center of "bit cells" are considered to represent bit values.

A transduced signal DE is supplied to an apparatus for detecting the data recorded on the magnetic tape of the tape deck. Such a detecting apparatus determines the value of each of the data bits recorded on magnetic tape and operates in three phases. During phase one, all the leading or trailing pulse edges in the center of each cell bit of signal DE are recognized to determine the value of the data bits. During phase two, each of the recognized edges is converted into a signal having an amplitude that remains constant during the period TO of this cell. A leading edge is converted into a signal of constant positive amplitude which is termed a "high level", whereas a trailing edge is converted into a signal of constant negative amplitude which is termed a "low level". The positive and negative amplitude signals are referred to collectively by the name "signal DEI". During phase three, the value of the bit corresponding to each cell is determined from signal DEI during each period TO. High and low levels, respectively, correspond to bit values of one or zero.

Imperfections in the magnetic tape and magnetic reading heads, as well as slow and instantaneous tape speed variations, cause distortion in both the amplitude and the phase of the signals read by the head, so that the signal amplitude is reduced and is phase shifted. The distortion is increased by the electronic shaping circuits and the data detecting apparatus and is manifested as a shift in the time position of the edges at the beginning or center of the bit cell. It can further be shown that the distortion increases as the density of the data recorded on the magnetic tape increases, that is, as the number of data items recorded per unit of length of the magnetic tape increases. The phase and amplitude distortion of signals DE and DEI may be relatively severe.

In the prior art there are simple and effective magnetic tape data-detecting devices which enable data bits to be detected with very great accuracy despite considerable phase and amplitude distortion in the signal DEI. Such an arrangement is described in French Pat. No. 2,138,029 entitled "Method and apparatus for detection by integration" filed May 17, 1972 by the S.T.C. company. In this prior art device the bit values are determined (phase 3) by a pair of integrators, each of which integrates the high and low levels of signal DEI during the period TO of the corresponding bit cell, which defines an integrating period.

To ascertain the bit value, it is merely necessary to determine, at the end of each period TO of one bit cell, the polarity of the integrated signal, designated DEINT. If signal DEINT is positive, or negative, the bit value is respectively equal to one or zero. After each integration operation, the integrating arrangement is returned to an initial, rest state during which the integrator output remains constant so that the sign of the integrated signal DEINT may be accurately determined from a constant reference level. Although the term is not strictly correct, the integrating arrangement is said to be reset to zero. If there were no zero reset, errors could occur when determining the polarity of DEINT and thus when determining the value of the data bits.

The integrating arrangement described in French Pat. 2,318,029 includes an integrator containing a capacitive integrating member C responsive to a charging current derived by a constant current generator regardless of the frequency FO of the signal DEI to be integrated. A device for controlling the integrator responds to signal DEI to control the direction and duration of the flow of the charging current supplied to the capacitive member C whereby the current flows during the period TO and the polarity of the integrated signal DEINT at the terminals of the capacitive member at the end of the integrating period TO is the same as signal DEI. A zero-reset circuit for the integrator resets the integrator to zero at the end of each integrating operation.

Since the voltage VC of signal DEINT, at the terminals of capacitive member C, is a linear function of time and the charging current is constant, VC.sbsb.T =kTO =k/FO ; where VC.sbsb.T =the value of VC at TO, k=I/C, and I is the constant charging current. Hence, voltage VC.sbsb.T varies as a function of the frequency FO of signals DE and DEI and is therefor a function of the slow or instantaneous variations in the magnetic tape speed. The effects of these variations on the voltage VC, added to those of the phase and amplitude distortion already mentioned, reduce the accuracy of the integration and thus the accuracy with which the values of the data bits are determined.

BRIEF DESCRIPTION OF THE PRESENT INVENTION

The present invention enables these disadvantages to be overcome by compensating for the effects of the slow variations in the frequency FO on voltage VC, by supplying the integrating member C with a charging current proportional to this frequency FO.

Thus, the voltage VC remains constant regardless of slow variations of frequency FO, and thus in the speed of the tape, while at the same time remaining of sufficient amplitude, when there are instantaneous variations in frequency, to allow the polarity of the integrated signal DEINT to be determined with sufficient accuracy.

In accordance with the invention, the apparatus for integrating a series of electrical signals comprises at least one integrator containing a capacitive integrating member. A device for controlling the integrator responds to the series of signals to be integrated and controls the direction and duration of the charging current for the capacitive member, as a function of the polarity and duration of each signal in the series. A circuit resets the integrator to zero at the end of the operation of integrating each signal in the series. The invention is characterized by a current generator which supplies the capacitive integrating member with a charging current proportional to the nomimal frequency FO of the series of signals.

In a preferred embodiment of the invention particularly applicable to integrating a series of signals having a high frequency FO, the integrating apparatus comprises first and second integrators and a switching circuit connected between the current generator output and inputs of the first and second integrators. The switching circuit includes separate controllers for the first and second integrators, and zero reset circuits associated with the first and second integrators. The switching arrangement responds to bit cells to be integrated and feeds half of the bit cells to each of the two integrators on a time division multiplexed basis, so that one of the integrators is in an integrating operation while the other integrator is reset to zero by the zero reset circuit associated with it. Such an integrating apparatus, including a current generator common to the two integrators, is more accurate, more reliable and less expensive than prior art integrating apparatus, in particular those described in the previously mentioned French Pat. No. 2,138,029.

In accordance with another aspect of the invention, the binary value of coded signals having opposite going transitions normally in the center of a bit cell is detected. The direction of the transition determines the binary value of the bit cell. The bit cells are subject to phase distortion causing a shift in the center position of the transition. Detection involves controlling the rate at which a signal to be integrated is accumulated by an integrator means in response to the repetition rate of bit cells of a coded signal. The duration is controlled by the bit cell period.

In response to the direction of the center transition of each bit cell, the integration direction during each bit cell is controlled. The binary value of the bit in the bit cell is determined in response to the accumulated signal at the end of the integration duration relative to a reference amplitude.

Preferably, the integration is performed by first and second integrators that are respectively activated to accumulate the signal to be integrated during odd and even numbered bit cells. The first and second integrators are reset to zero during even and odd numbered bit cells. The binary values of the odd and even numbered bit cells are indicated by responding to the accumulated signals of the first and second integrators prior to resetting thereof.

The above and still further objects, features and advantages of the present invention will become apparent upon consideration of the following detailed description of one specific embodiment thereof, especially when taken in conjunction with the accompanying drawing.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a diagram of a prior art data-detector incorporating an integrating apparatus;

FIG. 2 is a diagram with respect to time of various signals extracted from different points in the data-detecting arrangement of FIG. 1;

FIG. 3 are waveforms of the input and output signals of the integrating arrangement of FIG. 1 when the input signal contains phase distortion;

FIG. 4 is a general block diagram of a preferred embodiment of an integrating apparatus according to the invention;

FIG. 5 is a detailed diagram of part of the integrating apparatus shown in FIG. 4;

FIG. 6 is a detailed diagram of a zero reset circuit of the integrating apparatus illustrated in FIG. 4; and

FIG. 7 (comprised of 7A-7C) is an illustration of the operation of the zero reset circuit shown in FIG. 6.

To better understand the construction and operating of the integrating apparatus of the invention, reference is made to FIGS. 1-3 to review a few points about the operation and construction of a prior art apparatus for detecting recorded data. The data to be detected are recorded, for example, on a magnetic tape, a tape deck, magnetic disc or any other magnetic medium forming part of a magnetic memory of a data processing system and are coupled to the detector from a magentic head as signal DE.

The main components of the prior art detector are: a variable frequency oscillator VFO ; a circuit TRANSNIV that responds to shaping circuits for input signal DE to transpose the shaped signal into output signal DEI; an apparatus DISINTEG which integrates signal DEI to derive output signal DEINT; a decision circuit DECID which determines the sign of integrated signal DEINT to determine the binary value of data bits of signal DE.

Variable frequency oscillator VFO has an input responsive to input signal DE (FIG. 2) derived by shaping circuits for a series of signals derived by magnetic read/write heads of a tape deck (not shown to simplify FIG. 1). Signal DE is a series of logic pulses in the binary "PE" code, a code frequently used in magnetic memories. As illustrated by waveform DE, FIG. 2, signal DE contains a succession of bit cells CB1, CB2, CB3, CBi, CBi+1, CBn, each having a period TO, so bit cell CB1 lies between times t0 and t1, cell CB2 between times t1 and t2, cell CBi between times ti-1 and ti, and so on. Each bit cell CBi contains a data bit having a value that is a function of the transition direction of a pulse edge situated in the center of cell CBi, i.e. at time (t0 +t1)/2 in the case of cell CB1, (t1 +t2)/2 in the case of cell CB2, (ti-1 +ti)/2 in the case of cell CBi, and so on. Positive and negative going transitions respectively represent binary one and zero values. Hence, for cells CB1, CB2, CB4, CBi+2, the data bits all have binary zero values, while cells CB3, CBi, CBi+1 have binary one data bit values.

Variable frequency oscillator VFO contains phase comparator Cφ and a voltage controlled oscillator VCO which generates a sampling, clock signal H having a frequency FH substantially equal to 1/TO. Thereby, the frequency of signal H corresponds to the nominal frequency FO of input signal DE, so each period of signal H corresponds to the period TO of one cell of signal DE. Phase comparator Cφ compares the frequencies of signals H and DE which are applied to its inputs, to derive a d.c. signal having a voltage amplitude e=kFO, proportional to the frequency FO. The d.c. signal of comparator C is supplied to the frequency control input of voltage controlled oscillator VCO which is a function of voltage e. If the frequency FH of signal H is greater than the nominal frequency FO of signal DE, voltage e is reduced, to alter the frequency FH of signal H in a direction such that finally FO ≃FN. Thus, the frequency of the input signal DE and the frequency of clock signal H are both hereafter referred to as FO.

Level transposition circuit TRANSNIV converts input signal DE into a signal DEI which is to be integrated by integrating apparatus DISINTEG. As can be seen from waveform DEI, FIG. 2, the level of signal DEI is normally constant for the entire duration TO of a bit cell at either a positive or negative level which respectively correspond with binary one and zero cell values. However, if signal DE contains phase distortion, as during cell CBi+1, the value of signal DE is subject to change during a cell as described intra. Phase distortion occurs if the transition is not in the center of the bit cell. In other words, for each bit cell, circuit TRANSNIV normally converts a PE coded signal DE into a signal DEI having a bit value that is a function of the transition direction of the DE signal. It is clear that it is easier to detect the value of a bit in response to signal DEI than in response to signal DE.

To convert signal DE into signal DEI, circuit TRANSNIV includes a signal multiplier M1 that responds to signal DE and a fixed amplitude level (A/√TO) to convert signal DE into a signal Mk (waveform Mk, FIG. 2) having maximum and minimum amplitudes respectively equal to A/√TO and -A/√TO, where A is an arbitrary constant. Signal mk and signal φ(t), derived by shifting the level of signal H so signal φ(t) has maximum and minimum amplitudes respectively equal to +1/√TO and (1/√TO are combined in multiplier M2, which derives signal DEI as equal to (mk) (φ(t)). Integrating apparatus DISINTEG integrates signal DEI during each period TO of bit cells CBi to derive the signal ##EQU1##

Decision circuit DECID responds to signal DEINT and determines its sign at the end of each integration period TO of a bit cell CBi, i.e. substantially at time ti. Circuit DEINT derives a logic signal SB which indicates the value of the data bit corresponding to this cell during each of these periods, i.e. between times t0 and t1, t1 and t2, t2 and t3, etc. In response to the signs of signal DEINT being positive and negative, logic signal SB is respectively equal to one and zero. Because the sign of signal DEINT is determined at the end of the integrating period of bit cell CBi the value signal SB during bit cell i+1 corresponds with the value of signal DE during the preceding bit cell i (see waveforms DE, DEINT and SB, FIG. 2).

Consideration is now given to bit cell CBi+1 in FIGS. 2 and 3, FIG. 3 being an enlarged-scale view of part of FIG. 2. It is assumed that cell CBi+1 contains two phase distortions or errors, of duration Δt1 and Δt2. Phase distorted signals DE, me, φ(t), DEI, DEINT are shown with dotted lines while an ideal bit cell CBi+1 containing no phase distortion has the signals shown with solid lines, similar to the other cells CB1, CB2, CB3, CB4, CBi, CBi+1, etc. In the phase distorted cell CBi+1 the amplitude of signal DEI changes abruptly from A/TO to -A/TO between time intervals ti and (ti +Δt1), t'i and (t'i +Δt2). As a result, during these two intervals integrated signal DEINT has a negative slope. Hence, at the end of integrating period TO at time ti+1, the amplitude of signal DEINT equals A', which is less than A, the amplitude which DEINT would have reached if signal DE for the bit cell CBi+1 had no phase error. However, with prior art techniques, the amplitude A' is sufficient to enable decision devices DECID to determine the polarity of signal DEINT and thus the value of the data bit in cell CBi+1.

Any phase error in signal DE, which error corresponds to an instantaneous variation in the frequency of signal DE, is converted by integrator DISINTEG into an amplitude change of signal DEINT. In accordance with the present invention, the variation of DEINT as a function of time, is used to determine the total phase error (Δt1 +Δt2), and thus the variation in the frequency of signal DE, by measuring the amplitude difference (A-A').

As shown in FIG. 4, the principal parts of a preferred embodiment the integrating arrangement according to the invention include: a generator GCP which derives a positive current having an amplitude proportional to frequency FO ; two, preferably identical, integrators INTEG1 and INTEG2, respectively containing identical capacitive integrating members C1 and C2 ; a switching circuit AIG formed by two identical control devices COM1 and COM2 which respectively control integrators INTEG1 and INTEG2. Circuit AIG is preferably a multiplexer having two sets of switches (I11 -I21), (I12 -I22) respectively forming control device COM1 and COM2. The integrating arrangement also comprises zero reset circuit DISRAZ including two, preferably identical, zero reset circuits CIRCRAZ1 and CIRCRAZ2 that respectively reset integrators INTEG1 and INTEG2 to zero. Generator GCP is supplied to comparator Cφ, via an amplifier AMP, with a control voltage E proportional to the frequency FO of signal DE; generator GCP derives a current ie =k1 FO having an amplitude proportional to frequency FO.

Current ie is supplied to switching circuit AIG, which also responds to the signal DEI to be integrated. Circuit AIG supplies current ie to capacitive integrating member C1 of integrator INTEG1, via control device COM1, during odd numbered bit cells CB1, CB3, CB5, CBk where k=2n+1, and k is a whole number; during even numbered bit cells CB2, CB4, CB6, current ic is supplied to capacitive integrating member C2 of integrator INTEG2, via control device COM2. Thereby, the absolute values of charging currents ie and i'c respectively supplied to capacitors C1 and C2 are both virtually equal to ie. The output signals of integrators INTEG1 and INTEG2, respectively derived from the terminals of capacitors C1 and C2, are DEINT1 and DEINT2 (FIG. 2). Signal DEINT derived by integrating circuit DISINTEG is thus such that DEINT=DEINT1 during the periods of the odd bit cells and such that DEINT=DEINT2 during the periods of the even bit cells. The integrator INTEG2 is reset to zero by zero reset circuit CIRCRAZ1 while integrator INTEG1 is in an integrating operation during odd but cells; integrator INTEG1 is reset to zero by zero reset circuit CIRCRAZ1 while integrator INTEG2 is in an integrating operation during even bit cells. From FIG. 2, the duration of the zero reset [(t'1 -t1), (t'3 -t3), etc.] of each of integrators DEINT1 and DEINT2 is less than TO. As a result, each of integrators DEINT1 and DEINT2 is fully reset to zero before any of its integrating operations begins.

Since the charging currents ic in each of capacitors C1 and C2 are such that: ic ≃k1 FO, the value of signal DEINT voltage Vc across the terminals of each of capacitors C1 and C2 is, at the end of each integrating period TO :

Vc =ic /CTO =Ck1 TO FO =k/C=constant,

where C≃C1 ≃C2.

Thus, slow variations in the frequency FO, and therefore in the speed of the magnetic tape relative to the tape deck, causes the voltage of the signal received at the output terminals of integrators INTEG1 and INTEG2 to remain constant. This does not occur for instantaneous frequency variations, as explained above with reference to FIGS. 2 and 3. The integrating apparatus of the invention thus makes it possible to ensure high accuracy in the detection of data bits.

As seen in FIGS. 4 and 5, the integrating apparatus includes generator GCP and two identical assemblies (COM1 - INTEG1 - CIRCRAZ1) and (COM2 - INTEG2 - CIRCRAZ2). Generator GCP is common to the two assemblies which increases still further the accuracy of the arrangement.

In cases where it is desired to detect, by integration, signals having frequencies much lower than the frequencies of the signals read by tape decks or other magnetic memories, or signals where the loss of time due to the resetting of the integrators of the integrating arrangement to zero does not have an adverse effect on the accuracy of the detection, it is possible to use an integrating arrangement comprising only the generator GCP and one of the two above mentioned assemblies, such as assembly (COM1 - INTEG1 - CIRCRAZ1).

The construction of the integrating apparatus DISINTEG is shown in greater detail in FIG. 5, a circuit diagram of positive current generator GCP, the switching arrangement AIG and integrators INTEG1 and INTEG2. The construction and operation of zero reset arrangement DISRAZ are illustrated in FIGS. 6 and 7. From FIG. 5, current generator GCP contains two, preferably identical, PNP bipolar transistors T1 and T2 respectively having a collector resistor R1 and an emitter resistor R2. The emitters of transistors T1 and T2 are connected to a source of positive biassing voltage (not shown to simplify FIG. 5) which supplies a voltage VAL1 directly to the emitter of transistor T1 and via resistor R2 to the emitter of transistor T2. The base and collector of transistor T1 are short circuited so the transistor functions as a thermal compensation diode for transistor T2.

A control voltage E, having an amplitude proportional to the frequency FO of input signal DE, is fed to the base of transistor T2 that derives an output collector current ie. Current ie is fed to a first input of the switching circuit AIG, having second, third and fourth inputs respectively responsive to signals DEI, H and H/2. Signal is derived by frequency dividing signal H by a factor two, as performed by frequency divider DIV. Switches I11 -I21 of control device COM1 and I12 -I22 of control device COM2 are preferably transistor switches. Each of switches I11 -I21 and I12 -I22 is controlled by signals H, H/2 and DEI.

To consider the operation of circuit AIG, initially assume that signal H/2 (FIG. 2) has a binary zero value, as occurs between times t0 and t1, t2 and t3 and t4 etc., when the level of H/2 is low. At these times, control device COM1 causes integrator INTEG1 to integrate, while zero reset circuit CIRCRAZ2 resets integrator INTEG2 to zero. When signal H/2 has a high value and is equal to logic one, i.e. between times t1 and t2, t3 and t4, etc., control device COM2 causes integrator INTEG2 to integrate while zero reset circuit CIRCRAZ1 resets integrator INTEG1 to zero. Hence, integration by, and zero reset of, integrators INTEG1 and INTEG2 are controlled by signal H/2 and are a function of the value of signal H/2.

Signal H defines the limits and the duration of the integration of signal DEI by integrators INTEG1 and INTEG2. Thus, if signal H/2 is assumed to be at its low level, integrator INTEG1 starts and stops integrating signal DEI when signal H changes from logic one to logic zero, that is at the trailing edges of pulses of clock signal H, i.e. at time t0, t2, t4 etc., which correspond to the beginning of integration and times t1, t3, t5 etc., which in turn correspond to the end of an integration period. Similar, but complementary reasoning is applicable to integrator INTEG2.

Signal DEI controls the polarity of the integrated signals DEINT1 and DEINT2 respectively derived by integrators INTEG1 and INTEG2 by controlling the opening and closing of the transistor switches I11 and I21 of control device COM1 on the one hand, and the transistor switches I12 and I22 of control device COM2 on the other hand. While each of integrators INTEG1 and INTEG2 is being reset to zero, the switches of the associated control devices COM1 and COM2 are open.

Thus, if integrator INTEG1 is performing an integration (signal H/2 at its low level) and if signal DEI is positive, switch I11 is closed and switch I21 open (between times t2 and t3 for example), switches I12 and I22 being also open. The integrated signal DEINT1 is thus positive. If signal DEI is negative, switch I11 is open and switch I21 is closed, (I12 and I22 being open), and signal DEINT1 is thus negative. Identical reasoning is applicable to integrator INTEG2.

As illustrated in FIG. 5, integrator INTEG1 includes negative current generator GCN1 and capacitor C1, while integrator INTEG2 includes negative current generator GCN2 and capacitor C2.

Current generator GCN1 contains two, preferably identical, NPN bipolar transistors T31 and T41 having emitters respectively connected to a source of negative biassing voltage VAL2 (not shown) via preferably identical resistors R31 and R41. Negative current generator GCN2, which is identical to GCN1, similarly contains identical NPN bipolar transistors T32 and T42 having identical emitter resistors R32 and R42. Transistors T31 and T32, by virtue of the short circuited bases and collectors thereof, are thermal compensation diodes for transistors T41 and T42. Each of transistors T41 and T42 preferably has a high current gain. Terminals B11 and B12 of capacitive member C1 are respectively connected to the collector of transistor T41 and to a source (not shown) of D.C. reference voltage REF. Similarly, terminals B21 and B22 of capacitive member C2 are respectively connected to the collector of transistor T42 and the source of voltage REF.

Only the operation of integrator INTEG1 is described in detail, because integrators INTEG1 and INTEG2 operate identically.

Assume that signal DEI is positive, as between times t2 and t3, for example, and that signal H/2 is low. Control device COM1 therefore is activated so switches I11 and I21, are respectively closed and open, causing integrator INTEF1 to integrate, in response to a positive charging current ic, designated ic+, flowing to capacitor C1. Current ic+ is considered to perform a positive integration.

If signal DEI is negative, as between times t0 and t1, for example and signal H/2 remains at its low level, switches I11 and I21, are respectively open and closed, whereby a negative charging current ic (designated ic-) flows to capacitor C1 and integrator INTEG1 performs a negative integration. Thus ic =ic+, if DEI is positive, and ic =ic-, if DEI is negative.

If ib is the base current of transistors T41 and T31, or T42 and T32 then, regardless of the direction of current ic :

ic =ie -2ib =ie (1-2ib /ie)=ie (-2/β),

where β is the current gain of transistor T41 or T42. If β is greater than 100, ic =ie and the charging current flowing to capacitor C1 or C2 is proportional to the frequency FO.

The following table summarizes the operation of switching apparatus AIG and its four switches I11, I21, I12, I22, and that of the integrators INTEG1 and INTEG2. The convention adopted uses (1) and (0) to respectively indicate the closed and open states of the switches; the ratio ic /ie is equal to 1 for a positive integration and equal to -1 for a negative integration. The charging current for INTEG2 is termed i'c.

______________________________________   Switch   Switch   Switch Switch(ic /ie)   I11 I21 I12                            I22                                   (i'c /ie)______________________________________+1      1        0        0      0      0-1      0        1        0      0      00       0        0        1      0      +10       0        0        0      1      -1______________________________________

The zero reset circuit DISRAZ shown in FIG. 6 comprises: first and second, preferably identical, diode bridges P1 and P2 respectively forming zero reset circuits CIRCRAZ1 and CIRCRAZ2 for integrators INTEG1 and INTEG2 ; diodes DIOD1 and DIOD2 ; as well as transistor switches Q1 and Q2 which respectively control bridges P1 and P2.

In the described embodiment, the first diode bridge P1 comprises four "Schottky" diodes P11, P12, P13, P14, such as diodes of the HP - 5082 - 2013 type manufactured by Hewlett-Packard. Terminals P1 S2 and P1 S1 of bridge P1 are respectively connected to terminal B11 of capacitive member C1 and to resistor R61, in turn connected to diode DIOD1 and via switch Q1 to a source of positive voltage Vp, equal to +5 volts for example. Terminals P1 S4 and P1 S3 are respectively connected to a source of negative voltage VR (equal to -5 volts, for example) and to resistor R51, in turn connected to diode DIOD2 and to the positive voltage source Vp =+5 V by switch Q2.

Diode bridge P2 similarly comprises four Schottky type diodes P21 to P24. Terminals P2 S2 and P2 S4 are respectively connected to terminal B21 of capacitive member C2 and to the negative voltage source VR =-5 V. Terminal P2 S1 is connected to diode DIOD2 via a resistor R52 and to the source of voltage Vp via switch Q2, while terminal P2 S3 is connected to diode DIOD1 via a resistor R62 and to source Vp via switch Q1. The cathodes of diodes DIOD1 and DIOD2 are connected to a source of negative voltage Vn =-9 volts. Resistors R51 and R52 preferably have identical values, as do R61 and R62.

The following description is restricted to the operation of the diode bridge P1 which controls the resetting to zero of integrator INTEG1 as illustrated by FIGS. 7a, 7b, 7c; the operation of bridge P2 is identical to that of bridge P1.

In describing the integrating apparatus of the invention, it is assumed that capacitor C1 has returned to its initial, discharged state, whereby voltage VB11 is equal to VR, i.e. is equal to -5 V; also assume terminal B12 is maintained at a D.C. reference voltage REF, equal to +5 V. The positive and negative charges supplied to capacitor C1 correspond to variations ΔVB11 in the voltage VB11, respectively equal to +2 V and -2 V. Thus, after a positive integration,

VB11 =-5+ΔVB11 =(-5+2)=-3 V,

and after a negative integration

VB11 =(-5-2)V=-7 V.

In the first case to be considered, capacitor C1 returns to its initial state after a positive integration, as illustrated by FIG. 7A, whereby switches Q1 and Q2 are respectively closed and open. Voltages VH, VBAS and VB11 are respectively equal to +5 volts, -9 volts, and -3 volts. Since under these circumstances VH is greater than VR and since VB11 is greater than VBAS, diodes P11 and P13 are unblocked. Since the voltage drop across the terminals of the unblocked Schottky diodes is approximately 0.4 volts, VP1S3 and VP1S1 respectively equal -3.4 volts and -4.6 volts, approximately. Diode P14 is blocked because its anode voltage VR is less than its cathode voltage VP1S3 while diode P12 is blocked because its anode voltage VP1S1 is less than its cathode voltage VB11. Capacitor C1 therefore discharges through diode P13 and resistor R51.

When capacitor C1 has completed its discharge, (the condition illustrated in FIG. 7B) voltage VB11 is very close to 31 5 volts and diodes P11 and P13 remain unblocked since their anode voltages are higher than their cathode voltages. However, diodes P14 and P12 are also unblocked, because the cathode voltage VP1S3 of diode P14 equals -5.4 V and is thus less than its anode voltage VR =-5 volts, and the cathode voltage VB11 of diode P12 is less than its anode voltage VP1S1 (which is still equal to -4.6 V). When the discharge of capacitor C1 has been completed, diode bridge P1 is balanced, with VB11 =VR.

The case which will now be considered is that of capacitor C1 being reset to zero after a negative integration, as illustrated by FIG. 7C. VH is still equal to +5 volts and BBAS equal to -9 volts. Thus, VB11 =-5-2=-7 volts. Under these conditions, diode P12 is unblocked and its anode voltage VB1 is such that VP1S1 -VB11 =0.4 V, thus making VP 1S1 equal to -6.6 volts. Diode P11 is therefore blocked, its cathode voltage VR =-5 volts being greater than VP1S1. Diode P14 is unblocked since its anode voltage VR =-5 volts is very much higher than voltage VBAS =-9 volts. Voltage VP1S3 is therefore equal to -5.4 volts and is thus greater than VB11. Consequently, diode P13 is blocked. Capacitor C1 discharges through diode P12 and resistor R61.

At the end of discharge, the diode bridge P1 is again balanced (see FIG. 7B). Both in the case of a positive integration (the circuit formed by C1 - diode P13 - resistor R51) and in the case of a negative integration (the circuit formed by C1 - diode P12 - resistor R61), the time-constant of the discharge circuit for capacitor C1 is such that the zero reset of capacitor C1 is completed by times t'1, t'3, t'5, etc., which lie between times t1 and t2, t3 and t4, t5 and t6, etc. respectively and which are such that

______________________________________                       t'1 < t2(see FIG. 2)                t'3 < t4                       t'5 < t6______________________________________

While there has been described and illustrated one specific embodiment of the invention, it will be clear that variations in the details of the embodiment specifically illustrated and described may be made without departing from the true spirit and scope of the invention as defined in the appended claims. For example digital integrators (counters) and techniques could be used, in which case the rate at which pulses are supplied to the integrators would be controlled by the frequency of signal DE, the counting direction would be controlled by the direction of the center transition and the integration period would be controlled by the period of signal DE.

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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4542420 *Jan 24, 1984Sep 17, 1985Honeywell Inc.Manchester decoder
US5231650 *Jun 27, 1990Jul 27, 1993Canon Kabushiki KaishaDigital signal reproducing apparatus
US5468201 *Feb 9, 1993Nov 21, 1995Minoura Co., Ltd.Loading apparatus for exercise device
US7469023Sep 3, 2003Dec 23, 2008Susan VasanaManchester code delta detector
US20040247051 *Sep 3, 2003Dec 9, 2004Susan VasanaManchester code delta detector
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Classifications
U.S. Classification341/70, G9B/20.039, 360/42
International ClassificationH03M5/12, G11B20/14, H04L25/49
Cooperative ClassificationG11B20/1419, H04L25/4904
European ClassificationH04L25/49C, G11B20/14A1D