|Publication number||US4209713 A|
|Application number||US 05/911,164|
|Publication date||Jun 24, 1980|
|Filing date||May 31, 1978|
|Priority date||Jul 18, 1975|
|Publication number||05911164, 911164, US 4209713 A, US 4209713A, US-A-4209713, US4209713 A, US4209713A|
|Inventors||Kazuo Satou, Mitsuhiko Ueno, Yasoji Suzuki|
|Original Assignee||Tokyo Shibaura Electric Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Non-Patent Citations (1), Referenced by (68), Classifications (12)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a continuation of application Ser. No. 705,960, filed July 16, 1976, now abandoned.
1. Field of the Invention:
This invention relates to semiconductor integrated circuit devices and in particular to Complementary Metal Oxide Semiconductor field effect transistors (hereinafter referred to by the abbreviation CMOS) in which difficulties caused by parasitic bipolar transistors are eliminated.
2. Description of the Prior Art:
Various CMOS circuits have been known in the past, and a typical example of these is a CMOS inverter circuit. This inverter circuit is made up of a P channel type MOS transistor Q1 and an N channel type MOS transistor Q2 ; the source electrode of the transistor Q1 is connected to a positive power source VDD ; the drain electrode of the transistor Q1 and the drain electrode of the transistor Q2 are connected together and both are connected to an output terminal OUT, and the source electrode of the transistor Q2 is connected to a negative power source VSS. Also, the gate electrodes of the transistors Q1 and Q2 are both connected to an input terminal IN to make up an inverter.
In a CMOS circuit constructed in this manner, the threshold direct voltages Vth of the N and P channel MOS transistors have opposite polarities, and therefore their actions on input voltages are entirely opposite to one another, and the operating power is extremely small. For example, if the power source VDD is made +5 V and the power souce VSS is made earth (GND), and if +5 V is supplied to the input IN, the transistor Q2 conducts and the transistor Q1 does not conduct, and no direct current at all flows between the power sources VDD and VSS. Conversely, if zero V is supplied to the input IN, the transistor Q2 becomes non-conductive and the transistor Q1 becomes conductive, and once again direct current does not flow between the power sources VDD and VSS. Therefore, in the CMOS circuit there is generally practically no operating power consumption; in the input information pulse transition time region, the transistors Q1 and Q2 both conduct, and all that happens is that an instantaneous transition current flows along with leakage current occurring at the PN junctions, and the current due to the charge and discharge of the load capacity at the output. Accordingly, in general the power of CMOS circuits can be said to be extremely small.
But in CMOS circuit systems of this kind, when noise in the form of an impulse is applied to the output or to the input, a large direct current (several dozen mA to several hundred mA) flows between the power sources VDD and VSS, and even when this noise is stopped, a phenomenon occurs whereby the large current continues to be maintained steadily. This phenomenon (hereinafter referred to as "Latch-up") magnifies the power consumption, and leads to a CMOS circuit of low reliability. The polarity of this impulse can be positive or negative; in order to eliminate this phenomenon it is necessary to reduce the power souce VDD below a certain voltage, or to cut off the power sources of the circuit system.
Accordingly, one object of this invention is to provide a novel semiconductor CMOS integrated circuit device in which difficulties caused by parasitic bipolar transistors are eliminated.
Another object of this invention is to provide a CMOS integrated circuit device in which an accidental large direct current does not flow between power sources.
Yet another object of this invention is to provide a CMOS integrated circuit device of high reliability.
A further object of this invention is to provide a CMOS integrated circuit whose power consumption is reduced and whose characteristics are improved.
The objects of the present invention are achieved by a semiconductor integrated circuit device comprising a CMOS circuit whose structure is characterized by the formation therein of parasitic thyristors, and noise absorption means connected to the CMOS circuit for absorbing impulse noise that otherwise could become trigger pulses for the thyristors.
A more complete appreciation of the invention and many of the attendant advantages thereof will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
FIG. 1 is a circuit diagram of a CMOS inverter.
FIG. 2 shows a sectional structural diagram of a CMOS inverter and parasitic bipolar transistors.
FIG. 3 shows an equivalent circuit diagram of the parasitic thyristor shown in FIG. 2.
FIG. 4 and FIG. 5 show circuit diagrams of one embodiment of this invention.
FIG. 6 shows a sectional structural diagram characteristics of the diode shown in FIG. 5.
FIGS. 7-9 show circuit diagrams of further embodiments of this invention.
Referring to FIG. 1, there is shown a CMOS inverter circuit, and FIG. 2 shows a sectional drawing of this circuit completed to make up a semiconductor wafer as an example. In this example, what is known as a P-well layer 2 having a P type impurity in a concentration of about 2×1016 atoms/cm3 is formed in an N type base plate 1 having a concentration of about 1×1015 atoms/cm3, and in the N type base plate outside this layer 2, P type regions 3 and 4, which becomes P channel MOS transistors, are formed by diffusion so that their concentration is for instance about 1019 atoms/cm3. On the other hand, inside the P-well layer 2, also, a P type region is formed which becomes an N channel MOS transistor stopper, and also in the P-well layer N type regions 5 and 6 which become N channel MOS transistors are formed by diffusion of about 1020 atoms/cm3 of an N type impurity. After this, a silicon oxide film about 1500 A thick is provided in the places which become the gates 7 and 8 of the MOS transistors, the necessary parts are apertured and the circuit is wired with a conductor such as Al, and a CMOS semiconductor element is thus obtained.
This invention has been perfected on the basis of the fact that it has been discovered that the thyristor circuits shown in FIG. 3 are formed in a CMOS structure.
FIG. 2 shows the manner in which the aforesaid thyristor circuits are formed in the CMOS inverter circuit of FIG. 1; FIG. 3 is a diagram showing the equivalent circuit of FIG. 2 consisting of a plurality of parasitic bipolar transistors. As soon as the thyristor action occurs, the power is often magnified and this causes thermal breakdown.
The above-mentioned thyristor circuits will now be described with reference to FIG. 3; in the P-well region 2 formed in the N type semiconductor substrate 1, parasitic bipolar transistors Tr2 and Tr4 are formed along the direction of the thickness of the substrate 1, and in the substrate 1 outside the P-well region parasitic transistors Tr1 and Tr3 are formed in a direction at right angles to the direction of this thickness; also, resistances RPwell, RNsub.sbsb.1 and RNsub.sbsb.2 are formed which are present in the P-well region 2 and the substrate 1. Now, as shown by the chain-dotted line arrow in FIG. 3, when positive impulse noise is applied to the output OUT, a current α3 ×Iin flows, bypassing the RPwell region, and when the voltage drop of this has become VBE2, a current flows in the base of the transistor Tr2.
Ib2 δα3 Iin (RPwell >>rbe2) (1)
Ic2 =β2 I2 =β2 α3 Iin (2)
Here, Ib2 and Ic2 are the base and collector currents of the transistor Tr2, α1, α2, α3 and α4 are the common base current gain of the transistors Tr1, Tr2, Tr3 and Tr4, β1 =α1 /1-α1, β2 =α2 /1-α2 are the common emitter current gain and Iin is the impulse noise.
Similarly, when Ic2 has become the drive current and the voltage drop across RNsub2 has become VBe1, the base current of the transistor Tr1 flows and this goes into the conductive state.
Ib1 =Ic2 (RNsub ≳rbe1) (3)
Ic1 =β1 Ib1 =β1 β2 α3 Iin (4)
Even if the application of further noise from outside is stopped, the current between the power source VDD and GND, that is to say between Tr1 and Tr2, will be maintained provided that the condition
Ib2 ≦Ic1 (5)
is satisfied. That is to say, if the condition
α3 Iin ≦β1 β2 α3 Iin 1≦β1 β2 (6)
or 1<β1 β2 is established, then if the base current of the cycle of the loop circuits is I'b2 then the base current I"b2 of the next cycle will be greater than this, and therefore as the cycles are repeated the current flowing through the system will increase, but this will not go on infinitely. Because of the dependency of β on the current, as the current increases a limit βmax will be reached at which β will begin to decrease, and in the steady state it appears that the abnormal current described previously will settle down where the following two conditions are satisfied simultaneously.
Ib2 (n-1)=Ib2 (n), β1 (n)·β2 (n)≧1
Here, Ib2 (n) is the current at which stability is maintained, and it appears that in this case there will be stability at the nth loop current.
Now, firstly, the size of the dimensions of the transistors is not the main factor regarding the readiness of occurrence of the phenomenon of the flow of the previously described abnormal current, but this will be discussed on the basis of the above equations. When the current gain is measured with the dimensions (more precisely, the drain surface area) of the transistors as a parameter, there is a correlation between the current value at which the normal current converges and the dimensions of the transistors; when the transistors have larger drain surface areas, the abnormal current becomes greater, and conversely, when the transistors are small, the value of the current become small. Moreover, in cases in which negative noise is applied to the output OUT as shown by the dotted line arrow, also, similar to the case of positive noise, ##EQU1## and the condition for the maintenance of the current of the system becomes
Ib1 ≦Ic2 1≦β1 β2 (8)
FIG. 4 represents a CMOS circuit according to an embodiment of this invention which can eliminate the above-mentioned drawbacks. In this embodiment, in order to prevent a forward current from flowing from the output part into the diffused layers wherein an inverter circuit is formed by CMOS structure P channel MOS transistors and N channel MOS transistors, a protective resistance 21 is provided in the output part of the above-mentioned CMOS structure so that the noise supplied to the thyristor circuit (as shown in FIG. 3) will be absorbed in this resistance. In this embodiment, whether the polarity of the impulse noise be negative or positive, the resistance 21 performs the function of keeping the above-mentioned positive or negative noise below the voltage VLa necessary for the commencement of conduction of the abnormal current by the parasitic thyristors, in other words, keeping it below the input current ILa necessary for the commencement of conduction of the abnormal current, and accordingly, the abnormal current of the parasitic thyristors can be prevented.
It is also possible, as shown in FIG. 5, to insert diodes D5 and D6 at the input part of the CMOS circuit in order to prevent gate breakdown. This is shown in a circuit structure in FIG. 6. As shown in the drawing these diodes D5 and D6 form parasitic bipolar transistors Tr'3 and Tr'4. These transistors correspond to the parasitic bipolar transistors Tr3 and Tr4 of FIG. 3, and therefore become the cause of abnormal currents. Accordingly, if in the case of a structure as in FIG. 6, resistance 21 is provided at the input part IN in contrast to the case in which it is provided at the output part OUT, abnormal current due to noise from the input part can be prevented. (For example, the resistance value is several kΩ).
FIGS. 7-9 show other embodiments of this invention. In FIG. 7, resistance 21 (80Ω-80 kΩ) is disposed between the positive power source VDD and the drain electrode of the transistor Q1 ; and a resistance 22 (80Ω-several kΩ) is disposed between the negative power source VSS and the source electrode of the transistor Q2. In this circuit, when a negative noise impulse is applied to the output OUT, the resistance 22 performs the function of keeping the above-mentioned negative impulse noise below the voltage VLa. On the other hand, when a positive noise impulse is applied to the output OUT, the resistance 21 performs in the same manner. Accordingly, for either polarity of impulse noise, the abnormal current of the parasitic thyristors can be prevented.
Furthermore, a protective resistance can be disposed only on the side of the positive power source VDD or GND as shown in FIG. 8 and FIG. 9, in accordance with the weaker side in the actual pattern layout.
If the CMOS circuit is susceptible to positive impulse noise, the resistance is disposed to positive power source VDD side. On the other hand if the circuit is susceptible to negative impulse noise, the resistance is disposed to the negative power source VSS side.
As described above, when the present invention is used absorption resistance is provided to deal with noise causing the thyristor phenomenon in CMOS circuit systems, and it is therefore possible to provide a semiconductor integrated circuit in which an accidental large direct current does not flow between power sources. Therefore thermal breakdown can be prevented, electric power consumption can be reduced, and the circuit characteristics can be improved.
Also, this invention is not restricted to the embodiment described above; it can be applied not only to the inverter circuit shown in FIG. 1, but also to all kinds of CMOS circuits in which thyristors are formed; as regards the CMOS structure, also, the invention may be used in cases where and N-well region is formed in a P type semiconductor base plate, and also with silicon gate CMOS.
Although this invention has been disclosed and illustrated with reference to particular applications, the principles involved are susceptible of numerous other applications which will be apparent to those skilled in the art. The invention is, therefore, to be limited only as indicated by the scope of the appended claims.
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|U.S. Classification||327/310, 326/104, 326/21, 326/121, 257/E27.063, 257/376|
|International Classification||H03K17/16, H01L27/092|
|Cooperative Classification||H01L27/0921, H03K17/162|
|European Classification||H03K17/16B2, H01L27/092B|