|Publication number||US4218764 A|
|Application number||US 05/948,335|
|Publication date||Aug 19, 1980|
|Filing date||Oct 3, 1978|
|Priority date||Oct 3, 1978|
|Publication number||05948335, 948335, US 4218764 A, US 4218764A, US-A-4218764, US4218764 A, US4218764A|
|Inventors||Yukio Furuta, Tomisaburo Okumura|
|Original Assignee||Matsushita Electric Industrial Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Non-Patent Citations (2), Referenced by (60), Classifications (14)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Field of the Technology
This invention relates to a non-volotile memory control circuit which drastically improves reliability of memory retention of a non-volatile memory device.
A non-volatile memory device is now well known as a circuit element which retains memory contents semipermanently. In fact, it is not avoidable that memory states gradually change as time passes. The non-volatile memory devices of semiconductor are largely classified into the following three groups:
(i) ROM . . . read only memory, wherein logic levels are fixed during the masking process and once data are programmed, reprogramming is not possible,
(ii) EPROM . . . erasable programmable ROM, wherein data can be electrically programmed, but data can only be erased by X-ray or ultraviolet light (UV),
(iii) EAROM . . . electrically alterable ROM, wherein information is introduced by selectively programming "1"s in proper bit locations and the bit pattern can be erased later and a new pattern can then be written into the devices.
For the non-volatile memory devices grouped in (i), there are a mask ROM and a fuse ROM. In these memory devices, once the data are programmed, they can not be reprogrammed, and accordingly there arises no problems in practical use even if memory states change as time passes. On the contrary, in the non-volatile memory devices where data information can be reprogrammed, there arise grave problems in practical use when the memory states change as time passes.
This inconvenience is explained referring to FIG. 1, which shows relationship between memory level (M) for example, electric potential or magnetic potential, and time lapse (T). The memory level shown by a curve M1 indicates a memory state 1 (hereinafter written "1"), and the memory level shown by a curve MO indicates a memory state 0 (hereinafter written "0"). The memory levels for "1" and "0" have their initial values M10 and M00 (at T0), respectively, and slowly change as time passes as shown in FIG. 1. They reach M11 and M01 at T1, and reach M12 and M02 at T2, respectively.
Theoretically speaking, it is possible to distinguish between "1" and "0", if the memory level M1 for "1" and the memory level for "0" satisfy the relationship |M1-M0|>0. But this is only theoretical relation, and in practice accuracies of an interrogation circuit or the like used must be taken into account. Accordingly, specified difference ΔM is required between the memory level M1 for "1" and the memory level M0 for "0". This means, distinction between "1" and "0" is surely possible when the relation |M1-M0|≧ΔM holds for the memory levels M1 and M0, where the difference ΔM is a positive and finite value.
For the characteristics of a non-volatile memory device, the longer the time period from a writing to the time for the memory level difference becoming to the value ΔM is, and also the smaller the minimum value of the memory level difference ΔM required for an accurate reading of "1" and "0" is, the longer the time of memory retention becomes.
In actual memory devices, as far as the memory levels M1 and M0 change as time passes shown in FIG. 1, a maximum memory retention time becomes a finite one. For example, if a difference ΔM(2) at T2 is equal to the threshold value of the difference of the memory levels ΔM which is necessary to distinguish between "1" and "0", then we can define T2 as the memory retention time of the non-volatile memory devices. Accordingly, if the memorized memory levels can be reprogrammed before the quantity |M1-M0| decreases to the threshold value ΔM(2), the valid memory states can be continuously retained.
The present invention provides a non-volatile memory control circuit, wherein memorized states of non-volatile memory devices can be semipermanently kept in valid states, and accordingly condition of circuits including non-volatile memory devices is kept in right circuit condition.
FIG. 1 is a time chart showing one example of change of memory levels in a non-volatile memory device for the passage of time.
FIG. 2 shows another time chart showing change of memory levels which are reprogrammed by a non-volatile memory control circuit in accordance with the present invention.
FIG. 3 to FIG. 5 are block diagrams of non-volatile memory control circuits for non-volatile memory devices in accordance with the present invention.
FIG. 6 is a circuit diagram showing one embodiment of a non-volatile memory control circuit for non-volatile memory devices in accordance with the present invention.
FIG. 7 is a time chart showing relationships between time and threshold voltage, and showing a scope indicated by hatching lines, within which scope the memory levels "1" and "0" are correctly read out by the gate voltage VG1 and VG3.
FIG. 8 (a) to FIG. 8 (j) are timing charts showing voltage of various parts of the circuit shown in FIG. 6.
The feature of the present invention is to provide a non-volatile memory control circuit for the non-volatile memory devices, wherein an interrogation circuit having a preset reference voltage corresponding to the difference ΔM(1) of the memory level at a time T1, which is prior to a time T2 as shown in FIG. 1, is provided, and the memory levels of the non-volatile memory devices are reprogrammed before the difference decreases to the threshold value ΔM(2) at the time T2, by utilizing the output signal of the interrogation circuit.
FIG. 2 shows that the non-volatile memory devices are reprogrammed by the non-volatile memory control circuit embodying the present invention when the difference ΔM decreases to a preset value ΔM(1). The non-volatile memory devices are thus reprogrammed when the difference of the memory levels ΔM reaches ΔM(1), so that the difference of the memory levels ΔM returns to the initial value ΔM(0), which is the value immediately after the initial programming at the time T0. The memory levels of the non-volatile memory devices again gradually change after this moment in the same manner as in the previous period T0-T1, based on its time-level difference characteristics. As shown in FIG. 2, the non-volatile memory devices are reprogrammed after every same time intervals, namely at T1 and 2T1 and therefore the difference of memory levels does not at all decrease to the threshold value ΔM(2).
FIG. 3 is a block diagram showing a principal part including an interrogation circuit of the non-volatile memory control circuit of the present invention. The non-volatile memory control circuit comprises:
(i) a first non-volatile memory part 1 constituted by signal or plural number of non-volatile memory devices,
(ii) a first interrogation circuit 2 which has a preset reference level of the value of threshold difference ΔM(2) shown in FIG. 1 and FIG. 2, and detects the level of an output of the first non-volatile memory part 1,
(iii) a second non-volatile memory part 3 which is constituted by single or plural number of non-volatile memory devices and which is constituted to be reprogrammed at the same time when the first non-volatile memory part 1 is reprogrammed. The number of the non-volatile memory devices in the non-volatile memory part 3 is more than one or equal to one and it can be arbitrarily determined depending on that how much accuracy is required for them. And the memory data pattern can be optionally selected, in other words the levels of the memory devices are fixed to "1" and "0" or to either one of them. The selection of the memory data pattern can be determined depending on the characteristics of the memory devices.
(iv) a second interrogation circuit 4 which has a preset reference level of the difference ΔM(1), that is larger than the threshold difference value ΔM(2) shown in FIG. 1 and FIG. 2, and detects the level of an output of the second non-volatile memory part 3, and (v) an alarm circuit 5 which generates a warning signal when the memory levels "1" or "0" programmed in the second non-volatile memory part 3 are erroneously read by the second interrogation circuit 4.
The circuit of FIG. 3 elucidated as above constitutes a circuit which has a function of keeping the memory states in the first non-volatile memoty part 1 always in that which enables accurate reading of the memory state.
FIG. 4 is a block diagram of another non-volatile memory control circuit of the present invention, wherein non-volatile memory devices are automatically reprogrammed in response to an output signal from an alarm circuit 5.
The non-volatile memory control circuit of FIG. 4 includes a reprogram control circuit 6 which operates responsive to an output signal of the alarm circuit 5, an erase write circuit 7 which operates responsive to an output signal of the reprogram control circuit 6, and a memory circuit 8 which stores memory contents of a first non-volatile memory part 1 and responding with the output of the reprogram control circuit 6, to the circuit of block diagram shown in FIG. 3. In this non-volatile memory control circuit of FIG. 4, the reprogram control circuit 6 performs control operation for transferring memory contents in the first non-volatile memory part 1 to the memory circuit 8 through a first interrogation circuit 2. This transferring operation is made responding with the output signal from the alarm circuit 5.
The erase write circuit 7 operates responding with the output signal of the reprogram control circuit 6 so as to erase data in the non-volatile memory parts 1 and 3 and to write the data in the memory circuit 8 into the first non-volatile memory part 1. Then, predetermined memory levels ("1" and "0" or either one of them depending on the number of the non-volatile memory devices) are reprogrammed in the second non-volatile memory part 3. By the abovementioned operation the data stored in the first non-volatile memory part 1 are automatically reprogrammed during the time period while the difference of the memory levels is still larger than the threshold level ΔM(2), without destroying the valid memory states. Thus, the data stored in the first non-volatile memory part 1 are semipermanently retained in the valid memory states as initially programmed.
FIG. 5 is a block diagram of another non-volatile memory control circuit, wherein on top of the construction of FIG. 4, the circuit has additional parts for causing the reprogramming of the memory devices when a power source for driving the circuit is turned on. In this embodiment output signals from a turn-on detection circuit 10 or from a start circuit 11 which issues a triggering signal for reprogramming operation are selected by a switch 9. The operation of the reprogram control circuit 6 is controlled by an output signal of an AND gate 12 which receives an output signal selected by the switch 9 and an output signal of the alarm circuit 5.
These circuits are so designed that the non-volatile memory divices are not necessarily reprogrammed immediately after every issuing of output signals from the alarm circuit 5 during an operation of an apparatus including the abovementioned circuits. There is no inconvenience that the operation of the apparatus stops or paralized for a moment due to the reprogramming operation for the non-volatile memory devices.
This situation is elucidated referring to FIG. 5. When the switch 9 is switched to the side to transmit the output signal of the turn-on detection circuit 10 to the AND gate 12, the reprogramming of the non-volatile memory devices is automatically executed if the alarm circuit 5 issues the output signal and besides the power source is turned on. When the switch 9 is switched to the side to transmit the output signal of the start circuit 11 to the AND gate 12, the reprogramming operation can be manually executed at any desired time during the while the alarm circuit 5 is issuing the output signal.
FIG. 6 is a schematic diagram of a specific example of the abovementioned non-volatile memory control circuit shown in block diagram in FIG. 5. In the circuit of FIG. 6, two non-volatile memory parts 1 and 3 are respectively constituted by using single non-volatile memory devices 1' and 3'. The non-volatile memory device 1' and the non-volatile memory device 3' used in this circuit are MNOS (metal-silicon nitride-silicon dioxide-semiconductor) memory devices. Other transistors are p-channel MOS FET's. The MNOS memory devices have a threshold voltage to gate voltage hysteresis characteristics. Data can be stored by applying gate voltage and later they can be erased and reprogrammed electrically.
In the circuit of FIG. 6 the specified voltage VG1 and VG3 are respectively applied to the gates of the non-volatile memory devices 1' and 3' thereby making the MNOS memory devices turn on or turn off.
The non-volatile memory devices 1' and 3' are so designed that, when both non-volatile memory devices 1' and 3' have the memory level of "1", the time period during which the memory level "1" can be correctly read out by the gate voltage of VG1 at the gate terminal 13 is the time period from T0 to T2, and the time period during which the memory level "1" can be correctly read out by the gate voltage VG3 at the gate terminal 14 is the time period from T0 to T1. This means that the memory level in the non-volatile memory 3' is erroneously read out as "0" after the time T1.
Then, the output of the interrogation circuit 4 causes the alarm circuit 5, which has been previously reset by the turning-on of the power source, to set and issue an alarm signal WA. This alarm signal WA is given to the reprogram control circuit 6, which lets a timing signal generator 15 operate to produce a sequence of a read-out signal R, an erase signal E and a write-in signal W, which are to be applied to the terminals 19 and 16, 20 and 21, respectively with the belowmentioned logic levels.
FIG. 8 (a) to FIG. 8 (j) are timing diagrams of the logic levels and the voltages of various parts of the circuit shown in FIG. 6. FIG. 8 (a) shows an output signal of a turn-on detection circuit 10. FIG. 8 (b) shows the output signal WA of the alarm circuit 5. FIG. 8 (c) shows the gate voltage VG1 of the non-volatile memory 1'. FIG. 8 (d) shows the gate voltage VG3 of the non-volatile memory 3'. FIG. 8 (e) shows an output signal at a terminal X of the first interrogation circuit 2. FIG. 8 (f) shows an output signal at a terminal Y of the second interrogation circuit 4. FIG. 8 (g) shows the read-out signal R, FIG. 8 (h) the erase signal E, FIG. 8 (i) the write-in signal W and FIG. 8 (j) an end signal ER to indicate an end of memory reprogramming, respectively. The dotted lines in FIG. 8 (e) and FIG. 8 (f) indicate that their logic levels can be arbitrary during erasing and writing-in operation.
The read-out signal R generated by the timing signal generator 15 is applied to a memory circuit 8 through the terminal 16, and an inverted signal R of the read-out signal R is applied to the gate of a transistor for read-out 17 of the first interrogation circuit 2 and to the gate of a transistor for read-out 18 of the second interrogation circuit 4 through the terminal 19. An inverted signal E of the erase signal E is applied to the substrates of the non-volatile memory devices 1' and 3' through the terminal 20. The write-in signal W is applied to a NAND gate 22 and an inverter 23 through the terminal 21. The end signal ER for memory reprogramming is applied to the alarm circuit 5. A power source is connected to terminals 28 and 29.
The circuit operation by these signals is now elucidated. When a pulse r of the read-out signal R of FIG. 8 (g) is applied to the terminal 16, the memory level of the non-volatile memory 1' is transmitted to a delayed flip flop (D-FF) 25 through the terminal X and an AND gate 24. Then, a pulse e of the erase signal E is generated after the fall-down of the pulse r of the read-out signal R as shown in FIG. 8 (h). The inverted signal E is applied to the terminal 20 after the abovementioned transmission of the memory state. As a result, the memories of both non-volatile memory devices 1' and 3' are erased after the completion of the transmission of the memory state.
Then, after the erasing, the pulse w of the write-in signal W is generated and memory contents of the D-FF 25 are written into the non-volatile memory 1' through the NAND gate 22 and a writing transistor 26. And also, the memory level "1" is written into the non-volatile memory 3' through the inverter 23 and another writing transistor 27. During this write-in operation, the gate potentials of the non-volatile memory devices 1' and 3' become to those of the write-in potentials. After the abovementioned sequence of these timing signals is generated, the pulse er of the end signal ER for memory reprogramming is finally generated, thereby resetting the alarm circuit 5, and completing the whole operation for memory reprogramming.
As elucidated above, memory levels which have considerably decayed at the time T1 from the initial level, are rewritten to the initial "1" level by means of the several amplifier stages.
The operation of the circuit of FIG. 6 can be made to reprogram the memory states when the power is turned on. By using a switch linked to a power source turn-off switch in place of the power source turn-on detection circuit of the previous example and by introducing a suitable time delay circuit which delays an actual turn-off of the power source to be after the time of the mechanical turn-off of the linked switch by a specified time period, it is also possible to reprogram the memory data when the power source is turned off.
When plural number of memory devices are formed in the device fabrication, their electrical characteristics may be slightly different from each other. In case that the memory devices in the second non-volatile memory part 3 have the memory characteristics not identical to, but similar to those of the memory devices in the first non-volatile memory part 1, it is possible to detect the memory levels more precisely by detecting the memory level of a memory device in which the memory level first reaches a specified level (e.g. M11) which is different from the initially memorized level.
The data pattern of the reprogramming "1" and "0" consists of or either one of them and this pattern is always same one controlled by pulse signals to be applied to the gate of the memory devices.
As elucidated above, according to the non-volatile memory control circuit of the present invention, memory states of the non-volatile memory devices can be held in valid states semipermanently and circuit condition of the non-volatile memory parts including non-volatile memory devices is kept in right circuit condition.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3761901 *||Jun 28, 1972||Sep 25, 1973||Ncr||Nonvolatile memory cell|
|US3771148 *||Mar 31, 1972||Nov 6, 1973||Ncr||Nonvolatile capacitive memory cell|
|US3796998 *||Sep 7, 1971||Mar 12, 1974||Texas Instruments Inc||Mos dynamic memory|
|1||*||Johnson, Self-Actuating Refresh Scheme for Dynamic Memories, IBM Tech. Disc. Bul., vol. 20, No. 11A, 4/78, pp. 4399-4400.|
|2||*||Shattuck et al., Memory Protection System, IBM Tech. Disc. Bul., vol. 9, No. 6, 11/66, pp. 731-734.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US4393481 *||Nov 21, 1980||Jul 12, 1983||Xicor, Inc.||Nonvolatile static random access memory system|
|US4393500 *||Aug 20, 1980||Jul 12, 1983||Fujitsu Fanuc Limited||Method of modifying data stored in non-volatile memory and testing for power failure occurring during modification|
|US4517663 *||Dec 22, 1983||May 14, 1985||Fujitsu Fanuc Limited||Method of rewriting data in non-volatile memory, and system therefor|
|US4564922 *||Oct 14, 1983||Jan 14, 1986||Pitney Bowes Inc.||Postage meter with power-failure resistant memory|
|US4633444 *||Sep 30, 1983||Dec 30, 1986||Toko, Inc.||Switch circuit provided with means for setting up the initial condition thereof|
|US4691303 *||Oct 31, 1985||Sep 1, 1987||Sperry Corporation||Refresh system for multi-bank semiconductor memory|
|US4800528 *||Dec 3, 1987||Jan 24, 1989||U.S. Philips Corporation||Non-volatile memory having charge correction circuitry|
|US4947378 *||May 16, 1988||Aug 7, 1990||Nec Corporation||Memory element exchange control circuit capable of automatically refreshing a defective address|
|US5052002 *||Aug 20, 1990||Sep 24, 1991||Oki Electric Industry Co., Ltd.||Method of detecting and indicating errors in a memory device|
|US5414671 *||Apr 30, 1991||May 9, 1995||Sharp Kabushimi Kaisha||Semiconductor memory device having operation control means with data judging function|
|US5590340 *||Apr 1, 1994||Dec 31, 1996||Matsushita Electric Industrial Co., Ltd.||Apparatus and method for suspending and resuming software application on a computer|
|US5652720 *||Dec 18, 1995||Jul 29, 1997||Sgs-Thomson Microelectronics S.A.||Electrically programmable memory with improved retention of data and a method of writing data in said memory|
|US6049899 *||Jul 8, 1998||Apr 11, 2000||Zilog, Inc.||Soft errors handling in EEPROM devices|
|US6169691||Sep 15, 1999||Jan 2, 2001||Stmicroelectronics S.R.L.||Method for maintaining the memory content of non-volatile memory cells|
|US6894926||Apr 30, 2003||May 17, 2005||Sandisk Corporation||Multi-state memory|
|US6898117||Oct 18, 2001||May 24, 2005||Sandisk Corporation||Multi-bit-per-cell flash EEPROM memory with refresh|
|US7170781||Apr 7, 2005||Jan 30, 2007||Sandisk Corporation||Multi-bit-per-cell flash EEPROM memory with refresh|
|US7173852||Oct 18, 2005||Feb 6, 2007||Sandisk Corporation||Corrected data storage and handling methods|
|US7224607||Nov 10, 2005||May 29, 2007||Sandisk Corporation||Flash memory data correction and scrub techniques|
|US7289360||Jan 11, 2006||Oct 30, 2007||Sandisk Corporation||Multi-state memory|
|US7315916||Dec 16, 2004||Jan 1, 2008||Sandisk Corporation||Scratch pad block|
|US7345934||Apr 14, 2005||Mar 18, 2008||Sandisk Corporation||Multi-state memory|
|US7395404||Dec 16, 2004||Jul 1, 2008||Sandisk Corporation||Cluster auto-alignment for storing addressable data packets in a non-volatile memory array|
|US7397697||Jan 5, 2007||Jul 8, 2008||Sandisk Corporation||Multi-bit-per-cell flash EEPROM memory with refresh|
|US7437631||Aug 13, 2004||Oct 14, 2008||Sandisk Corporation||Soft errors handling in EEPROM devices|
|US7443723||Mar 24, 2004||Oct 28, 2008||Sandisk Corporation||Multi-state memory|
|US7457162||Oct 5, 2007||Nov 25, 2008||Sandisk Corporation||Multi-state memory|
|US7477547||Mar 28, 2007||Jan 13, 2009||Sandisk Corporation||Flash memory refresh techniques triggered by controlled scrub data reads|
|US7518919||May 14, 2007||Apr 14, 2009||Sandisk Corporation||Flash memory data correction and scrub techniques|
|US7548461||Jun 22, 2004||Jun 16, 2009||Sandisk Corporation||Soft errors handling in EEPROM devices|
|US7573773||Mar 28, 2007||Aug 11, 2009||Sandisk Corporation||Flash memory with data refresh triggered by controlled scrub data reads|
|US7616484||Oct 26, 2004||Nov 10, 2009||Sandisk Corporation||Soft errors handling in EEPROM devices|
|US7716538||Sep 27, 2006||May 11, 2010||Sandisk Corporation||Memory with cell population distribution assisted read margining|
|US7839685||Oct 1, 2009||Nov 23, 2010||Sandisk Corporation||Soft errors handling in EEPROM devices|
|US7886204||Sep 27, 2006||Feb 8, 2011||Sandisk Corporation||Methods of cell population distribution assisted read margining|
|US8004895||Mar 31, 2009||Aug 23, 2011||Sandisk Technologies Inc.||Flash memory data correction and scrub techniques|
|US8050095||Nov 12, 2010||Nov 1, 2011||Sandisk Technologies Inc.||Flash memory data correction and scrub techniques|
|US8473813||Jan 4, 2011||Jun 25, 2013||Sandisk Technologies Inc.||Methods of cell population distribution assisted read margining|
|US8687421||Mar 30, 2012||Apr 1, 2014||Sandisk Technologies Inc.||Scrub techniques for use with dynamic read|
|US20030021149 *||Oct 18, 2001||Jan 30, 2003||So Hock C.||Multi-bit-per-cell flash EEPROM memory with refresh|
|US20040042294 *||Apr 30, 2003||Mar 4, 2004||Guterman Daniel C.||Novel Multi-state memory|
|US20040237010 *||Jun 22, 2004||Nov 25, 2004||Auclair Daniel L.||Soft errors handling in EEPROM devices|
|US20050058008 *||Aug 13, 2004||Mar 17, 2005||Auclair Daniel L.||Soft errors handling in eeprom devices|
|US20050083726 *||Oct 26, 2004||Apr 21, 2005||Auclair Daniel L.||Soft errors handling EEPROM devices|
|US20060039196 *||Oct 18, 2005||Feb 23, 2006||Gorobets Sergey A||Corrected data storage and handling methods|
|US20060062048 *||Nov 10, 2005||Mar 23, 2006||Gonzalez Carlos J||Flash memory data correction and scrub techniques|
|US20060129751 *||Jan 11, 2006||Jun 15, 2006||Guterman Daniel C||Novel multi-state memory|
|US20060136655 *||Dec 16, 2004||Jun 22, 2006||Gorobets Sergey A||Cluster auto-alignment|
|US20060161722 *||Dec 16, 2004||Jul 20, 2006||Bennett Alan D||Scratch pad block|
|US20070104004 *||Jan 5, 2007||May 10, 2007||So Hock C||Multi-Bit-Per-Cell Flash EEprom Memory with Refresh|
|US20080130364 *||Jan 17, 2008||Jun 5, 2008||Guterman Daniel C||Novel Multi-State Memory|
|US20080239808 *||Mar 28, 2007||Oct 2, 2008||Lin Jason T||Flash Memory Refresh Techniques Triggered by Controlled Scrub Data Reads|
|US20080239851 *||Mar 28, 2007||Oct 2, 2008||Lin Jason T||Flash Memory with Data Refresh Triggered by Controlled Scrub Data Reads|
|US20090187785 *||Jul 23, 2009||Gonzalez Carlos J||Flash Memory Data Correction And Scrub Techniques|
|EP0039449A1 *||Apr 23, 1981||Nov 11, 1981||Matsushita Electric Industrial Co., Ltd.||A memory refreshing arrangement|
|EP0156417A1 *||Feb 28, 1985||Oct 2, 1985||Philips Electronics N.V.||Semiconductor device having at least a non-volatile memory transistor|
|EP0225441A2 *||Sep 17, 1986||Jun 16, 1987||Texas Instruments Incorporated||Programming current controller|
|EP0307958A2 *||Sep 19, 1988||Mar 22, 1989||Oki Electric Industry Company, Limited||Eeprom system with bit error detecting function|
|EP0718849A1 *||Dec 14, 1995||Jun 26, 1996||Sgs-Thomson Microelectronics S.A.||Method of writing data in a memory and corresponding electrically programmable memory|
|EP0987715A1 *||Sep 15, 1998||Mar 22, 2000||SGS-THOMSON MICROELECTRONICS S.r.l.||Method for maintaining the memory of non-volatile memory cells|
|U.S. Classification||365/222, 365/228|
|International Classification||G11C16/34, G11C16/10, G11C11/406, G11C11/34|
|Cooperative Classification||G11C16/3431, G11C11/406, G11C16/10, G11C16/3418|
|European Classification||G11C16/34D6, G11C16/34D, G11C11/406, G11C16/10|