|Publication number||US4319343 A|
|Application number||US 06/169,307|
|Publication date||Mar 9, 1982|
|Filing date||Jul 16, 1980|
|Priority date||Jul 16, 1980|
|Publication number||06169307, 169307, US 4319343 A, US 4319343A, US-A-4319343, US4319343 A, US4319343A|
|Inventors||Robert W. Powell|
|Original Assignee||Honeywell Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (1), Referenced by (30), Classifications (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to digital computer memories. More specifically, the present invention is directed to a selection circuit for programming digital computer memory circuits.
An object of the present invention is to provide a novel programmable digital memory circuit for enabling memory circuit selection and data substitution in digital computer memory circuits.
In accomplishing this and other objects, there has been provided, in accordance with the present invention, a programmable memory circuit having a plurality of read only memories and a digital storage means having addressable storage locations. A circuit means applies sequential memory addresses in parallel to the memories and the storage means while control signal means responds to the memory addresses to concurrently enable and disable either the memories or the storage means.
A better understanding of the present invention may be had when the following detailed description is read in connection with the accompanying drawing, in which the single figure is a block diagram of a programmable digital memory circuit embodying an example of the present invention.
1. Detailed Description
Referring to the single figure drawing in more detail, there is shown a block diagram of a programmable digital memory circuit embodying an example of the present invention for selecting ones of a plurality of read only memory (ROM) chips. The ROM chips are inserted into respective memory sockets A through H on a printed circuit card to form a first memmory bank, such memory chips and sockets being well-known in the art. A first group of memory address bits 0 to 10 from any suitable memory address circuit (not shown) for reading the data stored in a memory bank are connected in parallel to corresponding address input pins on each of the memory sockets A through H and to a first programmable read only memory identified as a mapping PROM 2. The PROM 2 is also supplied on inuts A1 through A6 with a second group of memory address bits 11 through 15 and a memory write signal on input A7. The outputs of the mapping PROM 2 selected by address bits 11 to 15 on output lines D1 through D7 are used to select the memory socket to be utilized. Specifically, output lines D1 and D2 are applied to pins 18 and 21 on each of the sockets A through B as socket selection signals. Output lines D3, D4 and D5 are applied to a three to eight decoder 4 used to decode the status of the digital signals on the three lines D3, D4 and D5 to ones of a plurality of eight output lines applied to respective ones of the sockets A through H on pin 20 of each of the sockets A through H. The output lines D6 and D7 from the mapping PROM 2 are used to select among memory banks with each memory bank having a group of the IC sockets similar to those shown as sockets A through H.
Memory address bits 5 through 13 are also applied to the address inputs of a second programmable read only memory identified as an overlay trap PROM 6. The outputs D0, D1, D2 and D3 from the overlay trap PROM 6 selected by the address bits 5 to 13 are applied to respective inputs 1C, 2C, 3C and 4C of a select 1 of 4 circuit 8. Memory address bits 14 and 15 are applied to respective inputs A and B of the select 1 of 4 logic circuit 8. An output from the logic circuit 8 on input 1Y is used as an overlay enable signal and is applied through an inverter 10 to an overlay patch PROM 12 and to each of the memory sockets A through H on signal line 14 to an enable input terminal. The "3 to 8 decoder 4" and the select 1 of 4 circuit 8 are devices which are well-known in the art and are available as integrated circuit chips.
The memory address bits 0 to 10 are applied to all of the memory integrated circuit sockets A through H to effect a memory ready operation from the memory chips of the ROMS plugged into the sockets A to H. The output from a memory chip however is determined by the combination of additional output signals from the mapping PROM 2 and the three to eight decoder 4 which combination enables a specific memory chip in the sockets A to H to be selected. Specifically, the memory address bits 11 to 15 are applied to inputs A1 through A5 of the mapping PROM 2 while a memory "write" signal is applied to enable input A6 of the mapping PROM 2 to be used when a random access memory chip is used in any of the sockets A to H. The mapping PROM 2 has output signals on outputs D1 through D7 which are produced as a result of the memory address bits 11 through 15 and the memory write signal. The outputs D1 and D2 are applied in parallel to all of the memory sockets A through H on pins 18 and 21. However, the outputs D1 and D2 are configured or selected for each memory address to be applicable to the one of the memory chips in the sockets A through H selected by the outputs D3 to D5 whereby all of the other memory chips would be non-responsive thereto.
The outputs from the mapping PROM 2 shown as outputs D3, D4, and D5 are applied to a three to eight decoder 4 which is effective to produce an output signal on one of eight output lines in response to combination of the three input signals applied thereto. These output lines are applied to the enable input 20 of each of the memory sockets A through H. Thus, only the desired one of the primary chips in one of the sockets A through H is enabled by an output signal on one of the output lines from the three to eight decoder 4. The outputs D6 and D7 from the mapping PROM are used to select banks of memory chips. Thus, in the illustrated example, each memory bank would have eight memory sockets A through H, and the select one and select two signals from the outputs D6 and D7, respectively, of the mapping PROM 2 would be configured to select one of four banks of memory IC sockets, i.e., a selection of eight memory sockets from a total of 32 memory sockets available in the memory system. Thus, the memory address bits 0 to 10 are applied to all of the memory chips of the read only memories, however, only the memory chip selected by the mapping PROM 2 is effective to produce an output signal on the output lines from the memory socket. Thus, the circuit can use many different types of memory chips (ROMS) without altering the physical layout of the printed circuit board by assigning to each data byte in the mapping PROM both the socket address of where the memory chip being accessed is located and the correct configuration of the pins 18 and 21 on the socket having the memory chip desired. Since pins 18 and 21 on the most popular memory chips are the only pins that differ in configuration between chip types, the selection of these pins independently per socket allows many different types of memory chips to be located concurrently on a printed circuit board without the necessity of having all the memory chips be of an identical type.
In order to either correct the firmware code errors or permit expansion of firmware memory read only memory (ROM) chips, an overlay patch PROM 12 is used to substitute information stored in the overlay patch PROM 12 for information requested from various locations in the memory chips used in the memory sockets A through H. Thus, code corrections are made by overlaying a portion of the overlay patch PROM 12 at an address code which is found in an overlay trap PROM 6. Initially, the overlay trap PROM 6 is unprogrammed whereby all locations are logical lows. Each bit location in the overlay trap PROM 6 can act as an enable/disable selection for a 32 byte data block in the overlay trap PROM. When a bit location in the overlay trap PROM is previously programmed, i.e., converted to a logical high, and when the memory address bits 0 to 10 select that location in the main firmware memory of the sockets A through H, the main firmware is disabled by the signal on the overlay enable line 14 which signal concurrently enables the patch PROM 12 through the logic invertor 10 and the information in the patch PROM 12 is selected by the address bits 0 to 10 and substituted therefore. Since there are 256 bit locations in a typical overlay trap PROM 6 there are 256 32 byte patches from the patch PROM 12 which may be substituted for the main firmware memory data. Each data patch may be added simply by coding one more location in the overlay trap PROM 6 and inserting the corrected firmware code into the overlay patch PROM 12. The memory address bits 5 to 13 and 14 to 15 are used in a combination of the overlay trap PROM 6 and the select one of four circuit 8 to develop an enable signal on line 14 for the overlay patch PROM 12 to provide substitute data for a location in one of the memory chips in the sockets A through H. The first five memory address bits 0 to 4 are not used for the trap PROM 6 addresses since the patches are in 32 byte lengths whereby the first five address bits can be ignored 25 =32. Such a system is designed specifically to facilitate program changes, error connections and expansions of firmware. This facilitates the progress of a program memory development to be advanced to a so-called masked ROM at an early stage on a program design project and eliminates the need to fill memory bank sockets A to H with more expensive reprogrammable versions of the memory chips whenever a growth is expected in the firmware design.
Accordingly, it may be seen that there has been provided, in accordance with the present invention, an improved memory programming circuit for providing memory selection independent of memory chip type and substitution of information at locations within any of the memory chips. While the example utilizes a direct disable of memory chips, if such a disable function is not available at the chip, then the disable function can be attained by disabling the 3 to 8 decoder 4 when the patch PROM 12 is enabled and vice versa.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4048626 *||Dec 29, 1975||Sep 13, 1977||Honeywell Information Systems Inc.||Memory device|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US4603399 *||Dec 27, 1983||Jul 29, 1986||International Business Machines Corporation||Data processing apparatus for address substitution|
|US4610000 *||Oct 23, 1984||Sep 2, 1986||Thomson Components-Mostek Corporation||ROM/RAM/ROM patch memory circuit|
|US5040153 *||Feb 1, 1990||Aug 13, 1991||Chips And Technologies, Incorporated||Addressing multiple types of memory devices|
|US5404475 *||Feb 3, 1992||Apr 4, 1995||Fujitsu Limited||Memory apparatus comprising memory cards with a side detecting signal pin and address assignment circuitry|
|US5454100 *||Mar 2, 1995||Sep 26, 1995||Sony Corporation||Electronic apparatus|
|US5517630 *||Jun 20, 1994||May 14, 1996||Canon Kabushiki Kaisha||Electronic apparatus featuring a plurality of selectable memories|
|US5551012 *||Mar 8, 1994||Aug 27, 1996||Acer Incorporated||Single socket upgradeable computer motherboard with automatic detection and socket reconfiguration for inserted CPU chip|
|US5619678 *||Sep 16, 1993||Apr 8, 1997||Sony Corporation||Electronic device for correction of ROM data with a parameter for calculation of position of correction data|
|US5623665 *||Mar 13, 1995||Apr 22, 1997||Sony Corporation||Electronic apparatus for patching a read-only memory|
|US5731972 *||May 20, 1996||Mar 24, 1998||Sony Corporation||Electronic apparatus which inhibits control of certain objects during initialization processing|
|US5742742 *||May 20, 1994||Apr 21, 1998||Canon Kabushiki Kaisha||Printing system for determining if there is enough memory to store revised program and controlling the system using control program with the revised program|
|US5761479 *||Mar 31, 1995||Jun 2, 1998||Acer Incorporated||Upgradeable/downgradeable central processing unit chip computer systems|
|US6065090 *||Oct 6, 1997||May 16, 2000||Memory Corporation Plc||Memory management apparatus that replaces defective storage locations with functional storage locations|
|US6128751 *||Jun 6, 1995||Oct 3, 2000||Sony Corporation||Electronic apparatus and method for patching a fixed information|
|US6189145||May 28, 1997||Feb 13, 2001||International Business Machines Corporation||Concurrent patch to logical partition manager of a logically partitioned system|
|US6223147 *||Mar 31, 1993||Apr 24, 2001||Intel Corporation||Multiple use chip socket for integrated circuits and the like|
|US6237120||Jan 4, 1995||May 22, 2001||Sony Corporation||Program patching of a ROM|
|US6421679||Oct 27, 1995||Jul 16, 2002||International Business Machines Corporation||Concurrent patch to logical partition manager of a logically partitioned system|
|US7533240 *||Aug 1, 2005||May 12, 2009||Marvell International Ltd.||Device with mapping between non-programmable and programmable memory|
|US20090031090 *||Jul 24, 2007||Jan 29, 2009||Via Technologies||Apparatus and method for fast one-to-many microcode patch|
|US20090031103 *||Jul 24, 2007||Jan 29, 2009||Via Technologies||Mechanism for implementing a microcode patch during fabrication|
|US20090031107 *||Jul 24, 2007||Jan 29, 2009||Via Technologies||On-chip memory providing for microcode patch overlay and constant update functions|
|US20090031108 *||Jul 24, 2007||Jan 29, 2009||Via Technologies||Configurable fuse mechanism for implementing microcode patches|
|US20090031109 *||Jul 24, 2007||Jan 29, 2009||Via Technologies||Apparatus and method for fast microcode patch from memory|
|US20090031110 *||Jul 24, 2007||Jan 29, 2009||Via Technologies||Microcode patch expansion mechanism|
|US20090031121 *||Jul 24, 2007||Jan 29, 2009||Via Technologies||Apparatus and method for real-time microcode patch|
|EP0405498A2 *||Jun 27, 1990||Jan 2, 1991||Canon Kabushiki Kaisha||Electronic apparatus having read-only memories|
|EP2026199A1 *||Aug 21, 2007||Feb 18, 2009||VIA Technologies, Inc.||Microcode patch expansion mechanism|
|WO1992008231A1 *||Nov 1, 1991||May 14, 1992||Transcomputer, Inc.||Rom patch device|
|WO1996031825A1 *||Feb 14, 1996||Oct 10, 1996||Memory Corporation Plc||Memory management|
|U.S. Classification||365/196, 365/104, 365/230.04|