|Publication number||US4320438 A|
|Application number||US 06/149,968|
|Publication date||Mar 16, 1982|
|Filing date||May 15, 1980|
|Priority date||May 15, 1980|
|Also published as||CA1154541A, CA1154541A1, DE3119239A1|
|Publication number||06149968, 149968, US 4320438 A, US 4320438A, US-A-4320438, US4320438 A, US4320438A|
|Inventors||Shawki Ibrahim, James E. Elsner|
|Original Assignee||Cts Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Referenced by (92), Classifications (50)|
|External Links: USPTO, USPTO Assignment, Espacenet|
In "packaging" interconnected chip or chip arrays, wire bondings from the chip or chip array, particularly where there is a high component density, or where bonding pads on chips are closely spaced, are excessively crowded so that there is a real danger that the wire bonds will come into too close contact with each other and present a serious difficulty in maintaining required spacing for the wires and the bonding lands. This is because the conductive patterns converge upon the chips from the printed metalized patterns provided on the single ceramic lamina. The result is overcrowding of the wire conductor or bondings. However, the trend in multiple circuit chip structures, is toward even greater component density, and the conductive patterns on the ceramic package must be wire bonded to the chips of the array.
Thus, the technology trend, headed as it is toward even greater component density, presents serious and thus far unsolved problems of how to achieve the necessary pin outs, from LSI (large scale integrated) arrays though wire bondings to the metalized conductive patterns while still maintaining an industry imposed standard of 10 mil spacings for the pin out wire bonds.
It is a principal object of the present invention to provide a high component density, multi-layer chip carrier in which wire bonds are connected to a single chip or to chips interconnected in a chip array, with the wire bondings then disposed for pin-outs at alternately different layers in the ceramic package, thus achieving greater clearance for the respective wire bonds and wire bonding lands.
Another object of the present invention, is to provide an interconnected chip array disposed within a cavity of a multi-layer ceramic package, in which the wire bonds are successively secured between the chip array at one end and to different levels of a multi-layer ceramic package at the other end. The respective levels of the ceramic package are individually metalized for a particular conductive pattern, and the patterns are connected through either or both of metalized connections in the form of "tunneled through" openings from one layer to the other and edge metalizations so that the respective conductive patterns are connected, leading ultimately to a series of pads at the undersurface of the ceramic package.
Another object of the present invention, is to increase the density of an interconnected LSI chip array while at the same time providing the necessary pin outputs for wire bondings leading to such array and while maintaining the requisite 10 mil spacing and 10 mil width of metalized wire bonding lands.
An overall object of the present invention is to provide a multi-layer ceramic package having various level lamina each with a particular conductive pattern, the patterns on the respective layers being connected by either tunneled through or edge metalization bonding, or both. Various pin outs from a central disposed interconnected chip array, disposed within a cavity are connected through wire bonds with said patterns while maintaining an appropriate spacing one relative to the other.
Other objects and features of the present invention will become apparent from a consideration of the following description which proceeds with reference to the accompanying drawings in which selected example embodiments are illustrated by way of example, and not by way of limitation.
FIG. 1 is an isometric exploded view illustrating the multi-layer ceramic package, with a printed circuit board at the lower portion and a combination ring-and-cover at the upper end which seals an internal cavity in the ceramic package for receiving a chip array;
FIG. 2 is an isometric detail view of a multi-layer ceramic package with the ring and cover removed;
FIG. 3 is a section view taken on Line 3--3 of FIG. 2 showing the metalized edges, tunnels, and wire bond-pattern connections between the chip array and the various levels of the multi-layer ceramic package;
FIG. 4 is the undersurface of the base layer of the ceramic package to be mounted to the metalized board;
FIG. 4a is the upper surface of the base layer of the ceramic package and is the opposite face to that of FIG. 4; and,
FIG. 5 is an enlarged detail view of the ball bond and wedge bond leads of the wire between the chip array at one wire end and a respective layer of the ceramic package at the other wire end.
Referring to FIG. 1, a multi-layer ceramic package designated generally by reference numeral 10 includes multi-layers of ceramic substrate including a base layer 12, intermediate layer 14 on which is mounted an interconnected chip array 16, an upper frame layer 18, a ring layer 20, and a cover layer 22. The multi-layer ceramic package as a whole is mounted on a metalized board 24.
The base layer 12, intermediate layer 14, and frame layer 18 each has a printed conductive pattern illustrated by reference numeral 26 in the base layer 12, by reference numeral 28 in the intermediate layer, and by reference numeral 30 for the frame layer 18. The particular pattern of these conductive metalization paths is not a part of the present invention. However, it is contemplated that prior to assembly, the "green" or unfused ceramic substrates have formed thereon the conductive patterns which are then matched together and electrically connected through connections leading ultimately to pads 33 on the undersurface 31 (FIG. 4) of the base layer 12 for the metalized board 24.
The conductive patterns are communicated one layer with the next, in one instance through "tunnels" 32 (FIG. 3) which are in the form of vertical through openings filled with metalization, and which connect the conductive patterns of one layer to the next. In another form the conductive patterns of the respective lamina are connected through edge metalizations 34 (FIG. 3).
The interconnected chip array 16 consists of component LSI chips which are connected together. The chips are connected by metalization printed circuits constructed on the confronting surface of intermediate layer 14, and indicated by reference numeral 36.
Between the chips, and to obviate the necessity for the wire bondings to be connected from a chip first outwardly to the periphery of the package and then back to another chip, there can be chip-to-chip wire bonding through lands 38 disposed between and separating the chips 40. These wire bonds are designated generally by reference numeral 42. There is thus, the interconnections necessary to form a high density interconnected chip array which has pin out connections to the conductive patterns at the respective laminations of the multi-layer ceramic package.
With the high component density described, it is difficult to maintain 10 mil spacing which is required for conductive patterns. This is achieved in the present invention, in the manner illustrated in FIGS. 2 and 3. As shown in FIGS. 2 and 3, the wire bonds converge upon the chip array connected at one end through a ball bond 44 (FIG. 5) to a chip 40 and at the other end through a wedge bond 46 to a conductive pattern on one or the other of the intermediate layer 14 or frame layer 18. In spite of the high density of LSI chip components and wire bonds, the 10 mil spacing of the conductive patterns is nontheless maintained by alternating between layers 14 and 18.
Obviously, there can more than two alternating layers; three, four, or even more layers for alternate wire bonding are contemplated. But the idea, generally, is that by coupling the wire bonds between the centrally disposed high density chip array, and alternately different levels of the metalized layers, it is possible to increase the number of wire bonds and thus achieve the desired centrally disposed component density while in no way compromising the necessary 10 mil spacing for the conductive patterns.
The wire bonds between the central array and the conductive patterns at the various levels, make appropriate connections from layer-to-layer as described, either through tunnels 32 or edge metalizations 34 (FIGS. 3 and 4a) all of which ultimately lead to the base layer 12 and underlying pads 33 which are then bonded to appropriate locations on an underlying metalized board 24. The laminas may typically consist of aluminum silicate or other inert substrate materials, which, as stated previously, are green at the time the metalizations, tunnel, and edge metalizations are formed thereon. Then the green laminas are fired to hermetically seal the laminas together to produce a monolithic ceramic package.
The layers having a conductive pattern, the ring 20, and the chip array, once the chip array is fixed and wire bondings made with the centrally disposed array, are surmounted with cover layer 22. The package as a whole is next fired (sealed) and the final product mounted onto the metalized board 24.
The chip array is mounted on the intermediate layer 14, and the chips 40 of the array are communicated chip-to-chip through lands 38 on the upper face of the intermediate layer 14, and other layers as required.
The chip array has wire bond connections 42 to the metalized ceramic conductor patterns, by bonding the ends of the wire bonds so that adjacent wire bonds are connected from the chip array to alternating levels in the multi-layer ceramic package.
The package as a whole, is next mounted on metalized board 24 so that the pads 33 at the exterior surface of the package are mounted on various terminals of the metalized board having a predetermined printed circuit architecture and componentry.
It should be understood that any conductive pattern can be screened onto the surface of the respective layers of the multi-layer ceramic package, and the conductive patterns as such, i.e. the particular architecture or pattern per se, does not form a part of the present invention.
It should be further emphasized that the 10 mil spacing is achievable in the present invention by reason of connecting first one wire from the chip array to a first level and then alternating the wire bonds to a second level, a third level, a fourth level, etc. thereby providing the means for maintaining a 10 mil of conductive patterns spacing in spite of the increased component density and the central converging of such wires. Quite obviously, if the 10 mil spacing is not maintained as an industry standard, it is equally possible to obtain an even higher component density with either an agreed upon less than 10 mil spacing and/or less than 10 mil bonding lands.
In all events, the present invention provides a possibility of maximum component density while maintaining a 10 mil spacing, but is equally applicable to whatever component density is desired, while achieving an inherently greater density for the respective wire bonds.
Although the present invention has been illustrated and described in connection with a single example embodiment, it will be understood that this is illustrative of the invention and is by no means restrictive thereof. For example, instead of three ceramic layers of the multi-layer ceramic package, it is possible to use four, five, or any number desired to achieve the desired combination of wire spacing, multi-layering, and various arrangements for the printed circuit network as well as the architecture of interconnected chip array. All of these changes are contemplated as part of the present invention and it is intended that such variation shall be included within the scope of the following claims as equivalents of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3436604 *||Apr 25, 1966||Apr 1, 1969||Texas Instruments Inc||Complex integrated circuit array and method for fabricating same|
|US3436606 *||Apr 3, 1967||Apr 1, 1969||Texas Instruments Inc||Packaged multilead semiconductor device with improved jumper connection|
|US3651434 *||Apr 30, 1969||Mar 21, 1972||Microwave Semiconductor Corp||Microwave package for holding a microwave device, particularly for strip transmission line use, with reduced input-output coupling|
|US3676748 *||Mar 30, 1971||Jul 11, 1972||Fuji Electrochemical Co Ltd||Frame structures for electronic circuits|
|US3808475 *||Jul 10, 1972||Apr 30, 1974||Amdahl Corp||Lsi chip construction and method|
|US3926746 *||Oct 4, 1973||Dec 16, 1975||Minnesota Mining & Mfg||Electrical interconnection for metallized ceramic arrays|
|US4150420 *||Dec 15, 1977||Apr 17, 1979||Tektronix, Inc.||Electrical connector|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US4410927 *||Jun 21, 1982||Oct 18, 1983||Olin Corporation||Casing for an electrical component having improved strength and heat transfer characteristics|
|US4423468 *||May 4, 1982||Dec 27, 1983||Motorola, Inc.||Dual electronic component assembly|
|US4513355 *||Jun 15, 1983||Apr 23, 1985||Motorola, Inc.||Metallization and bonding means and method for VLSI packages|
|US4539622 *||Oct 25, 1984||Sep 3, 1985||Fujitsu Limited||Hybrid integrated circuit device|
|US4571451 *||Jun 4, 1984||Feb 18, 1986||International Business Machines Corporation||Method for routing electrical connections and resulting product|
|US4638348 *||Aug 8, 1983||Jan 20, 1987||Brown David F||Semiconductor chip carrier|
|US4659931 *||May 8, 1985||Apr 21, 1987||Grumman Aerospace Corporation||High density multi-layered integrated circuit package|
|US4682414 *||Jun 24, 1985||Jul 28, 1987||Olin Corporation||Multi-layer circuitry|
|US4688150 *||Apr 7, 1986||Aug 18, 1987||Texas Instruments Incorporated||High pin count chip carrier package|
|US4731700 *||Feb 12, 1987||Mar 15, 1988||Delco Electronics Corporation||Semiconductor connection and crossover apparatus|
|US4739443 *||Jul 20, 1987||Apr 19, 1988||Olin Corporation||Thermally conductive module|
|US4755910 *||Dec 17, 1986||Jul 5, 1988||Cimsa Sintra||Housing for encapsulating an electronic circuit|
|US4772820 *||Sep 11, 1986||Sep 20, 1988||Copytele, Inc.||Monolithic flat panel display apparatus|
|US4777615 *||Feb 28, 1986||Oct 11, 1988||Scientific Computer Systems Corporation||Backplane structure for a computer superpositioning scalar and vector operations|
|US4821151 *||Dec 20, 1985||Apr 11, 1989||Olin Corporation||Hermetically sealed package|
|US4827327 *||Jul 5, 1988||May 2, 1989||Fujitsu Limited||Integrated circuit device having stacked conductive layers connecting circuit elements therethrough|
|US4860442 *||Nov 28, 1988||Aug 29, 1989||Kulite Semiconductor||Methods for mounting components on convoluted three-dimensional structures|
|US4920454 *||Jul 1, 1988||Apr 24, 1990||Mosaic Systems, Inc.||Wafer scale package system and header and method of manufacture thereof|
|US5015207 *||Dec 28, 1989||May 14, 1991||Isotronics, Inc.||Multi-path feed-thru lead and method for formation thereof|
|US5016085 *||Mar 4, 1988||May 14, 1991||Hughes Aircraft Company||Hermetic package for integrated circuit chips|
|US5025114 *||Oct 30, 1989||Jun 18, 1991||Olin Corporation||Multi-layer lead frames for integrated circuit packages|
|US5031069 *||Dec 28, 1989||Jul 9, 1991||Sundstrand Corporation||Integration of ceramic capacitor|
|US5067004 *||Dec 13, 1989||Nov 19, 1991||Digital Equipment Corporation||Module for interconnecting integrated circuits|
|US5093708 *||Aug 20, 1990||Mar 3, 1992||Grumman Aerospace Corporation||Multilayer integrated circuit module|
|US5128749 *||Apr 8, 1991||Jul 7, 1992||Grumman Aerospace Corporation||Fused high density multi-layer integrated circuit module|
|US5151771 *||Jan 28, 1991||Sep 29, 1992||Ibiden Co., Ltd||High lead count circuit board for connecting electronic components to an external circuit|
|US5157588 *||May 29, 1991||Oct 20, 1992||Samsung Electronics Co., Ltd.||Semiconductor package and manufacture thereof|
|US5159750 *||Apr 3, 1991||Nov 3, 1992||National Semiconductor Corporation||Method of connecting an IC component with another electrical component|
|US5175397 *||Dec 24, 1990||Dec 29, 1992||Westinghouse Electric Corp.||Integrated circuit chip package|
|US5209798 *||Nov 22, 1991||May 11, 1993||Grunman Aerospace Corporation||Method of forming a precisely spaced stack of substrate layers|
|US5227583 *||Aug 20, 1991||Jul 13, 1993||Microelectronic Packaging America||Ceramic package and method for making same|
|US5231304 *||Jul 10, 1992||Jul 27, 1993||Grumman Aerospace Corporation||Framed chip hybrid stacked layer assembly|
|US5325268 *||Jan 28, 1993||Jun 28, 1994||National Semiconductor Corporation||Interconnector for a multi-chip module or package|
|US5397861 *||Oct 21, 1992||Mar 14, 1995||Mupac Corporation||Electrical interconnection board|
|US5422435 *||May 22, 1992||Jun 6, 1995||National Semiconductor Corporation||Stacked multi-chip modules and method of manufacturing|
|US5495398 *||Jun 5, 1995||Feb 27, 1996||National Semiconductor Corporation||Stacked multi-chip modules and method of manufacturing|
|US5502289 *||Mar 13, 1995||Mar 26, 1996||National Semiconductor Corporation||Stacked multi-chip modules and method of manufacturing|
|US5559306 *||Oct 11, 1995||Sep 24, 1996||Olin Corporation||Electronic package with improved electrical performance|
|US5579207 *||Oct 20, 1994||Nov 26, 1996||Hughes Electronics||Three-dimensional integrated circuit stacking|
|US5613861 *||Jun 7, 1995||Mar 25, 1997||Xerox Corporation||Photolithographically patterned spring contact|
|US5621190 *||Nov 23, 1994||Apr 15, 1997||Ngk Spark Plug Co., Ltd.||Ceramic package main body|
|US5629840 *||Mar 28, 1994||May 13, 1997||Digital Equipment Corporation||High powered die with bus bars|
|US5777265 *||May 21, 1997||Jul 7, 1998||Intel Corporation||Multilayer molded plastic package design|
|US5804004 *||May 24, 1996||Sep 8, 1998||Nchip, Inc.||Stacked devices for multichip modules|
|US5822851 *||Dec 31, 1996||Oct 20, 1998||Ngk Spark Plug Co., Ltd.||Method of producing a ceramic package main body|
|US5848685 *||Dec 20, 1996||Dec 15, 1998||Xerox Corporation||Photolithographically patterned spring contact|
|US5856235 *||Apr 12, 1995||Jan 5, 1999||Northrop Grumman Corporation||Process of vacuum annealing a thin film metallization on high purity alumina|
|US5914218 *||Dec 20, 1996||Jun 22, 1999||Xerox Corporation||Method for forming a spring contact|
|US5944537 *||Dec 15, 1997||Aug 31, 1999||Xerox Corporation||Photolithographically patterned spring contact and apparatus and methods for electrically contacting devices|
|US5979892 *||May 15, 1998||Nov 9, 1999||Xerox Corporation||Controlled cilia for object manipulation|
|US6077728 *||May 4, 1998||Jun 20, 2000||Ngk Spark Plug Co., Ltd.||Method of producing a ceramic package main body|
|US6124553 *||Jun 20, 1994||Sep 26, 2000||Hitachi, Ltd.||Multilayer wiring board having vent holes and method of making|
|US6184065||Mar 25, 1999||Feb 6, 2001||Xerox Corporation||Photolithographically patterned spring contact|
|US6184699||Dec 14, 1998||Feb 6, 2001||Xerox Corporation||Photolithographically patterned spring contact|
|US6213789||Dec 15, 1999||Apr 10, 2001||Xerox Corporation||Method and apparatus for interconnecting devices using an adhesive|
|US6255601 *||Apr 1, 1997||Jul 3, 2001||Applied Materials, Inc.||Conductive feedthrough for a ceramic body and method of fabricating same|
|US6264477||Apr 6, 2000||Jul 24, 2001||Xerox Corporation||Photolithographically patterned spring contact|
|US6331681 *||Mar 18, 1994||Dec 18, 2001||Kabushiki Kaisha Toshiba||Electrical connection device for forming and semiconductor device having metal bump electrical connection|
|US6439898||Feb 28, 2001||Aug 27, 2002||Xerox Corporation||Method and apparatus for interconnecting devices using an adhesive|
|US6791171||Jun 20, 2001||Sep 14, 2004||Nanonexus, Inc.||Systems for testing and packaging integrated circuits|
|US6815961||Mar 8, 2002||Nov 9, 2004||Nanonexus, Inc.||Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies|
|US7009412||Aug 12, 2004||Mar 7, 2006||Nanonexus, Inc.||Massively parallel interface for electronic circuit|
|US7247035||Sep 1, 2004||Jul 24, 2007||Nanonexus, Inc.||Enhanced stress metal spring contactor|
|US7349223||Jun 16, 2004||Mar 25, 2008||Nanonexus, Inc.||Enhanced compliant probe card systems having improved planarity|
|US7382142||May 18, 2005||Jun 3, 2008||Nanonexus, Inc.||High density interconnect system having rapid fabrication cycle|
|US7397186 *||Aug 23, 2004||Jul 8, 2008||Samsung Sdi Co., Ltd.||Plasma display panel|
|US7403029||Nov 1, 2006||Jul 22, 2008||Nanonexus Corporation||Massively parallel interface for electronic circuit|
|US7579848||Feb 7, 2006||Aug 25, 2009||Nanonexus, Inc.||High density interconnect system for IC packages and interconnect assemblies|
|US7621761||Jul 20, 2007||Nov 24, 2009||Nanonexus, Inc.||Systems for testing and packaging integrated circuits|
|US7772860||Jul 17, 2008||Aug 10, 2010||Nanonexus, Inc.||Massively parallel interface for electronic circuit|
|US7872482||Sep 19, 2007||Jan 18, 2011||Verigy (Singapore) Pte. Ltd||High density interconnect system having rapid fabrication cycle|
|US7884634||Jan 15, 2009||Feb 8, 2011||Verigy (Singapore) Pte, Ltd||High density interconnect system having rapid fabrication cycle|
|US7952373||Oct 23, 2006||May 31, 2011||Verigy (Singapore) Pte. Ltd.||Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies|
|US20040022042 *||Mar 8, 2002||Feb 5, 2004||Sammy Mok||Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies|
|US20040075455 *||Nov 19, 2003||Apr 22, 2004||Sammy Mok||Mosaic decal probe|
|US20050026476 *||Sep 1, 2004||Feb 3, 2005||Sammy Mok||Systems for testing and packaging integrated circuits|
|US20050051353 *||Aug 12, 2004||Mar 10, 2005||Chong Fu Chiung||Massively parallel interface for electronic circuit|
|US20050068054 *||Jul 9, 2004||Mar 31, 2005||Sammy Mok||Standardized layout patterns and routing structures for integrated circuit wafer probe card assemblies|
|US20050082977 *||Aug 23, 2004||Apr 21, 2005||Jae-Ik Kwon||Plasma display panel|
|US20060074836 *||May 5, 2005||Apr 6, 2006||Biowisdom Limited||System and method for graphically displaying ontology data|
|US20060186906 *||Feb 7, 2006||Aug 24, 2006||Bottoms W R||High density interconnect system for IC packages and interconnect assemblies|
|US20060240690 *||Sep 1, 2004||Oct 26, 2006||Sammy Mok||Systems for testing and packaging integrated circuits|
|US20070057684 *||Nov 1, 2006||Mar 15, 2007||Chong Fu C||Massively parallel interface for electronic circuit|
|US20070098895 *||Nov 27, 2006||May 3, 2007||Smith Donald L||Method and Apparatus for Producing Uniform, Isotropic Stresses in a Sputtered Film|
|US20070245553 *||Mar 27, 2007||Oct 25, 2007||Chong Fu C||Fine pitch microfabricated spring contact structure & method|
|US20080090429 *||Jul 20, 2007||Apr 17, 2008||Sammy Mok||Systems for testing and packaging integrated circuits|
|US20090153165 *||Jan 15, 2009||Jun 18, 2009||Fu Chiung Chong||High Density Interconnect System Having Rapid Fabrication Cycle|
|DE3538933A1 *||Nov 2, 1985||May 14, 1987||Bbc Brown Boveri & Cie||Leistungshalbleitermodul|
|EP0294015A1 *||Mar 11, 1988||Dec 7, 1988||Citizen Watch Co. Ltd.||A device having a circuit board for connecting a plurality of IC-chips|
|WO1993003871A1 *||Aug 17, 1992||Mar 4, 1993||Kenneth L Ii Jones||Improved ceramic package|
|WO1995031826A1 *||May 1, 1995||Nov 23, 1995||Olin Corp||Electronic packages with improved electrical performance|
|WO1996041506A1 *||May 30, 1996||Dec 19, 1996||Xerox Corp||Photolithographically patterned spring contact|
|U.S. Classification||361/764, 257/E23.173, 174/557, 174/535, 257/E23.062, 361/774, 257/E23.189, 361/776|
|International Classification||H01L23/057, H05K3/46, H01R12/04, H01L23/538, H01L23/498|
|Cooperative Classification||H01L24/45, H01L2924/12033, H01L2924/00014, H01L2224/451, H01L24/48, H01L23/057, H01L2924/01014, H01L2924/01082, H01L23/5383, H01L2224/49109, H01L2924/01033, H01L2224/48227, H01L2224/48091, H01L2924/15153, H01L2924/01006, H01L2924/01052, H01L2924/0101, H01L2924/15313, H01L2224/49433, H01L23/49822, H01L2924/01079, H01L2924/01057, H01L2924/01013, H01L2924/01042, H01L2224/48465, H01L2924/01075, H01L2924/01058, H01L2924/16195, H01L24/49, H01L2924/15787, H01L2924/01023, H01L2924/1517, H01L2924/12041|
|European Classification||H01L24/49, H01L23/538D, H01L23/498D, H01L23/057|