|Publication number||US4325747 A|
|Application number||US 06/038,895|
|Publication date||Apr 20, 1982|
|Filing date||May 14, 1979|
|Priority date||May 19, 1978|
|Also published as||DE2821975A1, DE2821975C2, EP0005461A1, EP0005461B1, US4425573|
|Publication number||038895, 06038895, US 4325747 A, US 4325747A, US-A-4325747, US4325747 A, US4325747A|
|Original Assignee||Siemens Aktiengesellschaft|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Non-Patent Citations (4), Referenced by (10), Classifications (18)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention relates to a metal-semiconductor-field effect transistor (MESFET).
Field effect transistors are known in which the gate electrode is supported directly on the semiconductor surface between the source area and the drain area and forms a metal-semiconductor (Schottky) contact. Such field effect transistors are designated as MESFET's. Such a MESFET is built up, for example, on a semiconductor layer located on an insulating substrate, whereby the layer thickness generally amounts from 0.1 to 0.5 μm and the doping of this semiconductor material has a magnitude of about 1017 particles per cm3. The contact areas for source and drain generally have a distance from one another of about 3 to 7 μm and a strip-shaped Schottky-contact area with a width of 0.5 to 2 μm lies between these two areas. Gallium arsenide is preferably considered as the semiconductor material for MESFET's. All the three areas have the same conductivity type.
For power MESFET's, the parasitic resistances at the contacts and in the semiconductor layer are to be kept small and a large voltage between source and drain area can be applied without an electrical puncture or breakthrough occurring in the semiconductor layer between these areas.
Up to now, this problem was solved in such manner that one provided a relatively thick semiconductor layer and applied the contact strip for the gate in a somewhat recessed area of the semiconductor layer. It was thereby achieved that the semiconductor layer has a small thickness below the contact strip serving as the gate required for the function of a MESFET. The thicker layer parts beyond the gate area contribute to a reduction of the parasitic resistances. It has likewise been suggested to provide both the source area as well as the drain area with an increased doping of, for example, 1018 particles per cm3. Accordingly, the contact resistance between the material of the semiconductor layer and the contact metallization located thereon was reduced by the ohmic junction, the path resistance was reduced in the semiconductor layer, and higher voltages could be applied. Moreover, by so doing, the noise property could also be improved. Concerning this state of the art, the publications IEEE MT-24, 1976, 312-317; Proceedings of the 6th International Symposium concerning Gallium arsenide and Related Compounds, St. Louis (1976), Pages 262-270; and IEEE ED-24 (1977), 1129-1130 all incorporated herein by reference, are pertinent.
According to the IEEE ISSCC Digest of Technical Papers (1978), 118-119, incorporated by reference, good power MESFET's can also be achieved when the doping in the source area and in the drain area lies at only about 1017 particles per cm3 and the thickness of the semiconductor layer is selected correspondingly large.
An object of the present invention is to optimize a MESFET, particularly of the last-mentioned type, when it functions as a power-MESFET.
This object is inventively achieved in a MESFET wherein the drain area or zone is less highly doped than the gate area and the gate area is less highly doped than the source area. In the manufacturing of such metal-semiconductor field effect transistor, a mask is applied over a portion of a surface of the semiconductor layer where the drain zone is to be formed. A portion of the semiconductor layer adjacent the covered surface portion thereof, (i.e., a portion adjacent to an edge of the mask), is stripped away so as to create a step at such mask edge. Ion implantation for doping of the semiconductor layer at the uncovered surface thereof is then carried out from a first direction while the mask covers the drain zone but not the source and gate zones (i.e., so that only the source and gate zones are doped). Next, ion implantation is carried out from a second direction (generally at an oblique angle to the first direction) so that only the source zone is doped. During this second ion implantation step, the gate zone is not doped because of the shadowing effect provided by the mask edge and, of course, the drain zone is not doped because it is still covered by the mask. Either prior to the application of the mask or after the removal of the mask, all three zones, drain, gate and source zones, are commonly doped. This common doping of all three zones can occur prior to the first implantation step (i.e., prior to the doping of only the source and gate zones) or after the second implantation (i.e., when the mask is removed). In this manner, the resultant MESFET has a source zone with greater doping than a gate zone thereof while such gate zone has a greater doping than a drain zone thereof.
The invention proceeds from the consideration that the largest electric field strengths which could lead to a puncture occur in the MESFET between the gate and the drain area. It is therefore advantageous to provide a lower doping concentration in this area. It was determined that the electric resistance between the gate and drain areas thereby resulting has a relatively small influence on the amplification effect, and comparatively smaller than a resistance between the gate and the source area. For this reason, a degenerated (N+) doping is also advantageous for the source area according to a feature of the invention. Thus, the doping condition ND <NG <NS is to be fulfilled for the three areas of the drain, of the gate and of the source which have distances from one another which lie at a few μm.
FIG. 1 shows a MESFET of the invention; and
FIGS. 2 through 6 show individual process steps in manufacturing the MESFET.
An inventive MES-field effect transistor located in a semiconductor layer 2 is designated 1. The semiconductor layer 2 preferably consisting of gallium arsenide is located on an electrically insulating substrate body 3. In particular high-impedance gallium arsenide or gallium arsenide which has been made semi-insulating is employed.
A drain area referenced with 11 is indicated by means of shading. On the drain area a metal contact referenced 12 is provided for the current supply. As a rule, the contact 12 is part of a printed line, for example, of a gold alloy, serving as a feed. An area of the semiconductor layer 2 functioning as a source area is noted by a further shading 13. A contact for this area is applied thereon corresponding to contact 12. 16 designates a metal strip, already mentioned above, which forms a gate (Schottky) metal-semiconductor contact on the semiconductor layer 2. A gate area 15, which is again noted by means of shading and which functions as an electrical control, is formed beneath this metal strip 16. This results because the different potentials at the source and drain areas are different than the potential of strip 16.
According to the invention, a doping distribution is provided in the MESFET 1, for example, for gallium arsenide, in which the doping in the drain area 11 amounts to less than 1017 particles per cm3. A doping of, for example, 1 to 4·1017 particles per cm3 is provided in the gate area 15. On the other hand, a doping of 1 to 8·1018 particles per cm3 is present in the source area 13. For a lower limit of the doping of the drain area 11, care must be taken that sufficient electrical conductivity is still present so that an unallowably large parasitic resistance does not occur. For the upper limit of the doping of the source area 13, care must be taken to see that the doping is not large such that crystal lattice defects compensate or at least negatively influence the intended doping. N doping for the areas or, respectively, regions is preferably provided, for example, for gallium arsenide.
As a rule, a lower doping of 1015 particles per cm3 or less is to be provided beyond the areas 11, 13 and 15. There, however, a doping can also be completely omitted or the layer can be etched away.
The manufacture of a MESFET in accordance with the invention preferably ensues as follows.
FIG. 2 shows the aforementioned substrate body 3 on which the semiconductor layer 2 consisting of, for example, gallium arsenide, silicon, or indium phosphide is located. In a first process step, this semiconductor layer 2 is first doped to such a degree, for example, in the manufacturing process of layer 2 or by means of a succeeding diffusing-in or of an entire surface ion implantation, that the doping present for the drain area 11 is not more than 1017 particles per cm3.
The arrows 21 indicate, for example, an ion implantation process for the production of the doping of this process step.
FIG. 3 shows the substrate body 3 with the semiconductor layer 2 located on it and upon which a coating or mask 22 is located which covers a portion of the surface of the semiconductor layer 2. Therefore, the area of the semiconductor layer 2 is covered in which the drain area 11 is located. This covering 22 can be produced with the assistance of a metal which is sputtered on or also by means of a photosensitive resist.
FIG. 4 shows the result of a further process by which a superficial erosion of the semiconductor layer 2 has been achieved. The thickness of the cut amounts, for example, to 20 nm. This leads to a step referenced 23 which, in a later processing step, serves as a recognition of the limit of the drain area 11 indicated by shading.
FIG. 5 again shows the substrate 3 with the semiconductor layer 2 located thereon and on which the coating 22 is still located. In the next process step, the semiconductor layer 2 is now further doped, in the area not covered by the covering 22, to the extent of the gate area doping of 1 to 4·1017 particles per cm3. This doping, for example, can again be undertaken with the help of an implantation. For this implantation, one must take care that no significant shadow effect ensues because of the covering 22. The implantation direction can be carried out as indicated by arrows 24 and 25 (and at directions lying inbetween).
The still higher doping of the source area with 1 to 8·1018 particles per cm3 is undertaken in a further implantation step with an implantation direction as indicated by arrows 26. For this implantation direction corresponding to the arrows 26, care must be taken that, as a function of the thickness of the shadowing edge of the covering 22, the doping is such that the shadowing effect causes an intermediate space to remain as seen in step 26 (toward the left in FIG. 6) which is not further doped (gate area 15 of the transistor according to FIG. 1).
In further process steps--not illustrated--the covering 22 is then removed and the contacts 12, 14 and 16 are applied.
In the execution of the inventive manufacturing process with implantation in all process steps, only the implantation direction need be changed between the individual process steps, for example, by means of angular rotation of the substrate body on its carrier. The doping substance can always remain the same.
The manufacturing process of an inventive MESFET can be changed according to a variation of the manufacturing process described above in such manner that the sequence of the doping steps of FIGS. 2, 5 and 6 is interchanged. For example, the implantation 26 of the source area (FIG. 6) can be undertaken first with the implantation according to FIG. 5 then being undertaken subsequently. According to another variation, the implantation 21 corresponding to that of FIG. 2, for example, can be undertaken after the process step of FIG. 6, namely, after removal of the covering 22. One need only take care that the inventive doping steps respectively exist in the individual areas or, respectively, regions in the final result.
According to a further embodiment of the inventive MESFET or, respectively, of the inventive manufacturing process, during or after the process step of FIG. 2, a merely superficial implantation, i.e. an implantation 40 existing in the semiconductor layer 2 with only a minimum penetration depth as shown in dotted lines in FIG. 2 is undertaken which leads to a (superficial) high doping in the magnitude of 1 to 8·1018 particles per cm3. Such a superficial additional doping leads to a reduction of the contact resistance between the metal contact 12 and the otherwise weakly doped drain area 11. The penetration depth of this increased doping is selected, in particular, in such manner that it does not exceed the dimension of the step shown in FIG. 2, so that this increased surface doping, i.e. this highly doped semiconductor material of the surface layer of the semiconductor layer 2 is already removed again by means of the process step of FIG. 4 outside of the drain area. A residue of the highly doped surface layer can also be stripped immediately before the application of the metal strip 16.
Although various minor modifications may be suggested by those versed in the art, it should be understood that I wish to embody within the scope of the patent warranted hereon, all such embodiments as reasonably and properly come within the scope of my contribution to the art.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4048712 *||Dec 1, 1975||Sep 20, 1977||Selenia-Industrie Elettroniche Associate S.P.A.||Processes for manufacturing semiconductor devices|
|US4089712 *||May 17, 1977||May 16, 1978||International Business Machines Corporation||Epitaxial process for the fabrication of a field effect transistor having improved threshold stability|
|US4111725 *||May 6, 1977||Sep 5, 1978||Bell Telephone Laboratories, Incorporated||Selective lift-off technique for fabricating gaas fets|
|US4193182 *||Mar 6, 1978||Mar 18, 1980||Hughes Aircraft Company||Passivated V-gate GaAs field-effect transistor and fabrication process therefor|
|US4232439 *||Nov 29, 1977||Nov 11, 1980||Vlsi Technology Research Association||Masking technique usable in manufacturing semiconductor devices|
|1||*||Fukuta et al. IEEE, vol. MTT-24, No. 6 (1976) pp. 312-317.|
|2||*||Hasegawa et al., IEEE Int'l. Solid State Circuits Conf. Digest Tech. Papers, (1978) pp. 118.|
|3||*||Ohata et al. IEEE-Trans. Electron Device, ED-24 (1977) 1129-1130.|
|4||*||Wemple et al. in Inst. Phys. Conf. Series No. 33b, 1977, Chapt. 5, pp. 262-270.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US4532698 *||Jun 22, 1984||Aug 6, 1985||International Business Machines Corporation||Method of making ultrashort FET using oblique angle metal deposition and ion implantation|
|US4558509 *||Jun 29, 1984||Dec 17, 1985||International Business Machines Corporation||Method for fabricating a gallium arsenide semiconductor device|
|US4581076 *||Apr 5, 1984||Apr 8, 1986||Itt Industries, Inc.||Selectively implanting GaAs semiconductor substrates through a metallic layer|
|US4640003 *||Sep 30, 1985||Feb 3, 1987||The United States Of America As Represented By The Secretary Of The Navy||Method of making planar geometry Schottky diode using oblique evaporation and normal incidence proton bombardment|
|US4771012 *||Jun 12, 1987||Sep 13, 1988||Matsushita Electric Industrial Co., Ltd.||Method of making symmetrically controlled implanted regions using rotational angle of the substrate|
|US4918027 *||Apr 27, 1988||Apr 17, 1990||Matsushita Electric Industrial Co., Ltd.||Method of fabricating semiconductor device|
|US5026655 *||Sep 21, 1989||Jun 25, 1991||Nec Corporation||Process of fabricating a heterojunction field effect transistor|
|US5399508 *||Jun 23, 1993||Mar 21, 1995||Vlsi Technology, Inc.||Method for self-aligned punchthrough implant using an etch-back gate|
|US5424229 *||Jun 3, 1994||Jun 13, 1995||Kabushiki Kaisha Toshiba||Method for manufacturing MOSFET having an LDD structure|
|USRE35036 *||Jan 14, 1993||Sep 12, 1995||Matsushita Electric Industrial Co., Ltd.||Method of making symmetrically controlled implanted regions using rotational angle of the substrate|
|U.S. Classification||438/179, 148/DIG.84, 257/E29.109, 438/944, 257/E29.317, 257/280, 257/286|
|International Classification||H01L21/265, H01L29/36, H01L21/338, H01L29/812, H01L29/80|
|Cooperative Classification||H01L29/36, H01L29/812, Y10S438/944, Y10S148/084|
|European Classification||H01L29/36, H01L29/812|